JPH05211176A - Field-effect transistor and manufacture thereof - Google Patents

Field-effect transistor and manufacture thereof

Info

Publication number
JPH05211176A
JPH05211176A JP887392A JP887392A JPH05211176A JP H05211176 A JPH05211176 A JP H05211176A JP 887392 A JP887392 A JP 887392A JP 887392 A JP887392 A JP 887392A JP H05211176 A JPH05211176 A JP H05211176A
Authority
JP
Japan
Prior art keywords
metal film
etched
scribe
metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP887392A
Other languages
Japanese (ja)
Inventor
Makoto Matsunoshita
誠 松野下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP887392A priority Critical patent/JPH05211176A/en
Publication of JPH05211176A publication Critical patent/JPH05211176A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a solder from adhering on the surface of an element by a method wherein a scribing region on the surface of an element formation finished semiconductor substrate is etched to form a first metal film to cover the scribing region and its vicinity and the periphery of a second metal film to cover the rear of the substrate is junctioned with the first metal film. CONSTITUTION:A scribing region on the surface of an element formation finished gallium-arsenic substrate 1 is etched and a scribe metal film 2 consisting of a gold plating is formed on this region. Then, the rear of the substrate 1 is etched or ground, is made thin until a flat part of the metal film 2 is exposed and a gold plating is selectively applied to this rear to form a rear metal film 3. Then, the metal film 2 on the scribing region is etched using this metal film 3 as a mask to complete a gallium-arsenic element. The film 2 and 3, to which tweezers come into contact at the time of adhesion of the element to a package, exist on the sides, which are positioned on the rear, of the side surfaces of the gallium-arsenic element, the adhesion area of the element is large, the element hardly exfolitates and a possibility of adhesion of a solder to the element surface is eliminated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電界効果トランジスタお
よびその製造方法に関し、特にマイクロ波帯用の高出力
GaAs電界効果トランジスタにおよびその製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a manufacturing method thereof, and more particularly to a high power GaAs field effect transistor for a microwave band and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来のGaAs電界効果トランジスタに
ついて、図3を参照して説明する。
2. Description of the Related Art A conventional GaAs field effect transistor will be described with reference to FIG.

【0003】ガリウム砒素基板1が表面周辺から水平に
形成されたスクライブ金属2および裏面に形成された裏
面金属3で包み込まれている。
A gallium arsenide substrate 1 is covered with a scribe metal 2 formed horizontally from the periphery of the front surface and a back surface metal 3 formed on the back surface.

【0004】ピンセットを用いてチップ(ダイ)をパッ
ケージ(容器)に接着するとき、非常にもろく割れ易い
ガリウム砒素基板1を保護する構造になっている。
When a chip (die) is bonded to a package (container) using tweezers, it has a structure for protecting the gallium arsenide substrate 1 which is very brittle and easily broken.

【0005】ピンセットでは両端を挟むので、ガリウム
砒素基板1から突き出しているスクライブ金属2および
裏面金属3に接触することになる。
Since both ends of the tweezers are sandwiched, they come into contact with the scribe metal 2 and the back surface metal 3 protruding from the gallium arsenide substrate 1.

【0006】[0006]

【発明が解決しようとする課題】図3において、スクラ
イブ金属2はガリウム砒素基板1との接着面積が小さい
ので密着力が弱い。両端からチップをつかむ力が加わる
と、ガリウム砒素基板1から突き出しているスクライブ
金属2および裏面金属3が裏面方向に曲がり、スクライ
ブ金属2が剥れてしまう。
In FIG. 3, since the scribe metal 2 has a small adhesion area with the gallium arsenide substrate 1, the adhesion is weak. When a force for gripping the chip is applied from both ends, the scribe metal 2 and the back surface metal 3 protruding from the gallium arsenide substrate 1 bend in the back surface direction, and the scribe metal 2 peels off.

【0007】また、チップをパッケージにマウントする
際に、チップをつかんだピンセットを微動させてソルダ
ーをなじませて接着する。そのときピンセットがソルダ
ーに接触すると、ピンセットがチップに接触するところ
が素子表面と同じ高さなので、ピンセットをつたってソ
ルダーが上ってきて素子の表面にソルダーが付着すると
いう問題が生じることがある。
Further, when the chip is mounted on the package, the tweezers holding the chip are finely moved to conform the solder and adhere. If the tweezers come into contact with the solder at that time, the place where the tweezers come into contact with the chip is at the same height as the surface of the element, so that there is a problem that the solder comes up through the tweezers and the solder adheres to the surface of the element.

【0008】[0008]

【課題を解決するための手段】本発明の電界効果トラン
ジスタは、素子形成が終了した半導体基板表面のスクラ
イブ領域がエッチングされ、前記スクライブ領域および
その近傍を覆う第1の金属膜が形成され、前記半導体基
板裏面を覆う第2の金属膜の周辺が前記第1の金属膜と
接合されているものである。
In the field effect transistor of the present invention, a scribe region on the surface of a semiconductor substrate on which element formation has been completed is etched, and a first metal film covering the scribe region and its vicinity is formed. The periphery of the second metal film that covers the back surface of the semiconductor substrate is joined to the first metal film.

【0009】また本発明の半導体装置の製造方法は、素
子形成が終了した半導体基板表面のスクライブ領域をエ
ッチングしたのち、前記スクライブ領域に第1の金属膜
を被着する工程と、前記半導体基板裏面をエッチングし
て前記スクライブ領域の前記1の金属膜を露出させる工
程と、前記半導体基板の裏面に選択的に第2の金属膜を
被着する工程と、前記第2の金属膜をマスクとして前記
スクライブ領域の前記第1の金属膜をエッチングする工
程とを含むものである。
According to the method of manufacturing a semiconductor device of the present invention, a step of etching a scribe region on the surface of a semiconductor substrate on which elements have been formed and then depositing a first metal film on the scribe region, and a back surface of the semiconductor substrate. Etching to expose the first metal film in the scribe region, selectively depositing a second metal film on the back surface of the semiconductor substrate, and using the second metal film as a mask. And a step of etching the first metal film in the scribe region.

【0010】[0010]

【実施例】本発明の第1の実施例について、図1(d)
を参照して説明する。
EXAMPLE FIG. 1D shows a first example of the present invention.
Will be described.

【0011】ガリウム砒素基板1の裏面側でスクライブ
金属2および裏面金属3が水平に突き出している。
A scribe metal 2 and a backside metal 3 are horizontally projected on the backside of the gallium arsenide substrate 1.

【0012】つぎに本発明の第1の実施例の製造方法に
ついて、図1(a)〜(d)を参照して説明する。
Next, a manufacturing method of the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (d).

【0013】はじめに図1(a)に示すように、素子形
成済みのガリウム砒素基板1のスクライブ領域を深さ3
0〜60μmエッチングする。つぎに約1μmの金めっ
きからなるスクライブ金属2を形成する。
First, as shown in FIG. 1A, the scribe region of the gallium arsenide substrate 1 on which elements have been formed has a depth of 3 mm.
Etching 0-60 μm. Next, a scribe metal 2 made of gold plating having a thickness of about 1 μm is formed.

【0014】つぎに図1(b)に示すように、ガリウム
砒素基板1の裏面をエッチングまたは研削してスクライ
ブ金属2の平坦部分が露出するまで薄くする。
Next, as shown in FIG. 1B, the back surface of the gallium arsenide substrate 1 is etched or ground to be thinned until the flat portion of the scribe metal 2 is exposed.

【0015】つぎに図1(c)に示すように、ガリウム
砒素基板1の裏面に選択的に金めっきして厚さ10〜3
0μmの裏面金属3を形成する。
Next, as shown in FIG. 1C, the back surface of the gallium arsenide substrate 1 is selectively plated with gold to a thickness of 10 to 3
A backside metal 3 of 0 μm is formed.

【0016】つぎに図1(d)に示すように、裏面金属
3をマスクとしてスクライブ領域のスクライブ金属2を
エッチングしてGaAs電界効果トランジスタが完成す
る。
Then, as shown in FIG. 1D, the scribe metal 2 in the scribe region is etched by using the back surface metal 3 as a mask to complete a GaAs field effect transistor.

【0017】つぎに本発明の第2の実施例について、図
2を参照して説明する。
Next, a second embodiment of the present invention will be described with reference to FIG.

【0018】本実施例では、ガリウム砒素基板1を薄く
するとき、スクライブ領域のガリウム砒素1を厚さ10
〜20μm残しておく。つぎに選択的にスクライブ領域
のガリウム砒素1をエッチングする。
In this embodiment, when the gallium arsenide substrate 1 is thinned, the gallium arsenide 1 in the scribe region has a thickness of 10
Leave ~ 20 μm. Next, the gallium arsenide 1 in the scribe region is selectively etched.

【0019】スクライブ領域の下にガリウム砒素1を残
すことにより、ガリウム砒素1表面からのスクライブ領
域のエッチング深さのばらつきを吸収することができる
ので、最初のスクライブ領域のエッチング精度の条件が
緩和される。
By leaving the gallium arsenide 1 under the scribe region, variations in the etching depth of the scribe region from the surface of the gallium arsenide 1 can be absorbed, so that the condition of the etching precision of the first scribe region is relaxed. It

【0020】[0020]

【発明の効果】ガリウム砒素素子をパッケージに接着す
るときピンセットが接触するスクライブ金属および裏面
金属が、ガリウム砒素素子側面の裏面側にある。そのう
えスクライブ金属の接着面積が大きく、しかも形状的に
はがれ方向の力が分散されるのでスクライブ金属がはが
れにくい。またピンセットとの接触の位置が素子表面よ
り低い位置にあり、ソルダーが素子表面まで上がりにく
いので、ソルダーが表面に付着する恐れがなくなった。
EFFECTS OF THE INVENTION The scribe metal and the back surface metal, which the tweezers contact when the gallium arsenide element is bonded to the package, are on the back surface side of the gallium arsenide element side surface. In addition, the scribe metal has a large adhesion area and the force in the peeling direction is dispersed in terms of shape, so that the scribe metal is difficult to peel off. Further, since the position of contact with the tweezers is lower than the surface of the element and the solder does not easily rise to the surface of the element, there is no risk of the solder sticking to the surface.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を工程順に示す断面図で
ある。
FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

【図2】本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the present invention.

【図3】従来の電界効果トランジスタを示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a conventional field effect transistor.

【符号の説明】[Explanation of symbols]

1 ガリウム砒素基板 2 スクライブ金属 3 裏面金属 1 gallium arsenide substrate 2 scribe metal 3 backside metal

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 素子形成が終了した半導体基板表面のス
クライブ領域がエッチングされ、前記スクライブ領域お
よびその近傍を覆う第1の金属膜が形成され、前記半導
体基板裏面を覆う第2の金属膜の周辺が前記第1の金属
膜と接合されている電界効果トランジスタ。
1. A scribe region on the surface of a semiconductor substrate after element formation is etched to form a first metal film covering the scribe region and its vicinity, and a periphery of a second metal film covering the back surface of the semiconductor substrate. A field effect transistor in which is bonded to the first metal film.
【請求項2】 素子形成が終了した半導体基板表面のス
クライブ領域をエッチングしたのち、前記スクライブ領
域に第1の金属膜を被着する工程と、前記半導体基板裏
面をエッチングして前記スクライブ領域の前記1の金属
膜を露出させる工程と、前記半導体基板の裏面に選択的
に第2の金属膜を被着する工程と、前記第2の金属膜を
マスクとして前記スクライブ領域の前記第1の金属膜を
エッチングする工程とを含む電界効果トランジスタの製
造方法。
2. A step of etching a scribe region on the surface of a semiconductor substrate on which element formation has been completed, and then depositing a first metal film on the scribe region, and etching the back surface of the semiconductor substrate to etch the scribe region of the scribe region. First metal film is exposed, a second metal film is selectively deposited on the back surface of the semiconductor substrate, and the first metal film in the scribe region is masked with the second metal film. And a method of manufacturing a field effect transistor including the step of etching.
JP887392A 1992-01-22 1992-01-22 Field-effect transistor and manufacture thereof Pending JPH05211176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP887392A JPH05211176A (en) 1992-01-22 1992-01-22 Field-effect transistor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP887392A JPH05211176A (en) 1992-01-22 1992-01-22 Field-effect transistor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05211176A true JPH05211176A (en) 1993-08-20

Family

ID=11704806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP887392A Pending JPH05211176A (en) 1992-01-22 1992-01-22 Field-effect transistor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05211176A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607182A (en) * 1983-06-25 1985-01-14 Toshiba Corp Manufacture of semiconductor device
JPS60127762A (en) * 1983-12-15 1985-07-08 Toshiba Corp Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607182A (en) * 1983-06-25 1985-01-14 Toshiba Corp Manufacture of semiconductor device
JPS60127762A (en) * 1983-12-15 1985-07-08 Toshiba Corp Semiconductor device and manufacture thereof

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Effective date: 19980623