JPH05210709A - Clock wiring designing system - Google Patents

Abstract

PURPOSE:To provide a clock wiring designing system capable of shortening a clock cycle. CONSTITUTION:A delay analyzing means 103 finds out the delay time allowance of all passes. A worst case pass detecting means 104 detects a pass having the worst delay time allowance among all the delay time allowance values. A clock skew adjusting time extracting means 105 finds out a difference between the worst delay time allowance among the pass succeeding to the worst case pass and the delay time allowance of the worst case pass. An additional delay time calculating means 106 finds out the optimum delay time to be added to a clock net connected to an FF arranged on the end point side of the worst case pass. A delay time adjusting art work pattern setting means 107 selects a delay time adjusting art work pattern most close to the found delay time and sets up the selected pattern in the FF arranged on the end point side of the worst case pass. A delay analyzing result updating means 108 recalculates the delay time allowance of the pass generating a change in a clock skew and updates a delay analyzing result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock wiring design system for LSI, PWB and the like.

[0002]

2. Description of the Related Art Conventionally, in the clock wiring design method of this type, in an automatic layout tool, the clock skew is reduced and the path length of the waste case path is shortened to reduce the path delay time. In general, the layout design and wiring design are performed for the purpose of shortening, and the clock wiring is generally not modified after the layout is completed. In particular, when it is necessary to shorten the clock cycle, instead of correcting the clock net wiring, the layout and wiring are manually corrected so as to shorten the path length of the waste case path. (Reference: Logic Information Processing CAD Society of Japan, issued March 20, 1981) An example of a conventional circuit configuration and a timing chart will be described with reference to FIG.

As shown in FIG. 4A, clock drivers 201-203, flip-flops 204-206 and gates are provided.
207 to 211 are placed, and then clock nets 212 to 211 are placed.
An example in which the nets on the path 214 and the paths 215 and 216 are wired will be described. Where clock nets 212-214
Are wired in equal length and the clock skew is 0,
It is assumed that the layout results are obtained such that the paths 215 and 216 are also wired by the shortest route. The delay analysis results show path 21
It is assumed that 5 is the worst case path with a delay time of 10 ns and the margin of the delay time is the smallest, and the next-stage path 21
It is assumed that the delay time of 6 is 6 ns.

In the example of FIG. 4A, since the clock skew is already 0, it cannot be further reduced, and the path length of the waste case path cannot be further shortened. The clock cycle is defined by the path path 215, and the clock cycle is 10 ns.
It cannot be shortened below. FIG. 4B shows the flip-flops when the clock cycle is 10 ns.
5, Waveforms of data at input terminals H01 and H02 of 206 and clock input terminals CK1 to CK of flip-flops 204 to 206
3 is a timing chart showing the waveform of the clock in 3. For simplification, here, it is assumed that there is no delay time in the circuit in the flip-flop and rounding of each waveform, and the flip-flop operates at the rising edge of the clock. As can be seen in this figure, 10 clock cycles
It cannot be made shorter than ns.

[0005]

In the above-mentioned conventional clock wiring design method, it is basically assumed that the clock skew is reduced. Therefore, when the clock cycle is shortened, the delay time of the waste case path is reduced. Needs to be small. However, since the clock cycle defines the delay time of the worst case path, there is a disadvantage in that the clock cycle cannot be made shorter than that delay time (performance is improved).

Further, there is a drawback that a large number of man-hours are required when the work of shortening the delay time of the waste case path is manually performed, and those for improving the performance are required especially in accordance with the large scale of the circuit. The number of man-hours is rapidly increasing because the number of repair work tends to increase.

[0007]

A first invention is an LSI,
In a clock wiring design method in a layout design such as a PWB, a flip-flop having a plurality of types of delay time adjusting artwork pattern provision installation areas for adding delay times to clock input terminals is provided, and connection information is provided. And an input means for inputting the layout result and the delay analysis information after the completion of the wiring processing including the layout processing of all the blocks including the flip-flop and the artwork pattern information for delay time adjustment and the clock net wiring. A delay analysis unit that determines the delay time margin of the path in the clock cycle given by the delay analysis information for all paths, and the worst of the delay time margins of the paths calculated by the delay analysis unit. A waste case for detecting a waste case path having a delay time margin And the delay time margin of the secondary waste case path having the worst delay time margin among the paths of the next stage of the waste case path detected by the waste case path detecting means and the waste case path detecting means. And the waste case detected by the waste case path detecting means.
A clock skew adjusting time extracting means for obtaining a difference between the delay time margin of the spat as a clock skew adjusting time, and the waste case path within the range of the clock skew adjusting time obtained by the clock skew adjusting time extracting means. Of additional delay time calculating means for calculating an optimum delay time to be added to the clock net connected to the clock input terminal of the flip-flop on the end side of A delay time adjusting artwork pattern setting means for selecting the delay time adjusting artwork pattern having a close delay time and setting it in the given setting area of the flip-flop on the end side of the worst case path; and the delay time. The delay due to the adjustment artwork pattern setting means Delay analysis result updating means for recalculating the delay time margin and updating the delay analysis result for the path whose clock skew has changed due to the installation of the inter-work adjustment artwork pattern, and the delay analysis result updating means for updating the delay analysis result updating means. Control means for restarting the worst case path detection means if there is another path having a delay time margin less than or equal to the delay time margin of the worst case path, and the provision installation area after execution of each means. And output means for outputting a layout result including

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a clock wiring design system which is an embodiment of the present invention.

In the clock wiring designing method of the present invention, the flip-flop has the original clock input terminal position (C in the figure) as shown in the flip-flop example 217 of FIG. 2C.
K ') and the clock input terminal position (CK in the figure) that is the target of automatic wiring are connected by an artwork pattern such as the default artwork pattern example 218. In particular, if no installation artwork pattern is specified, the default artwork pattern example 218 is installed on the clock input terminals of all flip-flops. Artwork patterns include
In addition, there are a plurality of patterns having additional delay times as shown in the examples 219 to 222 in FIG. 2D, which can be arbitrarily selected and installed.

According to the clock wiring design method of the present invention, FIG.
After the layout as shown in (a) is completed, the layout result information 111, the logical connection information 110, the delay time adjustment artwork pattern information 112, and the delay analysis information 113 are first inputted by the input means 102 shown in FIG. Next, the delay analysis means 103 performs an exhaustive delay analysis in a clock cycle of 10 ns, for example, to obtain delay time margins of all paths.
Based on the analysis result, the worst case path detecting means 10
4 detects the path 215 having the worst delay time margin of 0 ns as the worst case path. Next, by the clock skew adjustment time extraction means 105,
The next stage of the waste case path 215 (here, the path
216 only) with the worst delay time margin
The difference between the delay time margin of 4 ns of the stock case path 216 and the delay time margin of 0 ns of the waste case path 215 is 4 ns.
Is extracted as the clock skew adjustment time. next,
By the additional delay time calculating means 106, the delay time to be added to the clock net 213 connected to the clock input terminal CK2 of the end point side flip-flop 205 of the waste case path 215 within the range of the clock skew adjustment time 4 ns is 4 ns in the example of 4 ns. It is calculated as 2ns of / 2.

Next, the artwork pattern setting means 107 for delay time adjustment selects the artwork pattern 219 shown in FIG. 2D so that the additional delay time of 2 ns is added, and the clock input terminal is selected. Figure 3 on CK2
It is installed as shown in (e). The wiring obtained by merging the wiring result of the clock net 213 and the selectively installed artwork pattern 219 shown here is an example of the clock wiring capable of shortening the target clock cycle.

Next, the delay analysis result updating means 108 updates the delay time margins of the paths 215 and 216 to both become 2 ns. At this point, if the worst value (minimum value) of the delay time margins of all paths is 2 ns, the clock skew becomes a buffer even if the clock cycle is 8 ns, and the input terminals H01 and H02 of the flip-flops 205 and 206 are H02. Waveforms of the data and the original clock input terminals CK1 'to CK3' of the flip-flops 204 to 206
The timing chart showing the waveform of the clock in FIG. 3 is as shown in FIG. 3 (f), which shows that the circuit operates normally.

If the worst value (minimum value) of the delay time margin among all paths is 2 ns or less, the worst case path detecting means 10 is again passed through the control means 101.
Return to 4 and repeat the above processing for that waste case path to increase the delay time margin. In this way, the clock cycle can be shortened by the delay time margin of the worst case path.

The control means 101 in FIG. 1 controls all the means, and the output means 109 outputs the final layout result.

[0016]

As described above, the present invention intentionally uses the clock skew for the clock net to shorten the clock cycle (improve the performance) as compared with the delay time of the worst case path. There is an effect that can be. That is, it is effective in shortening the clock cycle as the circuit speed increases.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock wiring design method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a flip-flop configuration example and an artwork pattern example of the present embodiment.

FIG. 3 is a circuit configuration example and a time chart of the present embodiment.

FIG. 4 is a conventional circuit configuration example and a time chart.

[Explanation of symbols]

101 control means 102 input means 103 delay analysis means 104 worst case path detection means 105 clock skew adjustment time extraction means 106 additional delay time calculation means 107 delay time adjustment artwork pattern setting means 108 delay analysis result updating means 109 output means 110 logical connection information 111 layout result information 112 delay time adjustment artwork pattern information 113 delay analysis information

Claims (1)

[Claims] 1. A clock wiring design method in a layout design of an LSI, a PWB, or the like, which has an installation area for a plurality of types of delay time adjusting artwork patterns prepared in advance for adding a delay time to a clock input terminal. Equipped with flip-flops, connection information, artwork pattern information for delay time adjustment, layout processing of all blocks including the flip-flops, and layout result after completion of wiring processing including clock net wiring and delay analysis Input means for inputting information, delay analysis means for obtaining a delay time margin of the path in a clock cycle given by the delay analysis information for all paths, and delay of each path obtained by the delay analysis means The worst case path having the worst delay time margin among the time margins is detected. And a second waste case having the worst delay time margin among the paths next to the waste case path detected by the waste case path detecting means. Clock skew adjusting time extracting means for obtaining as a clock skew adjusting time the difference between the delay time allowance of the waste path and the delay time allowance of the waste case path detected by the waste case path detecting means; and the clock skew. The optimum delay time to be added to the clock net connected to the clock input terminal of the flip-flop on the end side of the waste case path within the range of the clock skew adjustment time obtained by the skew adjustment time extraction means. And an additional delay time calculating means for obtaining the maximum delay time calculated by the additional delay time calculating means. A delay time adjusting artwork pattern having a certain delay time, and setting the delay time adjusting artwork pattern on the end point side of the worst case path in the given installation area of the flip-flop; Delay analysis result updating means for recalculating the delay time margin and updating the delay analysis result for the path whose clock skew has changed due to the setting of the delay time adjusting artwork pattern by the adjusting artwork pattern setting means; Control means for restarting the worst case path detection means if there is another path having a delay time margin less than the delay time margin of the worst case path updated by the delay analysis result updating means; An output device for outputting the layout result including the provision installation area after executing each means. A clock wiring design method characterized by having steps.