JPH05207079A - Msk demodulation circuit - Google Patents

Abstract

PURPOSE:To always perform pull-in in the optimum state by operating first and second low frequency signal generators and inputting the output signals of the generators to a second adder when the output of a synchronous state discriminator is not set in a synchronous state. CONSTITUTION:When an MSK modulation signal is inputted to an input terminal 1 and no synchronous state is set, the output of a synchronous state detector 23 goes to 'LO', which turns on switches 25, 33. Therefore, a low frequency signal generated from a low frequency signal generation circuit 24 is inputted to an adder 26 in a carrier recovery circuit, and it is superimposed on the control signal of a voltage controlled oscillator 2 for carrier recovery, which controls the voltage controlled oscillator. Simultaneously, the low frequency signal generated from a low frequency signal generation circuit 32 is inputted to an adder 34 via the switch 33 in a clock reproduction circuit, and it is superimposed on the control signal of a voltage controlled oscillator 16 for clock reproduction, which controls the voltage controlled oscillator. When the synchronous state is set, the output of the synchronous state detector 23 goes to 'HI', which turns off the switches 25, 33, and stops the sweep of the voltage controlled oscillator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync pull-in device used in a demodulation circuit of a synchronous detection system for MSK (Minimum Shift Keying) signals.

[0002]

2. Description of the Related Art An MSK signal is a kind of FSK signal,
In the synchronous detection demodulation circuit, the well-known QPSK
Carrier regeneration and clock regeneration cannot be performed independently like signals. Details of the MSK demodulation circuit are disclosed in Japanese Patent Laid-Open No. 58-70664. That is, the PLL circuit for carrier regeneration and the PLL for clock regeneration
Circuit and two PLLs simultaneously lock to the input MSK signal. When synchronously detecting the MSK signal, it is necessary to reproduce this carrier,
In many cases, a carrier reproducing circuit using a PLL is required to have a reproducing ability over a wide frequency range. In such a case, Japanese Patent Laid-Open No. 62-136152 discloses a QPSK demodulation.
As disclosed in the publication, a synchronization detection circuit is provided to control the input frequency in an asynchronous state, and the voltage control oscillator is swept to artificially widen the synchronization frequency range.

Generally, it is difficult to detect the carrier synchronization of a digital modulation signal.
As disclosed in 6152, it is performed depending on whether or not the block sync signal is correctly detected by the sync pattern detection circuit of the digital signal processing circuit connected to the subsequent stage of the demodulation circuit. In the asynchronous state, the control voltage of the voltage controlled oscillator is used. Synchronous pull-in was performed by superimposing a low-frequency sweep signal.

According to the above-mentioned conventional technique, the apparent pull-in range can be widened even in the QPSK demodulation circuit having a narrow actual capture range, and particularly the pull-in frequency range sufficient for the frequency variation of the antenna converter at the time of satellite broadcast reception. Can be secured.

[0005]

However, the above-mentioned prior art relates to QPSK demodulation and is not sufficient for MSK demodulation, and when the received electric field strength is weak and there is much noise, that is, when the received C / N is bad. No consideration has been given to the response. In digital modulation broadcasting or the like that uses satellites with low transmission power such as communication satellites, it is necessary to downsize the receiving antenna, and the receiving C / N tends to deteriorate. In such a case, there is a problem that the optimum state for synchronization pull-in and the state for minimizing the error rate during reception are different, and if the error rate is emphasized, the synchronization pull-in is not optimal.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a synchronous pull-in device for an MSK demodulation circuit capable of pulling in a noisy signal in an optimum state.

[0007]

The above object can be achieved by configuring the demodulation circuit as follows. That is, the clock recovery PLL as well as the carrier recovery PLL circuit
A low-frequency signal generator and an adder are also provided in the circuit, and the control signal of the voltage-controlled oscillator of the clock recovery circuit and the output signal of the low-frequency signal generator are added in the same way as the carrier recovery circuit during the pull-in operation performed in the asynchronous state. By performing sweep control of the voltage-controlled oscillator in this way, it is possible to perform the pull-in operation of the MSK demodulator circuit in which the clock regenerator circuit and the carrier regenerator circuit are simultaneously in the synchronized state without operating the loop gain of the system. After the synchronization is pulled in, the output of the low frequency signal generator of the carrier recovery circuit and the clock recovery circuit is stopped by receiving the output of the synchronization state detector, so that the demodulation operation can be performed in the best error rate state.

[0008]

Generally, in a PLL circuit, its capture range is proportional to the product of the loop gain and the loop filter band. In a quadrature synchronous detection circuit for a digital angle modulation signal such as QPSK, the capture range of a carrier reproduction PLL circuit is generally expanded in order to improve its pull-in response characteristic. The same can be considered for the quadrature synchronous detection of the MSK, but in the quadrature synchronous detection of the MSK, the product signal of the in-phase component and the quadrature component after the quadrature detection is multiplied by the clock signal in the carrier recovery circuit and the voltage controlled oscillator is passed through the loop filter. Therefore, it is necessary to lock the carrier recovery PLL circuit and the clock recovery PLL circuit at the same time in the synchronization pull-in. Therefore, a method of increasing the loop gain or expanding the loop filter band can be considered in order to expand the capture range of both the carrier recovery circuit and the clock recovery circuit, but if the C / N is poor and there is much noise, the system noise is increased. As a result, it is impossible to obtain a sufficient effect.

PLL for carrier recovery and clock recovery
The carrier recovery circuit and clock recovery circuit are synchronized at the same time by sweeping the voltage controlled oscillator of the carrier recovery circuit and clock recovery circuit without expanding the loop gain or loop filter band of the circuit and expanding the capture range. Ideally, the synchronization pull-in of the MSK demodulation circuit can be performed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, 1 is an input terminal, 2 is a carrier reproduction voltage controlled oscillator, 3 is a first multiplier, 4 is a second multiplier, 5
Is a 90-degree phase shifter, 6 is a first low-pass filter (LP
F), 7 is the second LPF, 20 is the first determination circuit, 21
Is a second determination circuit, and 20 and 21 are A / D converters in FIG. 1, but may be composed of a voltage comparator and a latch circuit. 22 is an inverting circuit. Reference numeral 8 is a third multiplier, 9 is a fourth multiplier, 10 is a first loop filter, and 1 to 10 form a carrier recovery circuit. 11 is the fifth
Multiplier, 12 is a sixth multiplier, 13 is a differential amplifier, 1
4 is a seventh multiplier, 15 is a second loop filter, 16
Is a voltage controlled oscillator for clock reproduction, 17 is a frequency dividing circuit, 18 is an inverting circuit, 19 is a latch circuit, and 11 to 19 form a clock reproducing circuit. Reference numeral 23 is a synchronization state detector, 24 is a first low frequency generation circuit, 25 is a switch, and 26 is a first adder. 32 is a second low frequency generation circuit, 33 is a switch, and 34 is a second adder.

In FIG. 1, it is assumed that an MSK modulation signal having a transmission frequency of 24.576 Mbps and a carrier frequency of 140 MHz is input to the input terminal 1. 2 is 140M
It is a voltage controlled oscillator centering on Hz, 5 is 140M
It is a phase shifter that shifts a 90-degree phase of Hz. 16 is 2
It is a voltage controlled oscillator centering on 4.576MHz,
A clock signal of 12.288 MHz is reproduced at the output of the frequency dividing circuit of 17.

When the MSK modulation signal is input to the input terminal 1 and is not in the synchronization state, the output of the synchronization state detector 23 is "L".
Then, the switches 25 and 33 are turned on and the low frequency signal of about 6 Hz generated from the low frequency signal generation circuit 24 is input to the adder 26 via the switch 25. The voltage control oscillator is controlled by being superposed on the control signal of the carrier reproduction voltage control oscillator 2. At the same time, the low frequency signal of about 24 Hz generated from the low frequency signal generation circuit 32 is passed through the switch 33 to the clock reproduction circuit. The voltage control oscillator is controlled by being input to the adder 34 and superposed on the control signal of the clock recovery voltage control oscillator 16. To lock the two PLL circuits of the carrier recovery circuit and the clock recovery circuit at the same time as in the MSK demodulation circuit. Set the sweep frequency of one voltage-controlled oscillator to the sweep frequency of the other voltage-controlled oscillator from several times to more than ten times. Failure to perform efficiently sweep within each capture range. The required specifications capture range of generally the clock recovery circuit is narrow,
The required specifications of the capture range of the carrier reproduction circuit are wide. Therefore, it is advantageous to increase the sweep frequency of the voltage controlled oscillator of the clock recovery circuit.

When the output frequencies of both voltage controlled oscillators match the input frequency, phase control of the system is performed and the carrier recovery circuit and the clock recovery circuit are simultaneously in the synchronized state.
When the synchronous state is established, the output of the synchronous state detector 23 is "H".
I ", the switches 25 and 33 are turned off and the sweep of the voltage controlled oscillator is stopped. As a result, even when the C / N of the input signal is bad, the pulling is efficiently performed, and after the synchronization state, the best error rate demodulation is performed. In addition, the two voltage-controlled oscillators are swept-controlled to perform the pull-in operation, so that the offset voltage generated by system temperature changes, changes over time, changes in adjustment parts due to vibration, etc. There is also an effect that the pull-in operation can be stabilized even with respect to the frequency shift of the voltage-controlled oscillator that is caused.

FIG. 2 shows another embodiment of the present invention. Figure 1
The difference is that the low frequency signals sweeping the voltage controlled oscillators of the clock recovery circuit and the carrier recovery circuit are not independent, but the phase relationship is fixed. In FIG. 2, reference numeral 24 is a low frequency oscillating circuit with a square wave output of about 24 Hz, 25 is a switch, and 35 is a frequency divider, which divides the frequency by 4. The output of the frequency divider 35 is a square wave of 6 Hz, 36 is a low-pass filter that makes a square wave close to a triangular wave or a sine wave, and 37 is a low-pass filter that makes a square wave of 24 Hz close to a triangular wave or a sine wave. is there.
With this configuration, the phase relationship between the signals for sweeping the voltage-controlled oscillators of the carrier recovery circuit and the clock recovery circuit is established, and the efficiency of the acquisition can be further improved. The operation and effect are similar to those in the case of FIG.

FIG. 3 shows another embodiment of the present invention. Figure 3
Then, the carrier frequency of the MSK modulation signal input terminal 27 is 4
It is 02.78 MHz. A heterodyne circuit is composed of 28 mixers, 30 voltage controlled oscillators, and 29 band pass filters (BPF). 1 is different from FIG.
It serves as a fixed reference oscillator of 40 MHz, and the output of the first loop filter 10 controls the voltage controlled oscillator 30 centered at 542.78 MHz. 29 is a BPF having a center frequency of 140 MHz, and the output signal of 29 is the same as the signal of the input terminal 1 of FIG. A feature of such a heterodyne system is that even if the input frequency is deviated, a carrier centered at 140 MHz can be obtained accurately, and the details thereof are disclosed in Japanese Patent Laid-Open No. 63-30049. Also in the MSK demodulation circuit having the circuit configuration shown in FIG. 3, similar to FIG. 1, the first and second low frequency signal generators 2 are provided.
By providing the switches 4, 32, the switches 25, 33 and the adders 26, 34, the same effect as in FIG. 1 can be obtained.

FIG. 4 shows still another embodiment of the present invention. What is different from FIG. 3 is that the low frequency signals sweeping the voltage controlled oscillators of the clock recovery circuit and the carrier recovery circuit are not independent, but the phase relationship is fixed. In FIG. 4, reference numeral 24 is a low-frequency oscillation circuit having a square wave output of about 24 Hz, reference numeral 25 is a switch, and reference numeral 35 is a frequency divider, which divides the frequency by four. The output of the frequency divider 35 is a square wave of 6 Hz, 36 is a low-pass filter that makes a square wave close to a triangular wave or a sine wave, and 37 is a low-pass filter that makes a square wave of 24 Hz close to a triangular wave or a sine wave. is there. With this configuration, the phase relationship between the signals for sweeping the voltage-controlled oscillators of the carrier recovery circuit and the clock recovery circuit is established, and the efficiency of the acquisition can be further improved. The operation and effect are similar to those in the case of FIG.

[0017]

As described above, according to the present invention, in the synchronous detection type MSK demodulation circuit in which the carrier regenerating circuit and the clock regenerating circuit are locked at the same time, even if a signal with a bad C / N and a lot of noise is synchronized, In the pull-in, the characteristics of the system remain in the best error rate state, the sweep control of the voltage-controlled oscillators of both the carrier regeneration circuit and the clock regeneration circuit is performed to perform the pull-in efficiently, and after the synchronous pull-in, the sweep is stopped, Since the demodulation can be performed in the best error rate state, an ideal MSK demodulation circuit can be realized. Further, there is an effect that the pull-in can be stably performed even with respect to the frequency shift of the voltage controlled oscillator due to the offset voltage.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

1 ... Input terminal, 2 ... Carrier controlled voltage controlled oscillator, 1
0 ... First loop filter, 1 to 10 ... Carrier regeneration circuit, 15 ... Second loop filter, 16 ... Clock regeneration voltage controlled oscillator, 11 to 19 ... Clock regeneration circuit, 23 ... Synchronous state detector, 28 ... Mixer, 30 ... Voltage controlled oscillator, 29 ... Bandpass filter (BPF), 2
4 ... Low frequency signal generator, 25 ... Switch, 26 ... Adder, 31 ... Reference signal oscillator, 32 ... Low frequency signal generator,
33 ... Switch, 34 ... Adder, 35 ... Divider, 36,
37 ... Low-pass filter (LPF).

Claims (6)

[Claims] 1. A synchronous detection type MSK demodulation circuit having a voltage controlled oscillator, a quadrature detector, a carrier recovery circuit, a clock recovery circuit, a synchronization state discriminator, a first low frequency signal generator and a first adder. And when the output of the synchronization state discriminator indicates that it is not in the synchronization state, the first low frequency signal generator is operated to superimpose this output signal on the control signal of the voltage controlled oscillator. MSK to perform synchronous pull-in
In the demodulation circuit, the clock recovery circuit includes a second low-frequency signal generator and a second adder, and when the output of the synchronization state discriminator is not in the synchronization state, the clock signal is generated together with the first low-frequency signal generator. An MSK characterized by operating a second low frequency signal generator, inputting this output signal to the second adder, superimposing it on the control signal of the voltage controlled oscillator of the clock recovery circuit, and performing synchronization pull-in. Demodulation circuit. 2. The MSK demodulation circuit according to claim 1, wherein the output frequency of the second low frequency signal generator is several times higher than the output frequency of the first low frequency signal generator. 3. The second low frequency signal generator according to claim 1, wherein the output frequency of the second low frequency signal generator is several times higher than the output frequency of the first low frequency signal generator. An MSK demodulation circuit, wherein a phase relationship between an output signal of the signal generator and an output signal of the first low frequency signal generator is in a synchronized state. 4. The carrier according to claim 1, further comprising a reference oscillator corresponding to an intermediate frequency, a mixer, a voltage-controlled local oscillator, and an intermediate frequency filter, wherein the carrier reproduction circuit performs quadrature detection on the carrier signal. The voltage-controlled local oscillator is controlled through a loop filter by a multiplication output signal of the multiplication result of the in-phase component and the quadrature component and a signal obtained by shifting the clock signal obtained by the clock recovery circuit by 90 degrees, and the voltage-controlled local oscillator is controlled. The output signal of the local oscillator is input to the mixer, the output of the mixer is input to the intermediate frequency filter, the output signal of the intermediate frequency filter, the output signal of the reference oscillator corresponding to the intermediate frequency, and the intermediate frequency. An MSK demodulation circuit, wherein a quadrature detection output is obtained by multiplying an output signal of a reference oscillator which is shifted by 90 degrees. 5. The MSK demodulation circuit according to claim 4, wherein the output frequency of the second low frequency signal generator is several times higher than the output frequency of the first low frequency signal generator. 6. The output frequency of the second low frequency signal generator is several times higher than the output frequency of the first low frequency signal generator, and the second low frequency signal generator of claim 4. An MSK demodulation circuit, wherein a phase relationship between an output signal of the signal generator and an output signal of the first low frequency signal generator is in a synchronized state.