JPH05207066A - Line state recognizing system - Google Patents

Abstract

PURPOSE:To eliminate the noncoincidental state of a line by performing the management of a line state in a packet switching machine by sending out a data group representing the line state again to a high-order processor when the noncoincidental state of the line occurs. CONSTITUTION:Low-order processors B, C read out memory F, G, and send out the data group 1 representing the state of an accommodating line in its own processor to the high-order processor A as a signal at every constant period and when a state changes, and the high-order processor A sends out the data group 2 to the low-order processors B, C as a response to the signal 1 reading out and recognizing the memory D, E. The low-order processors B, C analyze the line state when receiving the data group 2 representing a high-order processor managing lined send out the data group representing the state of the accommodating line and a state noncoincidental occurrence signal 3 to the high-order processor A when state noncoincidence is detected. The high-order processor A, after changing the line state of the processor, sends out the data group 4 representing the line state to the low-order processors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch composed of a plurality of processors, and more particularly to a line state recognition system between a higher processor and a lower processor.

[0002]

2. Description of the Related Art Conventionally, in a packet switch composed of a plurality of processors of this type, even if a state mismatch occurs between a high-order processor and a low-order processor, there is no means for recognizing the mismatch state, and there is no match. The condition could not be resolved.

[0003]

In the conventional packet switch composed of a plurality of processors, even if a line state mismatch occurs between the upper processor and the lower processor,
Since there is no means for recognizing the state inconsistency, there is a problem that the line state inconsistency cannot be resolved.

[0004]

According to the line state recognition method of the present invention, the state of a line accommodated in a lower processor is sent as information to a higher processor at regular intervals and when the state changes, and a higher processor responds to this. Then, the information on the line status of the lower processor accommodating that it recognizes is sent to the lower processor. The lower processor analyzes this response information, and when the state mismatch is detected, the lower processor again sends the line status information and the information indicating the state mismatch detection to the upper processor. Further, the upper processor changes the state of the lower processor management line which it recognizes as receiving these pieces of information.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a signal sending state when the line states match, and FIG. 2 is a block diagram showing a signal sending state when the line states do not match.

The lower processors B and C read the memories F and G and read the data group 1 indicating the state of the line accommodated in the own processor at regular intervals and when the state changes.
On the other hand, the upper processor A reads the memories D and E, and, in response to the signal 1 recognized by the upper processor A, sends the data group 2 indicating the corresponding processor line state to the lower processors B and C. (Fig. 1). FIG. 3 shows the inside of the memory. Lower processor B, C
Analyzes the line status when receiving the data group 2 indicating the upper processor management line status, and sends the data group indicating the accommodated line status and the status mismatch occurrence signal 3 to the upper processor A again when the status mismatch is detected. To do. Upon receiving the signal 3, the upper processor A changes the line state of the relevant processor and then sends the data group 4 indicating the line state to the lower processor (FIG. 4).

[0008]

As described above, according to the present invention, the accommodating line state is sent from the lower processor to the upper processor at regular intervals and when the state changes, and the upper processor responds to the signal with the corresponding processor line state to the lower processor. The lower processor recognizes the state of the upper processor and notifies the upper processor when the state mismatch is detected.
The effect is that the states can be matched.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal transmission state when line conditions match in an embodiment of the present invention.

FIG. 2 is a block diagram showing a signal transmission state in the case where the line states do not match in the embodiment.

3 is a diagram showing the inside of a line status memory F. FIG.

[Explanation of symbols]

A Upper processor B, C Lower processor D Lower processor B Corresponding line state storage memory E Lower processor C Corresponding line state storage memory F Lower processor B accommodated line state storage memory G Lower processor C accommodated line state storage memory 1 Lower processor accommodated line state Data group signal 2 indicating the line state of the upper processor management 3 Data group signal indicating the state of the lower processor accommodating line when a state mismatch occurs 4 Data group signal a, b indicating the state of the corresponding processor line after state change , C, d Lower processor accommodating line e Line a corresponding line state storage memory area f Line b corresponding line state storage memory area

Claims (1)

[Claims] 1. A packet switch comprising a plurality of processors including a lower processor having a line-corresponding processing function and an upper processor having a higher-level protocol processing function, wherein each upper processor and each lower processor have a lower processor. A memory for storing the data for managing the line status of the line accommodated in is provided, and the lower processor sends a data group indicating the line status of its own processor to the upper processor at regular intervals and when the line status changes, As a response to the transmission of this data group, the upper processor sends to the lower processor a data group indicating the lower processor accommodating line state under the control of its own processor, and the lower processor analyzes the line state response data from this upper processor, and the line state does not match. If again the line Line status recognition method which is characterized in that the packet switching equipment of line state management by sending a group of data indicating the state to the host processor.