CN110784376A - Equipment with Ethernet PHY register detection function, detection method and device - Google Patents
Equipment with Ethernet PHY register detection function, detection method and device Download PDFInfo
- Publication number
- CN110784376A CN110784376A CN201911024089.4A CN201911024089A CN110784376A CN 110784376 A CN110784376 A CN 110784376A CN 201911024089 A CN201911024089 A CN 201911024089A CN 110784376 A CN110784376 A CN 110784376A
- Authority
- CN
- China
- Prior art keywords
- register
- phy
- detected
- detection
- configuration information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Small-Scale Networks (AREA)
Abstract
The embodiment of the invention discloses equipment with an Ethernet PHY register detection function, a detection method and a device, wherein the equipment comprises: the system comprises a Central Processing Unit (CPU) and an automatic scanning device connected with the CPU, wherein a PHY chip is connected with the automatic scanning device and at least comprises a PHY register; CPU, is used for sending and detecting the configuration information to the automatic scanning device; and the automatic scanning device is used for determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected. After the automatic scanning device in the device acquires the detection configuration information sent by the CPU, the PHY register to be detected is mainly determined by the automatic scanning device according to the detection configuration information, and the determined PHY register to be detected is automatically detected, so that the utilization rate of the CPU is reduced, the performance of detection equipment is improved, and the actual requirements of users are met.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to equipment with an Ethernet PHY register detection function, a detection method and a detection device.
Background
The ethernet device is the necessary core hardware for products such as servers and switches. When a bottom Layer developer encounters abnormal problems such as inconsistent data packet transmission and reception, packet loss in large data volume, and the like, it needs to read and write a register of a lower Layer part (media access Control, MAC) of a data link Layer in a local area network, and also needs to read and write a register of a Physical Layer (PHY) in an OSI model.
At present, when a detection system is used for detecting the state of a PHY register, a software rotation training method is generally adopted, and CPU equipment is used for directly detecting the state, and when the CPU equipment is used for directly detecting the PHY register in real time, the utilization rate of the CPU is increased, so that the performance of the system is affected, and therefore, the detection system in the prior art cannot meet the actual requirements of users.
Disclosure of Invention
The embodiment of the invention provides equipment with an Ethernet PHY register detection function, a detection method and a detection device. When the PHY register is detected, excessive resources of a central processing unit are not occupied, so that the performance of detection equipment is improved, and the actual requirements of users are met.
In a first aspect, an embodiment of the present invention provides an apparatus with an ethernet PHY register detection function, including: the system comprises a Central Processing Unit (CPU) and an automatic scanning device connected with the CPU, wherein a PHY chip is connected with the automatic scanning device and at least comprises a PHY register;
CPU, is used for sending and detecting the configuration information to the automatic scanning device;
and the automatic scanning device is used for determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected.
In a second aspect, an embodiment of the present invention provides a detection method, which is applied to the above device with an ethernet PHY register detection function, and includes:
acquiring detection configuration information;
and determining the PHY register to be detected according to the detection configuration information, and detecting the PHY register to be detected.
In a third aspect, an embodiment of the present invention provides an apparatus with an ethernet PHY register detection function, including:
the acquisition module is used for acquiring detection configuration information;
and the detection module is used for determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected.
According to the technical scheme of the embodiment of the invention, after the automatic scanning device acquires the detection configuration information sent by the CPU, the PHY register to be detected is determined according to the detection configuration information through the automatic scanning device, and the determined PHY register to be detected is automatically detected, so that the utilization rate of the CPU is reduced, the performance of the detection equipment is improved, and the actual requirements of users are met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a device with an ethernet PHY register detection function according to an embodiment of the present invention;
fig. 2(1) is a schematic structural diagram of an apparatus in which an automatic scanning device according to a second embodiment of the present invention is integrated in a switch chip;
fig. 2(2) is a schematic structural diagram of a device in which an automatic scanning apparatus according to a second embodiment of the present invention is disposed outside a switch chip;
FIG. 3 is a flowchart of a detection method according to a third embodiment of the present invention;
fig. 4 is a block diagram of an apparatus with an ethernet PHY register detection function according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of a device with an ethernet PHY register detection function according to an embodiment of the present invention, where the embodiment is applicable to a case of detecting a PHY register.
Optionally, the device with the ethernet PHY register detection function in this embodiment may include: the system comprises a central processing unit CPU11 and an automatic scanning device 12 connected with the CPU, wherein a PHY chip is connected with the automatic scanning device 12 and at least comprises a PHY register; a CPU for sending detection configuration information to the automatic scanning apparatus 12; and the automatic scanning device 12 is configured to determine the PHY register to be detected according to the detection configuration information, and detect the PHY register to be detected.
Optionally, the automatic scanning device 12 is further configured to, after detecting the PHY register to be detected, compare the real value of the PHY register to be detected with the preset value of the PHY register to be detected to obtain a comparison result, and determine whether to send an interrupt signal to the CPU according to the comparison result.
Specifically, the device having the ethernet PHY register detection function may be a switch including a CPU and a switch chip, or may be a transmission device including a CPU and other communication chips. The automatic scanning device can be integrated in a switching chip or other communication chips, and can also be arranged outside the switching chip or other communication chips and realized by a singlechip, a field programmable gate array FPGA chip or a complex programmable logic device CPLD chip.
It should be noted that the number of PHY chips in this embodiment may be at least one, three PHY chips are taken as an example in fig. 1, and the number of PHY registers in each PHY chip may also be at least one, and two PHY chips are taken as an example in fig. 1. Of course, in this embodiment, it is not limited whether the number of PHY registers included in each PHY chip is the same.
Optionally, the automatic scanning device 12 includes: configuration structure 121, processing module 122 and result register 123, configuration structure 121 comprising: an address register 1211, an offset register 1212 and an expectation register 1213, wherein the processing module 122 is connected to the address register 1211, the offset register 1212, the expectation register 1213 and the result register 123, respectively; an address register 1211 for acquiring address information from the detection configuration information and transmitting the address information to the processing module 122; an offset register 1211 configured to obtain an offset amount from the detection configuration information and transmit the offset amount to the processing module 122; the processing module 122 is configured to determine a PHY chip to be detected according to the address information, and determine a PHY register to be detected in the PHY chip to be detected according to the offset; the expected register 1213 is configured to obtain a preset value of the PHY register to be detected from the detection configuration information, and transmit the preset value to the processing module 122; the processing module 122 is configured to read a real value of the PHY register to be detected, compare the real value with a preset value to obtain a comparison result, and determine whether to send an interrupt signal to the CPU according to the comparison result; and the result register 123 is used for acquiring the comparison result from the processing module and saving the comparison result.
Optionally, the automatic scanning device 12 further includes: an auto-scan enable register 125 and an interrupt enable register 124, the auto-scan enable register 125 being connected to the processing module 122, the interrupt enable register 124 being connected to the processing module 122; an auto-scan enable register 125 for configuring enabling and disabling of the processing module upon acquiring the detection configuration information; an interrupt enable register 124 for sending status information to the processing module 122; and the processing module 122 is specifically configured to generate an interrupt signal when the actual value is determined to be different from the preset value according to the comparison result, and the interrupt enable register is determined to be enabled according to the state information, and transmit the interrupt signal to the CPU.
It should be noted that, in this embodiment, the auto-scan apparatus may detect a plurality of states of the PHY chip, and each state is configured with one PHY register, so that the detection of a plurality of states of one PHY chip may be implemented, for example, for the PHY1 chip in fig. 1, the state stored in the PHY11 register is rate duplex, and the state stored in the PHY12 register is link/down. Of course, this embodiment is merely an example, and the specific type of the state corresponding to each PHY register is not limited.
In one specific implementation, the CPU only needs to send the detection configuration information set by the user to the auto-scan apparatus and perform the auto-detection operation by the auto-scan apparatus, if the address information obtained by the address register from the detection configuration information is address B, and address B corresponds to the PHY2 chip, the processing module may determine that the status of the PHY2 chip needs to be detected, if the offset obtained by the offset register from the detection configuration information is 1, the processing module may determine that the PHY21 register in the PHY2 chip needs to be detected, and the status corresponding to the PHY21 register is rate duplex, the processing module obtains the current real value of the rate duplex in the PHY21 register as 30, and the expected register obtains the preset value of the rate duplex of the PHY21 register as 40 from the detection configuration information, the processing module compares the real value with the preset value, and obtaining the comparison result to be different, generating an interrupt signal under the condition that the interrupt enabling register is enabled according to the state information sent by the interrupt enabling register, transmitting the interrupt signal to the CPU, and obtaining and storing the comparison result from the processing module by the result register. And after receiving the interrupt generated by the automatic scanning device, the CPU enters an interrupt processing program, and because a plurality of bits are arranged in the result register and each bit corresponds to one PHY register, the CPU determines the PHY register which specifically causes the interrupt by judging the change condition of the bit. Therefore, in the present embodiment, the automatic scanning device mainly detects the PHY register, normally does not occupy the CPU, and only if the PHY register is interrupted, the CPU is used to handle the interruption, so that the performance of the detection device is improved.
According to the technical scheme of the embodiment of the invention, after the automatic scanning device acquires the detection configuration information sent by the CPU, the PHY register to be detected is determined according to the detection configuration information through the automatic scanning device, and the determined PHY register to be detected is automatically detected, so that the utilization rate of the CPU is reduced, the performance of the detection equipment is improved, and the actual requirements of users are met.
Example two
Fig. 2 is a schematic structural diagram of a detection device for an ethernet physical layer PHY register according to a second embodiment of the present invention, which is embodied based on the foregoing embodiment, and in this embodiment, an auto-scanning apparatus is integrated in a switch chip or is disposed outside the switch chip.
Optionally, the automatic scanning device is integrated in the switch chip, or the automatic scanning device is arranged outside the switch chip and implemented by a single chip microcomputer, a field programmable gate array FPGA chip or a complex programmable logic device CPLD chip.
Optionally, the automatic scanning device is connected to the CPU through a control bus, and the automatic scanning device is connected to the PHY chip through a management data input/output MDIO bus.
In a specific implementation, fig. 2(1) shows a schematic structural diagram of an apparatus in which an automatic scanning apparatus is integrated in a switch chip 13, and fig. 2(2) shows a schematic structural diagram of an apparatus in which an automatic scanning apparatus is disposed outside the switch chip 13 and is implemented by a single chip microcomputer/FPGA/CPLD chip 14. Of course, this embodiment is only described as an example, and other devices capable of implementing the PHY register detection function are also within the scope of the present application, and the present application does not limit the specific configuration of the devices.
It should be noted that the automatic scanning device in this embodiment may be integrated in the switch chip, or may be disposed outside the switch chip, and implemented by a single chip, an FPGA, or a CPLD chip. And other functional modules can be included in the switching chip or the single chip, therefore, when detecting the PHY register, conflict detection can be carried out, when determining that other functional modules are also reading and writing the PHY register to be detected, and the PHY register can occupy the MDIO bus, in order to avoid read-write operation conflict, the automatic scanning device can stop detection at the moment, when the read-write tasks of other functional modules are completed, and the MDIO bus is idle, the PHY register detection can be automatically carried out, therefore, by setting the priority of the automatic scanning device to be low, the use conflict of the MDIO bus can be avoided, and simultaneously, the read-write of other modules is not influenced.
According to the technical scheme of the embodiment of the invention, after the automatic scanning device acquires the detection configuration information sent by the CPU, the PHY register to be detected is determined according to the detection configuration information through the automatic scanning device, and the determined PHY register to be detected is automatically detected, so that the utilization rate of the CPU is reduced, the performance of the detection equipment is improved, and the actual requirements of users are met. And the automatic scanning device can be integrated in the exchange chip or arranged outside the exchange chip and is realized by a single chip microcomputer, an FPGA (field programmable gate array) or a CPLD (complex programmable logic device) chip, when the PHY register is detected, MIDO (device-in-package) bus conflict detection can be carried out, task conflict caused by the MDIO bus operation with other functional modules is avoided, and the compatibility and the reliability of other modules are not influenced.
EXAMPLE III
Fig. 3 is a flowchart of a detection method according to a third embodiment of the present invention, which is applicable to a case of detecting a PHY register. The method may be performed by an apparatus having an ethernet PHY register detection function as provided in embodiment one or embodiment two. The method of the embodiment of the invention specifically comprises the following steps:
step 101, acquiring detection configuration information.
Specifically, in this embodiment, the CPU may specifically acquire the detection configuration information, and send the detection configuration information to the automatic scanning device in the detection device. The detection configuration information is set in advance by a user according to the detection requirement of the PHY register.
And step 102, determining the PHY register to be detected according to the detection configuration information, and detecting the PHY register to be detected.
Optionally, determining the PHY register to be detected according to the detection configuration information, and detecting the PHY register to be detected may include: determining a PHY register to be detected according to address information and offset contained in the detection configuration information; acquiring a preset value of a PHY register to be detected from the detection configuration information; reading the real value of the PHY register to be detected, comparing the real value with a preset value to obtain a comparison result, and storing the comparison result; and generating an interrupt signal when the real value is determined to be different from the preset value according to the comparison result.
Specifically, in this embodiment, the address register in the automatic scanning device obtains address information from the detection configuration information, the offset register obtains an offset from the detection configuration information, and the processing module obtains the address information and the offset and determines the PHY register to be detected. The expected register can acquire the preset value of the PHY register to be detected from the detection configuration information and transmit the preset value to the processing module. The processing module can read the real value of the PHY register to be detected after determining the PHY register to be detected, compare the read real value with the obtained preset value to obtain a comparison result, and transmit the comparison result to the result register for storage.
Optionally, determining the PHY register to be detected according to the detection configuration information, and before detecting the PHY register to be detected, the method may further include: carrying out MDIO bus conflict detection; and determining that no read-write operation exists for the PHY register to be detected currently.
Specifically, when the PHY register is detected, collision detection is performed, when it is determined that other functional modules are also reading and writing the PHY register to be detected and occupy the MDIO bus, in order to avoid a read-write operation collision, detection is stopped at this time, and PHY register detection is automatically performed when the MDIO bus is idle, so that by setting the priority of the automatic scanning device to be low, the occurrence of an MDIO use collision can be avoided, and reading and writing of other modules are not affected.
After the detection configuration information sent by the CPU is obtained, the PHY register to be detected is determined mainly through an automatic scanning device, and the determined PHY register to be detected is automatically detected, so that the utilization rate of the CPU is reduced, the performance of detection equipment is improved, and the actual requirements of users are met.
Example four
Fig. 4 is a device with ethernet PHY register detection function according to a fourth embodiment of the present invention, where the device includes: an acquisition module 410 and a detection module 420.
The acquisition module is used for acquiring detection configuration information;
and the detection module is used for determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected.
The device can execute the detection method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, reference may be made to the method provided in any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A device having ethernet PHY register detection functionality, comprising: the system comprises a Central Processing Unit (CPU) and an automatic scanning device connected with the CPU, wherein a PHY chip is connected with the automatic scanning device and at least comprises a PHY register;
the CPU is used for sending detection configuration information to the automatic scanning device;
and the automatic scanning device is used for determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected.
2. The device according to claim 1, wherein the auto-scan apparatus is further configured to, after detecting the PHY register to be detected, compare the real value of the PHY register to be detected with the preset value of the PHY register to be detected to obtain a comparison result, and determine whether to send an interrupt signal to the CPU according to the comparison result.
3. The apparatus of claim 2, wherein the auto-scanning device comprises: a configuration structure, a processing module and a result register, the configuration structure comprising: the device comprises an address register, an offset register and an expected register, wherein the processing module is respectively connected with the address register, the offset register, the expected register and the result register;
the address register is used for acquiring address information from the detection configuration information and transmitting the address information to the processing module;
the offset register is used for acquiring an offset from the detection configuration information and transmitting the offset to the processing module;
the processing module is used for determining a PHY chip to be detected according to the address information and determining a PHY register to be detected in the PHY chip to be detected according to the offset;
the expected register is used for acquiring the preset value of the PHY register to be detected from the detection configuration information and transmitting the preset value to the processing module;
and the processing module is used for reading the real value of the PHY register to be detected, comparing the real value with the preset value to obtain a comparison result, and determining whether to send an interrupt signal to the CPU according to the comparison result.
And the result register is used for acquiring the comparison result from the processing module and storing the comparison result.
4. The apparatus of claim 3, wherein the auto-scanning device further comprises: the system comprises an automatic scanning enabling register and an interrupt enabling register, wherein the automatic scanning enabling register is connected with the processing module, and the interrupt enabling register is connected with the processing module;
the automatic scanning enabling register is used for configuring enabling and disabling of the processing module when the detection configuration information is acquired;
the interrupt enabling register is used for sending state information to the processing module;
the processing module is specifically configured to generate the interrupt signal when the real value is determined to be different from the preset value according to the comparison result, and the interrupt enable register is determined to be enabled according to the state information, and transmit the interrupt signal to the CPU.
5. The apparatus according to claim 1, wherein the automatic scanning device is integrated in the switch chip, or the automatic scanning device is disposed outside the switch chip and implemented by a single chip, a Field Programmable Gate Array (FPGA) chip or a Complex Programmable Logic Device (CPLD) chip.
6. The apparatus of claim 3, wherein the auto-scan device is connected to the CPU via a control bus, and wherein the auto-scan device is connected to the PHY chip via a Management Data Input Output (MDIO) bus.
7. A detection method applied to the device with ethernet PHY register detection function according to any one of claims 1 to 6, comprising:
acquiring detection configuration information;
and determining the PHY register to be detected according to the detection configuration information, and detecting the PHY register to be detected.
8. The method according to claim 7, wherein the determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected comprises:
determining the PHY register to be detected according to the address information and the offset contained in the detection configuration information;
acquiring a preset value of the PHY register to be detected from the detection configuration information;
reading the real value of the PHY register to be detected, and comparing the real value with the preset value to obtain a comparison result;
and generating an interrupt signal aiming at the PHY register to be detected when the real value is determined to be different from the preset value according to the comparison result.
9. The method according to any one of claims 7 to 8, wherein determining the PHY register to be detected according to the detection configuration information, and before detecting the PHY register to be detected, further comprising:
carrying out MIDO bus collision detection;
and determining that no read-write operation exists for the PHY register to be detected currently.
10. An apparatus having an ethernet PHY register detection function, comprising:
the acquisition module is used for acquiring detection configuration information;
and the detection module is used for determining the PHY register to be detected according to the detection configuration information and detecting the PHY register to be detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911024089.4A CN110784376A (en) | 2019-10-25 | 2019-10-25 | Equipment with Ethernet PHY register detection function, detection method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911024089.4A CN110784376A (en) | 2019-10-25 | 2019-10-25 | Equipment with Ethernet PHY register detection function, detection method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110784376A true CN110784376A (en) | 2020-02-11 |
Family
ID=69386799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911024089.4A Pending CN110784376A (en) | 2019-10-25 | 2019-10-25 | Equipment with Ethernet PHY register detection function, detection method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110784376A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202818337U (en) * | 2012-07-24 | 2013-03-20 | 中国电力科学研究院 | An FPGA-based IEC61588V2 event message detector |
| CN103095367A (en) * | 2013-01-25 | 2013-05-08 | 中兴通讯股份有限公司 | Optical-fiber interface speed self-adapting method and optical-fiber network device |
| CN103957130A (en) * | 2014-04-08 | 2014-07-30 | 迈普通信技术股份有限公司 | Fault detection and recovery method and system |
| CN104320317A (en) * | 2014-10-28 | 2015-01-28 | 杭州华三通信技术有限公司 | Method and device for transmitting state of Ethernet physical layer chip |
| CN108737211A (en) * | 2018-05-16 | 2018-11-02 | 武汉微创光电股份有限公司 | A kind of method and device of detection PHY chip port status variation |
| US20190310856A1 (en) * | 2018-04-09 | 2019-10-10 | International Business Machines Corporation | Executing instructions based on a shared physical register |
-
2019
- 2019-10-25 CN CN201911024089.4A patent/CN110784376A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202818337U (en) * | 2012-07-24 | 2013-03-20 | 中国电力科学研究院 | An FPGA-based IEC61588V2 event message detector |
| CN103095367A (en) * | 2013-01-25 | 2013-05-08 | 中兴通讯股份有限公司 | Optical-fiber interface speed self-adapting method and optical-fiber network device |
| CN103957130A (en) * | 2014-04-08 | 2014-07-30 | 迈普通信技术股份有限公司 | Fault detection and recovery method and system |
| CN104320317A (en) * | 2014-10-28 | 2015-01-28 | 杭州华三通信技术有限公司 | Method and device for transmitting state of Ethernet physical layer chip |
| US20190310856A1 (en) * | 2018-04-09 | 2019-10-10 | International Business Machines Corporation | Executing instructions based on a shared physical register |
| CN108737211A (en) * | 2018-05-16 | 2018-11-02 | 武汉微创光电股份有限公司 | A kind of method and device of detection PHY chip port status variation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1263759A (en) | Arrangement for on-line diagnostic testing of an off- line standby processor in a duplicated processor configuration | |
| CN100365994C (en) | Method and system for regulating ethernet | |
| WO2002084469A2 (en) | Arrangement for reducing power in a networking device | |
| TWI516942B (en) | Assigning addresses to devices on an interconnect | |
| CN110535715B (en) | Linux-based port state real-time detection method, circuit and switch | |
| CN109408126A (en) | A kind of starting-up method of multipath server, BMC and multipath server | |
| CN111966189A (en) | Flexibly configured multi-computing-node server mainboard structure and program | |
| US20050080903A1 (en) | Method, system, and program for maintaining a link between two network entities | |
| US20200136912A1 (en) | Method, Device, and System for Implementing MUX Machine | |
| US6732212B2 (en) | Launch raw packet on remote interrupt | |
| US6868375B1 (en) | Emulation of dynamically reconfigurable computer system | |
| US4821179A (en) | Communication system configuration detection apparatus and method | |
| CN115756824B (en) | Out-of-band query/configuration method of processor information in server and server | |
| CN110784376A (en) | Equipment with Ethernet PHY register detection function, detection method and device | |
| KR20170117326A (en) | Direct memory access control device for at least one processing unit having a random access memory | |
| JP3401160B2 (en) | Distributed shared memory network device | |
| CN111858187A (en) | Electronic equipment and service switching method and device | |
| CN111817892B (en) | Network management method, system, electronic equipment and storage medium | |
| CN106506074A (en) | A kind of method and apparatus of detection optical port state | |
| CN111083072A (en) | Switch message transmission device and method | |
| US7180906B1 (en) | Method and apparatus for autopolling physical layer devices in a network | |
| US10795848B2 (en) | Dual way communication method, system, and master device thereof | |
| US6938078B1 (en) | Data processing apparatus and data processing method | |
| CN113312089B (en) | Low-cost high-efficiency inter-disc communication physical channel switching control system and method | |
| CN112015689B (en) | Method, system and device for switching serial port output paths and switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200211 |