JPH0520475A - Microprocessor incorporating peripheral lsi - Google Patents

Abstract

PURPOSE:To set an incorporated peripheral I/O address to an arbitrary I/O address without the aid of CPU by providing a means setting the I/O address of peripheral LSI incorporated from the external part of a microprocessor before the operation of incorporated CPU. CONSTITUTION:A setting information read circuit 200 reads information required for setting an incorporated peripheral relocation register 180 before CPU 11 starts an operation. The incorporated peripheral relocation register 180 is set based on information which the setting information read circuit 200 reads. The processing of incorporated CPU is started after the termination of setting the incorporated peripheral relocation register 180. Thus, it becomes unnecessary to newly add a program for setting the incorporated peripheral relocation register to existed software, and it becomes unnecessary to alter existed software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor with a built-in peripheral LSI in a microprocessor.

[0002]

2. Description of the Related Art NEC's V50 (K40-issued "V40 /
V50 Handbook "or NEC Data Book V
Series Microprocessor IA-126CMar
ch 1989P: For internal peripheral relocation register, see p404) and V53
(NEC Users Manual V53 (Provisional) I
See EU-680B August 1990 P: For the internal peripheral relocation register, see p78).
I / O address is set to an arbitrary I / O address by setting a register called a built-in peripheral relocation register by programming the CPU.

The prior art will be described with reference to the drawings.

A CPU (V33) 1 and peripheral LSIs (μPD71051 (2), μPD7105) as shown in FIG.
4 (3) and μPD71059 (4)) are configured as separate ICs using a microprocessor (V53) with a built-in peripheral LSI.
Shown in. FIG. 6 shows that the I / O address of the peripheral LSI is set by hardware and the I / O address decoding circuit 8 is set.
Then, the peripheral LSI select signal (21, 22, 22,
23) the peripheral LSI to be accessed by controlling 23) is selected. In FIG. 7, the CPU (equivalent to V33) 11 sets the built-in peripheral relocation register 18 of the microprocessor (V53) 100 with built-in peripheral LSI by programming. And set the I / O address of the built-in peripheral LSI. Then, the contents of the internal peripheral relocation register 18 and the CPU (equivalent to V33)
11 The I / O address being accessed is compared by the comparator 19, and the internal peripheral selection signals (31, 32, 3) are compared.
3) to select the built-in peripheral to access.

Built-in peripheral selection signals (31, 32,
The operation of controlling 33) will be described in detail with reference to FIG. C
When the PU (corresponding to V33) 11 starts a bus cycle, the comparator 19 sets the address bus / control bus 16 to I
The I / O access determiner 190 determines whether or not it is an I / O access, and the comparison circuit 191, comparison circuit 192,
The 51-address register 112 and 54-address register 11 of the built-in peripheral relocation register 18 that have already been set by the comparison circuit 193.
It is determined whether or not it matches with the 3, 59 address register 114. If the CPU (equivalent to V33) 11 is in a bus cycle for I / O access and the address output by the CPU (equivalent to V33) 11 matches the 51 address register 112 of the internal peripheral relocation register 18, the internal The peripheral selection signal 31 becomes active, and the μPD71005 equivalent 12 is accessed.

Similarly, the CPU (corresponding to V33) 11
The address output by the CPU (corresponding to V33) 11 in the O access bus cycle is the 54th address register 1 of the internal peripheral relocation register 18.
13 matches the internal peripheral selection signal 3
2 becomes active, and 13 corresponding to μPD71054 is accessed. In addition, the CPU (equivalent to V33) 11
The address output by the CPU (corresponding to V33) 11 in the O access bus cycle is 59 address register 1 of the internal peripheral relocation register 18.
If it matches 14, the built-in peripheral selection signal 3
3 becomes active and the μPD71059 equivalent 14 is accessed.

That is, in the conventional microprocessor having a built-in peripheral LSI, it is necessary to set the I / O address of the built-in peripheral by the program processing of the CPU.

[0008]

The existing software of the hardware, which is composed of the CPU and the peripheral in separate ICs, is reassembled by using the microprocessor incorporating the peripheral LSI, and the I / O address is the same address. If you want to use it after the start of the CPU as shown in the flow in Figure 2 (a),
By setting the internal peripheral relocation register, it is necessary to set the I / O address. Therefore, it is necessary to add a program for setting the built-in peripheral relocation register to the existing software. This causes a problem that the verification of the software itself has to be redone because the existing software needs to be modified to some extent.

This poses a serious problem in maintaining the independence of existing software.

[0010]

In a microprocessor in which a CPU and a peripheral LSI capable of arbitrarily setting an I / O address are built in one chip, a means for reading information from the outside of the microprocessor before the operation of the built-in CPU,
I / O of the peripheral LSI built in based on the read information
A means for setting an address is provided.

[0011]

FIG. 1 shows an embodiment of the present invention.

The I / O address of the built-in peripheral of the peripheral LSI built-in microprocessor consisting of the CPU and the built-in peripheral whose I / O address can be arbitrarily set
A function for reading information for setting the internal peripheral relocation register 180 from the outside into the microprocessor 101 with a peripheral LSI as shown in FIG. A setting information reading circuit 200 having a function of setting the built-in peripheral relocation register 180 by the read information is provided.

That is, as shown in the flow chart of FIG. 2B, after the power is turned on or the reset state is released,
Before the CPU (equivalent to V33) 11 starts to operate, the setting information reading circuit 200 has a serial ROM 300 (this serial ROM is an example of an XC1736 equivalent of XILINX. A programmable gate array of XILINX). Data Book MCD-X-DB0
7.1000 (2) p2-123) to read the information necessary for setting the built-in peripheral relocation register 180. Then, the built-in peripheral relocation register 180 is set based on the information read by the setting information reading circuit 200. Built-in peripheral relocation register 18
After the setting of 0 is completed, the processing of the built-in CPU is started.

The operation of the setting information reading circuit 200 is shown in FIG.
Use to explain in detail.

FIG. 3 is a diagram showing in detail the periphery of the setting information reading circuit 200 of the peripheral LSI built-in micro-processor 101. FIG. 4 shows the inverted signal 311 of RESET.
3 is a timing chart showing the movement of signals related to the setting information reading circuit 200 after being released. Also, FIG.
Is the internal peripheral relocation register 18
7 is a timing chart showing the movement of signals related to the setting information reading circuit 200 when the setting of 0 is completed.

As shown in the timing chart of FIG. 5, after the inversion signal 311 of RESET transits from the low state to the high state, the control signal generator 220 starts the operation and the external peripheral relocation register is externally set. In order to notify the outside that the information for setting is read, the inversion signal 203 of LOAD is made low active, and the CLKOUT signal 202 outputs a clock signal notifying the reading timing to the outside. On the serial ROM 300 side, since the inverted signal of RESET goes into the high state,
The OE inversion signal 304 of the serial ROM 300 becomes low active and the LOAD inversion signal 203
The inversion signal 303 of CE connected to is also active low, and the clock is input to the CLK signal 302 as the CLKOUT signal 202 outputs the clock signal. Therefore, the data from the serial ROM 300 is DAT.
It is output through the A signal 301. The output data is input to the serial / parallel converter 230 through the DIN signal 201 of the setting information reading circuit 200. The clock / counter unit 231 of the serial / parallel converter 230 counts the clock and the 1-byte data Then, the byte data is transferred to the internal peripheral relocation register 180, the WR inversion signal 232 is generated as the write timing, and the write timing is written to the write control circuit 181 of the internal peripheral relocation register 180. Tell. The write control circuit 181 writes the internal registers of the internal peripheral relocation register 180 in order using the write control lines 185, 186, 187.

Further, as shown in the timing chart of FIG. 4, when the setting of the built-in peripheral relocation register 180 is completed, the write control circuit 18
1 makes the END signal 182 high active to notify the setting information reading circuit 200 side that the setting is completed.

When the END signal 182 becomes high active, the control signal generator 220 finishes the process of reading the data from the outside, so that the inverted signal 20 of the LOAD is inverted.
3 inactive in the high state and CLKO
The output of the clock signal from the UT signal 202 also ends.

Further, when the END signal 182 becomes high active, the inversion signal 211 of CPU RESET becomes high inactive, the reset state of the CPU (corresponding to V33) 11 is released, and the CPU (corresponding to V33) 11 is released. The operation is started.

Another embodiment of the present invention is shown in FIG.

In the case of this embodiment, the microprocessor 102 with a built-in peripheral LSI is provided with a rewritable built-in EPROM 30 instead of the setting information reading circuit 200 of the embodiment. The built-in EPROM 30 sets the built-in peripheral relocation register 180 based on the setting information written in the built-in EPROM 30 before the CPU (corresponding to V33) 11 starts the operation, like the setting information reading circuit 200 of the embodiment. With function.

That is, in another embodiment, as shown in FIG.
As shown in the flow of (b), CPU (corresponding to V33) 1
After setting the built-in peripheral relocation register 180 based on the information for setting the built-in peripheral relocation register 180 in which the built-in EPROM 30 is written before 1 starts operation,
Starts the processing of the built-in CPU.

Since the information written in the built-in EPROM 30 can be rewritten, the built-in peripheral L
The SI address can be set arbitrarily.

[0024]

As described above, the I / O address of the built-in peripheral of the microprocessor composed of the CPU and the built-in peripheral capable of arbitrarily setting the I / O address is not set by the software of the CPU, but an arbitrary I By making it possible to set the I / O address, it is not necessary to add a new program for setting the built-in peripheral relocation register to the existing software, and it is not necessary to change the existing software. That is, there is an effect that the existing software can be used as it is without adding a program for setting the I / O address. That is,
The effect is that the existing software need not be re-verified because it does not change.

In other words, this has the effect of maintaining the independence of the existing software.

[Brief description of drawings]

FIG. 1 is a system configuration example of a peripheral LSI built-in microprocessor according to an embodiment.

FIG. 2 is a conventional peripheral LS including a CPU and a peripheral LSI.
5 is a flowchart of the execution of an existing program of the I-built-in microprocessor and a flowchart of execution of an existing program of the peripheral LSI built-in microprocessor of the present invention including a CPU and peripheral LSIs.

FIG. 3 is a diagram showing details around a setting information reading circuit 200 of a peripheral LSI built-in microprocessor 101.

FIG. 4 is a timing chart showing the movement of signals related to the setting information reading circuit 200 after the reset reset signal 311 is released.

FIG. 5 is a timing chart showing the movement of signals related to the setting information reading circuit 200 at the end of the setting of the built-in peripheral relocation register 180.

FIG. 6 is a system configuration example in which a CPU and a peripheral LSI are configured by separate ICs.

7 is a system configuration example in which a system configuration example of FIG. 5 is configured by a conventional microprocessor (V53) 100 with a built-in peripheral LSI in which a CPU and a peripheral LSI are one IC.

FIG. 8 shows a built-in peripheral selection signal (31, 32, 3
It is explanatory drawing of the function which controls 3).

FIG. 9 is a system configuration example of a peripheral LSI built-in microprocessor of another embodiment.

[Explanation of symbols]

1 CPU (V33) 2 μPD71051 3 μPD71054 4 μPD71059 5 Memory 6 Address bus / control bus 7 Data bus 8 I / O address decode circuit 11 CPU (V33 equivalent) 12 μPD71051 equivalent 13 μPD71054 equivalent 14 μPD71059 equivalent 16 Internal address -Bus / control bus 17 Internal data bus 18 Internal peripheral relocation register 19 Comparator 21 Peripheral LSI selection signal 22 Peripheral LSI selection signal 23 Peripheral LSI selection signal 30 Internal EPROM 31, 32, 33 Internal peripheral LSI selection signal 100 Peripheral Microprocessor with LSI (V5
3) 101 microprocessor with built-in peripheral LSI 102 microprocessor with built-in peripheral LSI 112 51 address register 113 54 address register 114 59 address register 180 built-in peripheral relocation register 181 write control circuit 182 END signal 185, 186, 187 write control Line 190 I / O access determiner 191, 192, 193 Comparison circuit 195, 196, 197 OR gate 200 Setting information reading circuit 201 DIN signal 202 CLKOUT signal 203 Inversion signal of LOAD 204 Inversion signal of RESET 210 AND gate 211 CPU Reset of RESET Inversion signal 220 Control signal generator 230 Serial / parallel converter 231 Clock counter unit 232 Inversion signal of WR 33 PDATA 300 inverted signal 310 inverter 311 RESET of the inverted signal of the inverted signal 304 OE serial · ROM 301 DATA signal 302 CLK signal 303 CE

Claims (1)

Claim: What is claimed is: 1. A microprocessor in which a CPU and a peripheral LSI capable of arbitrarily setting an I / O address are built in one chip, and means for reading information from the outside of the microprocessor before the operation of the built-in CPU. And a peripheral LSI built-in microprocessor, comprising means for setting an I / O address of the built-in peripheral LSI based on the read information.