JPH05204758A - Microprocessor and memory control method - Google Patents

Abstract

PURPOSE:To enable the high-speed processing of a program for generating/ executing a new instruction by providing the means for accessing data and instructions from one cache memory controller to the other cache memory. CONSTITUTION:When generating the new instruction, a logical data address 410 outputted from an arithmetic unit 401 is converted to a physical data address 414 by a data cache memory controller (MMU) 403. Then, write data are written in a data cache memory 407. When executing the instruction, a logical instruction address 409 is converted to a physical instruction address 413 by an instruction MMU 402. The instruction MMU 402 reads the instruction by retrieving the data cache memory 407. When reloading the instruction, a logical data address 410 is outputted for writing the instruction to be newly reloaded as data. The MMU 403 retrieves an instruction cache memory 406 and reloads the old instruction to the new instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor and a memory control method thereof, and more particularly to a microprocessor suitable for use with a cache memory.

[0002]

2. Description of the Related Art Conventionally, as to a microprocessor using a cache memory and a memory control method thereof, see, for example, Nikkei Electronics (Nikkei McGraw-Hill Co.) 1989.6.26 (no. 476), page 131-.
The thing described in page 140 is mentioned.

In the above-mentioned conventional technique, in order to speed up the processing, the cache memory is divided into one for instructions and one for data, and address conversion from a logical address to a physical address is performed.
Also, a memory control unit (hereinafter, also referred to as MMU) that controls access to the cache memory is divided into an instruction memory and a data memory, and a copy-back method is used as the cache memory updating method.

[0004]

In the above-mentioned prior art, since the cache memory update method is the copy-back method, when an application program generates a new instruction and attempts to execute this new instruction, the instruction is handled. Since the data does not exist in the main storage device, the old data stored in the main storage device is transferred to the arithmetic unit, and it becomes impossible to execute the application program thereafter.

In order to solve this, before the newly generated instruction is executed, the operation of writing the newly generated instruction existing in the data cache memory to the main memory (hereinafter referred to as cache push) is required. ..

However, in order to execute this cache push, a program for calling an OS program or the like must be provided in the application program. As described above, in the above-mentioned conventional technique, in order to generate / execute a new instruction in the application program, it is necessary to create a complicated application program corresponding to the hardware such as the cache memory of the microprocessor and the OS program. However, there is a problem that the production efficiency of the program and the execution speed of the program decrease.

It is an object of the present invention to provide a microprocessor capable of high-speed processing of a program for generating / executing a new instruction, a memory control method thereof, and an information processing system using the same.

[0008]

The features of the present invention for achieving the above object include an arithmetic unit, an instruction cache memory which is a cache memory for instructions, a data cache memory which is a cache memory for data, An instruction cache memory controller for controlling access from the arithmetic unit to the instruction cache memory; a data cache memory controller for controlling access from the arithmetic unit to the data cache memory;
It is provided with means for accessing the data cache memory from the instruction cache memory controller, and means for accessing the instruction cache memory from the data cache memory controller.

Another feature of the present invention is that a logical address is converted into a physical address by using a conversion table, and a memory area is accessed by the physical address. In the conversion table, the conversion processing is performed. Is stored, and the access is controlled by the type information. Here, the type information is, for example, information indicating either access to the instruction cache memory or access to the data cache memory.

Still another feature of the present invention is a memory control method for a microprocessor, wherein a logical address is converted into a physical address by using a conversion table, and a storage area is accessed by the physical address.
The area type information of the storage area allocated at the time of the conversion processing is stored in the conversion table, and the access is controlled by the area type information. Here, the area type information is, for example, information indicating whether an area of a certain size on the main storage device allocated at the time of conversion is an instruction access area or a data access area.

Another feature of the present invention is that an arithmetic processing unit, a memory control unit for converting a logical address output from the arithmetic processing unit into a physical address using a conversion table, and an access by the converted physical address. The instruction cache memory device and the data cache memory device, and the instruction is executed by the access type information input from the arithmetic processing unit provided in the memory control unit and the area type information stored in the conversion table. And a means for determining which of the cache memory and the data cache memory is to be accessed.

[0012]

By providing means for accessing the data cache memory from the instruction cache memory control device and means for accessing the instruction cache memory from the data cache memory control device,
It is possible to solve the problem caused by the location of the instruction or data in the cache memory.

In the conversion table for converting the logical address existing in the main memory area to the physical address, it is determined whether the physical page for reading the instruction or accessing the data is for the instruction or for the data. Area type information (also referred to as attribute information) shown is provided, and is referred to when the OS program allocates a page. Further, when accessing the instruction cache memory or the data cache memory from the memory control device, if the page to be accessed has already been allocated, a means for accessing the same cache memory as the attribute information set in the page table To provide. This allows the memory control device to select the cache memory to be searched according to the attribute information set in the page table.
It is not necessary to create a complicated application program corresponding to the hardware such as the cache memory of the microprocessor and the OS program, and there is no problem that the production efficiency of the program and the execution speed of the program decrease.

[0014]

EXAMPLES Examples of the present invention will be described below.

As shown in FIG. 1, when a new instruction is generated in the process of executing an application program, since the newly generated instruction is written as data, the logical address 106 output from the arithmetic processing unit 101 and its logical address 106 are The access type information 107 indicating a data address is converted into a physical address 108 by the memory control device 102. At the time of conversion, attribute information indicating that the newly allocated page is a data page is set in the page table in the memory control device 102, and the data cache memory 104 is searched.
Here, since the update method of the cache memory is the copy-back method, there is a cache hit (the relevant entry exists in the instruction cache memory 104) and a mishit (the relevant entry does not exist in the instruction cache memory 104). At all times, the write data is written only in the data cache memory 104, and the process buses 110, 111, 112 are not written. Therefore, the new instruction is the data cache memory 1
It is generated only in 04.

When the generated instruction is executed after the generation of the new instruction is completed, the logical address 106 output from the arithmetic processing unit 101 for reading the instruction and the access type indicating that the logical address is the instruction address The signal 107 is translated by the memory controller 102 into a physical address 108. Since attribute information indicating that this page is a data page has already been set in the page table searched in the memory control device 102,
The memory control device 102 includes a data cache memory 10
4 will be searched. Therefore, the instruction generated in the data cache memory 104 can be read.

Further, when an instruction is rewritten in the course of program execution, a logical address 106 output from the arithmetic processing unit 101 for writing a newly rewritten instruction as data and an address indicating the logical address 106 data access The information type 107 is converted into a physical address 108 by the memory control device 102. At that time, since the attribute information indicating that this page is already an instruction page is set in the page table in the searched memory control device 102, the memory control device 1
02 searches the instruction cache memory 103, and the old instruction in the instruction cache memory 103 can be rewritten.

Next, the terms of the write-through method and the copy-back method used in this specification will be described with reference to FIG. FIG. 2 shows a memory control unit (hereinafter, referred to as a cache control unit) that controls address conversion from a logical address to a physical address and access to the cache memory as well as the cache memory.
(Abbreviated as MCU) is also an example in which it is divided into one for instructions and one for data.

In the write through system, the reading of instructions is performed as follows. The instruction logical address 208 output to read the instruction from the arithmetic unit 215 is converted into the instruction physical address 205 by the instruction MCU 201, and the instruction cache memory 202 is searched. When a corresponding entry (instruction) exists in the instruction cache memory 202 (hereinafter referred to as cache hit), the instruction is transferred to the arithmetic unit 215 via the instruction data bus 207.
If the corresponding data does not exist in the instruction cache memory 202 (hereinafter referred to as a cache mishit),
A main memory (not shown, hereinafter abbreviated as MS) is accessed via the bus controller 211. On the other hand, the reading and writing of data is performed by the arithmetic unit 215.
By using the data logical address 209 output for writing or reading more data, the same procedure as the instruction reading procedure can be performed.

Here, in order to further speed up the processing,
It is desirable to provide a method of updating the cache memory called a copyback method. The copy-back method allows the MS to immediately update the data cache memory 204.
Unlike the write-through method in which the contents of the MS are also updated, only the data cache memory 204 is rewritten, and the contents of the MS are not updated until necessary. According to this method, when writing data, only the data cache memory 204 is updated, and the data cache memory 20 is updated.
Since the access for updating the MS whose access speed is slower than 50 to 1/60 is not performed, the high speed processing is possible.

As shown in FIG. 2, the instruction MCU 201, the instruction cache memory 202, the data MCU 203, and the data cache memory 204 are completely independent. In this case, as shown in FIG. 4, the following effects can be obtained by having a unit (for example, a unit for accessing the data cache memory 204 from the instruction MCU 201) that references each other's cache memory between the instruction and the data. ..

That is, in the program execution process,
When a new instruction is generated and a program that executes the instruction after the generation is executed, generating the instruction is
Since the instruction code is to be written as data, the data logical address 209 output from the arithmetic unit 215 is stored in the data MCU 203 as the data physical address 206.
After the address is converted to, and the data cache memory 204 is searched, a new instruction is written in the data cache memory 204. Next, in order to execute the generated instruction, in order to read the instruction from the arithmetic unit 215, the instruction MCU 201 converts the output instruction logical address into an instruction physical address, and searches the instruction cache memory 202. However, since there is no newly generated instruction in the instruction cache memory 202, an instruction cache mishit occurs and the MS is accessed via the bus controller 211, but the cache memory update method is the copy back method. The newly generated instruction is not in the MS, and the old data is transferred to the arithmetic unit 215, so that the program cannot be executed thereafter.

Further, before executing the newly generated instruction, the operation of writing the newly generated instruction existing in the data cache memory 204 to the MS (hereinafter referred to as cache push) becomes unnecessary.

Further, since this cache push cannot be performed by the application program, the application program must provide a program for calling the OS program for performing the cache push in the application program, but this need is eliminated.

Further, in the process of executing a program, when rewriting an instruction of its own program, rewriting the instruction means rewriting an old instruction existing in the instruction cache memory 202 with a new instruction. Is to write the code of the instruction as data, the new instruction to be rewritten is written only in the data cache memory 204. Therefore, since the old instruction in the instruction cache memory 202 remains as it is without being rewritten, the newly rewritten instruction cannot be executed. However, the instruction cache memory 2 for eliminating this cannot be executed.
It is not necessary to perform the process (cache purge) of invalidating the old instruction in 02 and then the data cache push process.

FIG. 3 shows an example of the overall configuration of the information processing system. Central processing unit (CPU) 301, external cache memory unit (ECU) 302, bus control unit (BCU) 303, main memory unit (MS) 30
4, file control unit (FCU) 305, disk unit (DISK) 30
6, a graphic control unit (GCU) 307, a graphic display unit (GD) 308, and address lines 309, 310, 311 and 312, data lines 313.
314, 315, 316, 317, control lines 318, 31
They are connected at 9,320,321. Address line 30
9, the data line 313 and the control line 318 form a processor bus, and the address line 311, the data line 315 and the control line 320 form a system bus. CPU3
The program executed by 01 is stored in the DISK 306, and a part of the program is loaded into the MS 304 and then executed. The ECU 302 stores a part of the stored contents of the MS 304, and the CPU 301 can access it at high speed. The execution result of the CPU 301 is graphically processed by the GCU 307 and then displayed on the GD 308. In addition to the above, input devices such as a keyboard and a mouse are connected to the system bus via an interface unit (not shown).

FIG. 4 is a detailed explanatory diagram of the CPU 301 shown in FIG. 3 and the processor buses 309, 313, 318 connected thereto. In order to speed up the processing, the cache memory update method is set to the copy back method, and in addition to the cache memory, the MCU has a hardware configuration and a method that exists on the MS 304 in a method in which the MCU is divided into data for instruction and data. FIG. 3 is a diagram showing a page table format configuration to be performed and a format configuration of a high-speed address translation buffer (hereinafter abbreviated as TLB) that configures an MCU together with an address translation unit (hereinafter abbreviated as MMU).

FIG. 5 is a flow chart showing an outline of the processing based on the hardware configuration shown in FIG.

Normally, as shown in FIG. 5A, the instruction logical address 409 output from the arithmetic unit 401 to read the instruction is converted into the instruction physical address 413 by the instruction MMU 402. At this time, in order to allocate a new page, attribute information indicating that the page is an instruction page is set in the page table A, and the instruction cache memory 406 is searched. In case of cache hit,
Instruction data (bus) 4 from the instruction cache memory 406
The instruction is transferred to the arithmetic unit 401 via 11. In the case of a cache miss, the bus controller 408
To access the processor buses 309, 313, 318 via the MS 304 (not shown in FIG. 4, see FIG. 3).
More relevant entry is fetched and instruction data (bus) 4
The instruction is transferred to the arithmetic unit 401 via 11 and simultaneously written in the instruction cache memory 406. The arithmetic unit 401 decodes the fetched data, calculates the address, reads the operand, and finally executes the instruction.

When a new instruction is generated in the process of executing the program, as shown in FIG. 5B, since the newly generated instruction is written as data, the data logical address 410 output from the arithmetic unit 401 is written.
Is converted into a data physical address 414 by the data MMU 403. At that time, to allocate a new page,
Attribute information indicating that this page is a data page is set in the page table, and the data cache memory 407
To search. Here, since the update method of the data cache memory 407 is the copy back method, the write data is written only to the data cache memory 407 at both the cache hit and the cache miss hit, and is written to the processor buses 309, 313, 318. Does not write. Therefore, the new instruction is generated only in the data cache memory 407.

When the generation of the instruction is completed and the generated instruction is executed next, the instruction logical address 409 output from the arithmetic unit 401 to read the instruction is
It is converted into the instruction physical address 413 by the instruction MMU402. At that time, since attribute information indicating that the page is a data page has already been set in the retrieved page table, the command MMU402 transmits the data via the control line 417.
By instructing the MMU 403 to search the data cache memory 407 and obtaining permission from the data MMU 403, the data cache memory 407 can be searched to read the instruction generated in the data cache memory.

When rewriting an instruction in the course of executing a program, as shown in FIG. 5C, the operation unit 4 is used to write a new rewriting instruction as data.
The data logical address 410 output from 01 is converted into the data physical address 414 by the data MMU 403. At this time, since the attribute information indicating that this page is already the instruction page is set in the retrieved page table, the data MMU 403 receives the instruction MMU 402 via the control line 417.
Tell MM to search the instruction cache memory
After obtaining the permission from U402, the old instruction can be rewritten to the new instruction by searching the instruction cache memory 406.

As described above, in the process of executing the program,
It is not necessary to be aware of hardware such as cache memory when creating a new instruction and creating an application program that executes the instruction after it is generated, or a program that rewrites the instruction of its own program. The effect is that processing can be performed at high speed.

[0034]

According to the present invention, it is possible to provide a microprocessor capable of high-speed processing of a program for generating / executing a new instruction, a memory control method thereof, and an information processing system using the same.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a write-through method and a copy-back method.

FIG. 3 is a diagram showing the overall configuration of an embodiment of the present invention.

FIG. 4 is a diagram showing a detailed configuration around a central processing unit (CPU) and a page table format configuration in FIG. 3 and a TLB format configuration.

FIG. 5 is a flowchart showing an outline of processing according to an embodiment of the present invention.

[Explanation of symbols]

101 ... Arithmetic processing device, 102 ... Memory control device, 10
3 ... Instruction cache memory, 104 ... Data cache memory, 105 ... Bus controller, 106 ... Logical address, 107 ... Access type information, 108 ... Physical address, 109 ... Data, 110 ... Address, 111 ... Data, 112 ... Control line, 304 ... MS, 309, 313
318 ... Processor bus, 401 ... Arithmetic unit, 40
2 ... Instruction MMU, 406 ... Instruction cache memory, 40
8 ... Bus controller, 409 ... Instruction logical address, 4
11 ... Command data, 413 ... Command physical address.

Claims (10)

[Claims] 1. An arithmetic unit, an instruction cache memory that is a cache memory for instructions, a data cache memory that is a cache memory for data, and an instruction cache that controls access from the arithmetic unit to the instruction cache memory. A memory control device; a data cache memory control device for controlling access from the arithmetic unit to the data cache memory; a means for accessing the data cache memory from the instruction cache memory control device; Means for accessing the instruction cache memory from a device. 2. An arithmetic unit, a memory controller for converting a logical address output from the arithmetic unit into a physical address using a conversion table, an instruction cache memory and a data cache accessed by the converted physical address. A microprocessor comprising: a memory; and means for determining which of the instruction cache memory and the data cache memory is to be accessed based on the type information stored in the conversion table. 3. The microprocessor according to claim 2, wherein the memory control device comprises an instruction memory control device and a data memory control device. 4. A logical address is converted into a physical address using a conversion table, and when the memory area is accessed by the physical address, type information of the conversion process is stored in the conversion table. A microprocessor having a function of controlling the access according to the type information, a disk device that stores a program executed by the microprocessor, a main storage device that loads a part of the program, and a part of the main storage device An external cache memory device that stores a copy of a file, a file controller that controls input / output between the disk device and the system bus, and an input / output between the main storage device, the processor bus, and the system bus An information processing system comprising: a bus control device that operates. 5. A microprocessor for converting a logical address into a physical address by using a conversion table and accessing a memory area by the physical address, wherein the conversion table has a memory for instructions. A memory control method for a microprocessor, characterized in that type information indicating whether the access is to an area or a data memory area is stored and the access is controlled by the type information. 6. The memory control method for a microprocessor according to claim 5, wherein the memory area is an instruction cache memory and a data cache memory that perform a memory update by a copyback method. 7. The memory control method according to claim 6, wherein the data cache memory is accessed when a mishit occurs in the access to the instruction cache memory. 8. A logical address output from an arithmetic unit is converted into a physical address by using a conversion table on a main storage device, and a cache memory is accessed by the converted physical address. Area conversion information indicating whether an area of a certain size on the main memory allocated at the time is an instruction access area or a data access area is stored in the conversion table, and when accessing the cache memory, A memory control method for a microprocessor, wherein access to the cache memory is controlled by the area type information. 9. The memory control device according to claim 8, wherein a logical address output from said arithmetic unit is input and converted into a physical address by using a conversion table on a main memory, and access by said converted physical address. Two cache memories for instructions and data are provided, and the memory control device determines whether to access the instruction cache memory or the data cache memory based on the area type information. Memory control method for microprocessor. 10. The access type information according to claim 8, wherein the two or more logical addresses output from the arithmetic unit are input with access type information indicating either an instruction access or a data access, and access is performed by the converted physical address. An instruction cache memory and a data cache memory, and determines whether to access the instruction cache memory or the data cache memory according to the access type information and the area type information stored in the conversion table. A memory control method for a microprocessor, comprising: