JPH05204003A - Substrate type optical switch and its production - Google Patents

Abstract

PURPOSE:To provide the above switch which is suitable for high-speed switching by decreasing a driving current and diminishing a parasitic capacity. CONSTITUTION:A buffer layer 11 consisting of p-InP, an optical waveguide layer 12 consisting of u-InGaAsP, a current confining layer 13 consisting of n<+>-InP and a cap layer 14 consisting of n<+>-InGaAsP are successively crystal grown on a substrate 1 of P-InP by a liquid phase epitaxy or vapor growth method and thereafter, the current confining layer 13 is etched by a selective chemical etching method. A current block layer 15 of Si-InP is then crystal grown so as to be adjacent to the current confining layer 13 and further, this current block layer 15 is etched to constitute a bridge type waveguide structure. An electrode 18 in contact with the current confining layer is provided atop the substrate 1 and an electrode 19 is provided on the rear surface of the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate type optical switch used for optical communication, optical information processing and the like and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a substrate type optical switch, an internal total reflection type optical switch has been proposed which utilizes a large change in the refractive index due to a band filling effect caused by carrier injection (for example,
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATION vo
l.6, No.7 p1262-1266).

In this substrate type optical switch, as shown in FIG. 10, an X-shaped optical waveguide portion 5 is provided on a substrate 4 of n-InP (n-type indium phosphide) which is a compound semiconductor material, and intersects with each other. The part is formed as the switching part 6. The optical waveguide section 5 has a rib type optical waveguide structure as shown in FIG. 11, and is formed on the n-InP substrate 4 with n-I.
An optical waveguide layer 42 of u-InGaAsP (undoped indium gallium arsenide phosphide) is formed via an nP buffer layer 41, an n-InP clad layer 43 is further formed on the optical waveguide layer 42, and etching is performed. ..

The switching section 6 at the intersection is shown in FIG.
2, a part of the n-InP clad layer 43 has p
-InP current confinement layer 44 is formed, and p is formed on the upper surface thereof.
The mold electrode 46 and the n-type electrode 47 are formed on the lower surface.
An insulating layer 45 of silicon dioxide is formed on the upper surface of the n-InP substrate 4 so as to cover the entire surface of the p-InP current confinement layer 44 except the upper surface thereof.

When a current is injected by applying a voltage between the electrodes 46 and 47, a double heterojunction is formed between the p-InP current confinement layer 44 and the n-InP buffer layer 41, so that this p-InP is formed. A forward current flows through the current confinement layer 44. n-InP clad layer 43
Acts as a current blocking layer that blocks current. This structure has a structure of the u-InGaAsP optical waveguide layer 4
This is to increase the density of injected carriers within 2. By this carrier injection, the refractive index changes due to the band-filling effect, and total reflection of incident light can be generated. That is, as shown in FIG. 10, when the light is incident from one end Pi of the optical waveguide portion 5 and the current is not injected as described above, the light goes straight and is emitted from the one end Pa, but as described above. When the current is injected, it is totally reflected by the switching unit 6 and emitted from the other end Pb.

Such a substrate type optical switch is conventionally manufactured as follows. First, liquid phase epitaxial growth (LPE) method or metal organic chemical vapor deposition (OM)
VPE) method, as shown in FIG. 13, the n-InP buffer layer 41 and the u-InG are formed on one surface of the n-InP substrate 4.
aAsP optical waveguide layer 42 and n-InP clad layer 43
Are sequentially grown in multiple layers. Next, the upper surface of the substrate 4 is subjected to photolithography technology and reactive ion etching (RI
E) technique is used to etch a part of the n-InP cladding layer 43 to form a rib type optical waveguide structure as shown in FIGS. After that, zinc (Zn) is selectively diffused at the intersection to form the p-InP current confinement layer 44. Then, a part of the silicon dioxide insulating layer 45 covering the upper surface is removed, the p-type electrode 46 is brought into contact with the optical waveguide layer 42, and the n-type electrode 47 is formed on the lower surface.
To form.

Such a substrate type optical switch is characterized by using a large change in the refractive index due to the band-filling effect, and can be fabricated on the n-InP substrate by the LPE method or the OMVPE method only once. Have an advantage

[0008]

However, the conventional substrate type optical switch has a problem in that it is driven at a low current, and also has a problem that the parasitic capacitance becomes an obstacle to high-speed switching. When the driving current becomes large, the driving power of the optical switch becomes large, so that there is a serious problem especially when such an optical switch is integrated or operated at high speed.

The cause of the large drive current as described above can be considered as follows. First, in this substrate type optical switch, the current confinement layer is formed by using Zn diffusion in the n-InP cladding layer as described above. When a constant current is injected into the optical switch, the injection carrier density increases as the volume of the current confinement region decreases, so low current drive can be realized.However, in such an optical switch, a method called diffusion is used to reduce the current confinement region. Since it is formed, the width of the current confinement region is very small (for example, 1
.mu.m or less), and low current drive cannot be realized. In addition, p- formed in this way
The InP current confinement layer forms a pn forward homojunction with the n-InP cladding layer. That is, the injected current preferentially flows to the double heterojunction side due to the slight potential difference between the double heterojunction and this homojunction, but the potential difference is small at the time of high current injection, so this homojunction side Therefore, a current also flows, and high efficiency operation, that is, low current drive cannot be realized. Further, even if the width of the p-InP current confinement layer can be made fine by diffusion or other method, the region for confining this current is constituted by p-type InP, and p-type InP is n-type. Since the electrical resistivity is one digit higher than that of InP, the electrical resistance of the device increases in this current confinement region, making it difficult to drive the optical switch with low power. Therefore, when such an optical switch is integrated to form a matrix switch, the power consumption of each switch element is large, resulting in a large total current consumption, which is a serious problem.

The p-InP current confinement layer and the n-I
A junction capacitance generated between the nP clad layer (current blocking layer) is formed. This parasitic capacitance becomes a problem when the switching speed is increased, which is an obstacle to the high speed switching.

In view of the above, it is an object of the present invention to provide a substrate type optical switch which can be driven at a low current, has a small parasitic capacitance and is suitable for high speed switching.

Another object of the present invention is to provide a method of manufacturing such an improved substrate type optical switch.

[0013]

In order to achieve the above object, in the substrate type optical switch according to the present invention, p-
InP substrate and u-InGaA formed on this substrate
The sP optical waveguide layer and the n-InP current confinement layer and the SI-InP current blocking layer formed in parallel on the optical waveguide layer are provided, and the width of the current confinement layer is 1/2 or less of the conventional width. Of about 1 μm, and since the conductivity type is n-type, the resistance of the device can be improved by one digit as compared with the conventional p-type current confinement layer.

In the method of manufacturing a substrate type optical switch according to the present invention, a u-InGaAsP optical waveguide layer and an n-InP current confinement layer are sequentially grown on a p-InP substrate, and then the n-InP current confinement layer is etched. The width of the lever current confinement layer is narrowed, and then SI-I is formed on the optical waveguide layer so as to be adjacent to the side of the current confinement layer.
It is characterized in that the nP current blocking layer is crystal-grown again.

Further, u-InGaA is formed on the p-InP substrate.
The sP optical waveguide layer and the SI-InP current blocking layer are sequentially crystal-grown, and then the SI-InP current blocking layer is etched to form an elongated groove reaching the optical waveguide layer. The n-InP current confinement layer may be grown on the optical waveguide layer by crystal growth.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a substrate type optical switch according to a first embodiment. As shown in FIG. 1, an X-shaped optical waveguide portion 2 is provided on a p-InP substrate 1 which is a compound semiconductor material. And the intersecting portion is formed as the switching portion 3. The optical waveguide portion 2 has a ridge type optical waveguide structure as shown in FIG.
The u-InGaAsP optical waveguide layer 12 is formed on the -InP substrate 1 via the p-InP buffer layer 11, and the elongated SI-InP cladding layer 15 and n ⁺ -are further formed thereon.
The InGaAsP cap layer 14 has a convex structure. This SI-InP clad layer 15
This is a semi-insulated layer obtained by doping InP with Fe (iron) or the like to increase the resistance.

In the switching portion 3 at the intersection, as shown in FIG. 3, an n ⁺ -InP current confinement layer 13 is elongatedly embedded in a part of the convex SI-InP cladding layer 15, and n is formed on the upper surface thereof. The mold electrode 18 has a p-type electrode 19 on the lower surface.
Are formed. The upper surface of the p-InP substrate 1 was covered with silicon dioxide so as to cover the entire surface of the n ⁺ -InGaAsP cap layer 14 located on the n ⁺ -InP current confinement layer 13 except the upper surface. The insulating layer 17 is formed.

When a current is injected by applying a voltage between the electrodes 18 and 19, the p-InP buffer layer 11 and n
Through the pn double heterojunction between the ^{+ +} -InP current confinement layer 13 and the n ⁺ -InP current confinement layer 13,
Current flows through. A current is blocked in the SI-InP clad layer 15, and the clad layer 15 functions as a current blocking layer, so that the carrier density of the reflection portion in the u-InGaAsP optical waveguide layer 12 increases. Such carrier injection causes a change in the refractive index due to the band-filling effect and can cause total reflection of incident light. As shown in FIG. 1, one end Pi of the optical waveguide portion 2 is formed.
When the light is incident from the above, when the current is not injected as described above, the light goes straight and is emitted from one end Pa, but when the current is injected as described above, the light is totally reflected by the switch unit 3 and emitted from the other end Pb. Come to do.

In this case, the SI-InP current blocking layer 1
5 and the n ⁺ -InP current confinement layer 1 embedded therein
In No. 3, if crystal growth is performed on one side first, then unnecessary portions are removed by photolithography and selective chemical etching technology to leave only necessary portions, and then the other is formed by crystal growth again, n ⁺ −InP current confinement layer 13
Can be set to about 1 μm, which is 1/2 or less of the conventional width. Thus, the area of the current confinement layer 13 is reduced to 1 /
Since it can be reduced to 2 or less, the drive current as an optical switch can be significantly reduced as compared with the conventional one. Further, since the change in the refractive index for switching is a function of the carrier density that rises due to the switching current, the narrower the area of the current confinement layer 13, the more efficient the switching operation can be realized, and when considering integration. Very advantageous.

Further, since the conductivity type of the current confinement layer 13 is n type, the resistance of the element when a switching current is passed can be improved by one digit as compared with the case of the p type current confinement layer. For example, when the area of the n ⁺ -InP current confinement layer 13 is set to 1 μm × 200 μm (width × length) and the carrier concentration of this n ⁺ -InP is set to 4 × 10 ¹⁸ , the resistance at this portion is only 0. It becomes 1Ω. By the way, when a p-type current confinement layer is used as in the prior art, it becomes 1.4Ω under the same conditions such as setting the carrier concentration of p-InP to 4 × 10 ¹⁸ , and this embodiment has one digit or more. You can see that it is getting smaller. As a result, it is advantageous in terms of driving power and high-speed switching.

Since the SI-InP current blocking layer 15 has a very high electric resistance, the SI-InP current blocking layer 15 has a very high electric resistance.
P current blocking layer 15 and n ⁺ -InP current confinement layer 1
The junction capacitance formed with the capacitor 3 and 3 is very small, and therefore does not become a parasitic capacitance which becomes an obstacle when the switching speed is increased. That is, the parasitic capacitance can be reduced, and a substrate type optical switch suitable for high speed switching can be realized.

Next, an embodiment of a method of manufacturing a substrate type optical switch having such a structure will be described. First, as shown in FIG. 4, on the p-InP substrate 1 by using the OMVPE method, p-InP buffer layer 11, u-InGaAsP optical waveguide layer 12, n ⁺ -InP current confinement layer 13, n ⁺ -
The InGaAsP cap layer 14 was sequentially subjected to multilayer crystal growth.

Thereafter, in the switching section 3, n ⁺ -InGaAsP is used by using a photolithographic technique and a selective chemical etching technique using a hydrogen chloride based etching solution.
Using the cap layer 14 as a mask, the n ⁺ -InP current confinement layer 13 is selectively removed, and as shown in FIG.
Only the elongated n ⁺ -InP current confinement layer 13 having a length of m and a length of 200 μm was left.

Next, as shown in FIG. 6, the remaining n ⁺
-InP current confinement layer 13 and n ⁺ -InGaAsP
The cap layer 14 is covered with the silicon dioxide mask layer 16, and then the SI-InP current blocking layer 1 is formed by using the LPE method.
5 and n ⁺ -InGaAsP cap layer 14 with n ⁺ -I
Crystals were grown adjacent to both sides of the nP current confinement layer 13.

In the optical waveguide section 2, the n ⁺ -InP current confinement layer 1 as shown in FIG.
3, n ⁺ -InGaAsP cap layer 14 is not left, and all of them are removed. Then, the SI-InP current blocking layer (cladding layer) 15 and the n ⁺ -InGaAsP cap layer 14 are formed on the entire surface by the above-described crystal growth step.

Next, in order to form the optical waveguide portion 2 into an X shape, after patterning the photoresist into the X shape, reactive ion beam etching using chlorine gas was performed. In this way, the ridge type optical waveguide portion 2 as shown in FIG. 2 was formed, and the internal total reflection type switching portion 3 as shown in FIG. 3 was obtained. After forming the n-type electrode 18 and the p-type electrode 19 on the upper and lower surfaces of the substrate 1, respectively, the size of the 2 × 2 optical switch (2 mm × 0.5 m
m) to obtain a substrate type optical switch as shown in FIG.

In the above embodiment, the n ⁺ -InP current confinement layer 13 is first crystal-grown and then selectively etched, and then the SI-InP current block layer 15 is recrystallized. SI-InP current blocking layer 1
It is also possible to first grow the crystal of No. 5 and selectively remove it, and then recrystallize the n ⁺ -InP current confinement layer 13. In that case, first, as shown in FIG.
Using the VPE method, the p-InP buffer layer 11, the u-InGaAsP optical waveguide layer 12, and the S-layer are formed on the p-InP substrate 1.
I-InP current blocking layer (cladding layer) 15, n ⁺ -
The InGaAsP cap layer 14 is sequentially subjected to multi-layer crystal growth.

Next, in the switching unit 3, n ⁺ -InGaAsP is used by using the photolithographic technique and the selective chemical etching technique using a hydrogen chloride type etching solution.
Using the cap layer 14 as a mask, the SI-InP current blocking layer 15 is selectively removed, and as shown in FIG.
An elongated groove 20 having a length of m and a length of 200 μm was formed.

Thereafter, as shown in FIG. 9, the silicon dioxide layer 2
Using 1 as a mask, the n ⁺ -InP current confinement layer 13 and the n ⁺ -InGaAsP cap layer 14 were crystal-grown only in the groove 20 by using the LPE method.

In the optical waveguide portion 2, the groove 20 is not formed in the above etching step as shown in FIG.
The P-current blocking layer 15 is not removed at all, and the SI-InP current blocking layer 15 is entirely left.

Next, in order to form the optical waveguide portion 2 into an X shape, after patterning the photoresist into the X shape, reactive ion beam etching using a chlorine-based gas is carried out, as shown in FIG. While forming such a ridge type optical waveguide section 2, an internal total reflection type switching section 3 as shown in FIG. 3 was obtained. After forming the n-type electrode 18 and the p-type electrode 19 on the upper and lower surfaces of the substrate 1, respectively, they were cut out into a size of 2 × 2 optical switch (2 mm × 0.5 mm) to obtain a shape as shown in FIG.

The substrate type optical switches manufactured by the above manufacturing method all showed good characteristics. That is, when the characteristics of these substrate type optical switches were measured, a switching operation was obtained at a current of 40 mA and an extinction ratio of 15
The insertion loss was 10 dB. The switching current was 40 mA, which was 80 mA in the past, and it can be seen that the switching current is greatly reduced. Regarding other characteristics, that is, the extinction ratio and the insertion loss, no remarkable deterioration due to the change of the current confinement structure was observed as compared with the conventional one. Further, since the series electric resistance of these substrate type optical switches is 5Ω and is 4.5Ω in the related art, the increase of the element resistance due to the reduction of the area of the current confinement layer 13 is hardly seen. ..

If liquid phase growth is used for the second crystal growth, it is possible to form an optical switch having substantially the same structure without using a silicon dioxide mask.

[0034]

As described in the above embodiments, according to the substrate type optical switch and the manufacturing method thereof of the present invention,
Since it is possible to reduce the volume of the current confinement region and increase the carrier density of the light reflection part without increasing the resistance of the current confinement region, an optical switch with low power consumption (driving current) can be easily manufactured. be able to. Moreover, since the parasitic capacitance can be reduced, it is possible to prevent the parasitic capacitance from interfering with high-speed switching. Therefore, it is extremely advantageous for the integration and speedup of the optical switch.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing an appearance of a substrate type optical switch according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG.

FIG. 4 is a sectional view showing a step of the manufacturing method according to the embodiment.

FIG. 5 is a sectional view showing a next manufacturing step in the manufacturing method.

FIG. 6 is a cross-sectional view showing a further manufacturing process in the manufacturing method.

FIG. 7 is a sectional view showing a step of another manufacturing method according to the embodiment.

FIG. 8 is a sectional view showing a next step in another manufacturing method according to the embodiment.

FIG. 9 is a cross-sectional view showing a further subsequent step in another manufacturing method according to the embodiment.

FIG. 10 is a schematic perspective view showing an appearance of a substrate type optical switch according to a conventional example.

11 is a cross-sectional view taken along the line AA of FIG.

12 is a sectional view taken along line BB of FIG.

FIG. 13 is a cross-sectional view showing a step in the manufacturing method of the conventional example.

[Explanation of symbols]

1 p-InP substrate 2, 5 Optical waveguide part 3, 6 Switching part 4 n-InP substrate 11 p-InP buffer layer 12, 42 u-InGaAsP optical waveguide layer 13 n ⁺ -InP current confinement layer 14 n ⁺ -InGaAsP cap Layer 15 SI-InP current blocking layer (cladding layer) 16 Silicon dioxide mask layer 17, 45 Silicon dioxide insulating layer 18, 19 Electrode 20 Groove 41 n-InP buffer layer 43 n-InP cladding layer 44 p-InP current confinement layer 46 , 47 electrodes

Claims (3)

[Claims] 1. A p-InP substrate, a u-InGaAsP optical waveguide layer formed on the substrate, an n-InP current confinement layer and an SI formed in parallel on the optical waveguide layer.
A substrate type optical switch having an InP current blocking layer. 2. u-InGaAsP on a p-InP substrate
The step of crystal-growing the optical waveguide layer, the step of crystal-growing the n-InP current confinement layer on the optical waveguide layer, and the etching of the n-InP current confinement layer after that, and the width of the current confinement layer. And a step of crystallizing an SI-InP current blocking layer on the optical waveguide layer so as to be adjacent to the side of the current confinement layer. Method. 3. u-InGaAsP on a p-InP substrate
A step of crystal growing an optical waveguide layer, a step of crystal growing an SI-InP current block layer on the optical waveguide layer, and then etching the SI-InP current block layer to reach the optical waveguide layer. And a step of crystallizing an n-InP current confinement layer on the optical waveguide layer in the elongated groove of the current block layer. Production method.