JPH0520234A - Communication control equipment - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a microprocessor by using a receiving character as a part of an interruption vector. CONSTITUTION:At the time of receiving an interruption 56 from an interruption control circuit 11, the microprocessor 12 outputs an interruption response 57 and discriminates a transmitting interruption factor 50 or a receiving interruption factor 51 based upon an interruption vector 55 outputted from the circuit 11. A communication line control circuit 10 receives a character from a serial line 20 and generates the factor 50 for requesting the reception of the received character. The circuit 11 generates a receiving character reading instruction 52 to the circuit 10 based upon the response 57 outputted from the microprocessor 12. The circuit 10 allows the microprocessor 12 to read out the vector 55 using the instruction 52 as a part of a receiving character vector to be outputted to an internal bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device, and more particularly to a communication control device for performing character transmission processing.

[0002]

2. Description of the Related Art When a transmission or reception interrupt factor is generated, a conventional communication control device notifies the interrupt control circuit of the factor, and the interrupt control circuit prepares a vector corresponding to the factor, -Generate an interrupt to the processor.

FIG. 3 is a flow chart showing the processing of a conventional microprocessor. When a microprocessor receives an interrupt, it starts an interrupt response cycle to know what the interrupt is, and the interrupt control circuit. Reads the vector prepared by. Then, if the vector read causes the interrupt to be a receive interrupt, the microprocessor
By the program, the received character is read from the communication line control circuit, and the read character is also identified by the microprocessor so that the processing corresponding to the received character is performed. Next, when the interrupt is a transmission interrupt by the read vector, the microprocessor first reads the transmission character from the buffer memory by the micro program, and then writes (writes) the communication line control circuit. It was a method.

[0004]

In the above-mentioned conventional communication control device, in the character reception processing system, the processing intervention of the micro program is indispensable for identifying the received character, and the character reception processing method is applied. In executing the processing, there is a drawback that the response is delayed by the time necessary for the microprocessor to identify the character.

Further, in the character transmission processing method, from the generation of a transmission request until the transmission of the n (N> 1) th character being transmitted at that time is completed, the micro program is If the preparation of the (n + 1) th transmission character is not completed within the time when the transmission of the th character is completed, an underrun error occurs.

[0006]

A communication control device according to the present invention has a communication line control circuit for transmitting and receiving data to and from a serial communication line and a bit length of a character which is a unit of data transmitted and received by the communication line control circuit. A microprocessor that recognizes an interrupt factor with a vector having a long bit length, a buffer memory that stores the data to be transmitted and received, and a vector that corresponds to the interrupt factor related to transmission and reception from the communication line control circuit are prepared. An interrupt control circuit for generating an interrupt to a processor, wherein the microprocessor connected by one internal bus identifies an interrupt factor by a vector from the interrupt control circuit, The communication line control circuit receives the character from the serial communication line. Means for causing the communication control circuit to issue a read instruction of the received character to the communication line control circuit in the interrupt response cycle of the microprocessor in response to the interrupt requesting the receipt of the received character, and the communication by the means. The line control circuit makes the received character output to the internal bus a part of the vector and causes the microprocessor to read the vector.

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

The communication line control circuit 10 includes a serial line 2
Data transmission / reception to / from 0 and parallel data bus 5
Serial-parallel conversion of data for 4 is performed,
When one character, which is a unit of data transmitted / received to / from the serial line 20, is received, a reception interrupt factor 50, which is a request to receive the received character, and a transmission interrupt request 51, which requests the character when the character to be transmitted becomes necessary. Is generated for the interrupt control circuit 11.

The interrupt control circuit 11 uses a reception interrupt factor 50 or a transmission interrupt factor 51 to generate a micro interrupt signal.
An interrupt 56 is generated for the processor 12.

Microprocessor 12 uses interrupt 5
When 6 is accepted, an interrupt response 57 is returned to the interrupt control circuit 11 to request reading of a vector for identifying what the interrupt 56 is. The interrupt control circuit 11 outputs an interrupt vector 55 corresponding to an interrupt factor to the parallel data bus 54 so that the microprocessor 12 can read it.

When the interrupt control circuit 11 receives the interrupt response 57 when it is the reception interrupt factor 50, it issues a read instruction of the read / write instruction 52 to the communication line control circuit 10 and receives it on the parallel data bus 54. As a part of interrupt vector 55 by outputting a character,
Cause the microprocessor 12 to read.

FIG. 2 is a flow chart showing the processing of the microprocessor of this embodiment.
When the interrupt factor caused by reading is received, the interrupt is a receive interrupt, and the identification of the received character can be known at the same time, so the process of identifying the received character by the micro program is not required, and the process for the received character is performed. Can be achieved at high speed. Further, the microprocessor reads the transmission character from the buffer memory 13 and writes it in the interrupt control circuit 11 before receiving the transmission interrupt, and the interrupt control circuit 11 holds the transmission character class.

When the interrupt control circuit 11 receives the interrupt response 57 when it is the transmission interrupt factor 51, the transmission control character held in advance is included in the parallel data bus 54 as a part. Interrupt vector 5
5 is output and the microprocessor 12 is read,
At the same time, a write instruction of the read / write instruction 52 is generated to the communication line control circuit 10, and the transmission character output as a part of the interrupt vector 55 is written to the parallel data bus 54.

In this way, by reading the interrupt vector 55, when the interrupt indicating the request of the (n + 1) th transmission character generated during the transmission of the n (n> 1) th character is recognized, n + 1 has already been recognized. The second transmission character is ready and the micro
The program may read the n + 2th transmission character from the buffer memory 13 and write it to the interrupt control circuit 11 in preparation for a transmission interrupt that occurs during the transmission of the n + 1th character.
Since the time allowed for the program to prepare the transmission character is until the transmission of the (n + 1) th character is completed, it is possible to increase the allowable range by the transmission time of one character as compared with the conventional example. .

[0015]

As described above, the present invention has the effect of improving the processing efficiency of the microprocessor by making the received character part of the interrupt vector.

Further, by holding the transmission character, making the transmission character a part of the interrupt vector, and generating the interrupt vector, there is an effect that the permissible range of the transmission processing time of the micro program is increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the processing of the microprocessor of this embodiment.

FIG. 3 is a flowchart showing the processing of a conventional microprocessor.

[Explanation of symbols]

10 Communication line control circuit 11 Interrupt control circuit 12 microprocessors 13 buffer memory 20 serial lines

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Claims (2)

[Claims] 1. A communication line control circuit for transmitting / receiving data to / from a serial communication line, and a vector of a bit length longer than a bit length of a character, which is a unit of data transmitted / received by the communication line control circuit, recognizes an interrupt factor. A microprocessor, a buffer memory for storing the data to be transmitted and received, an interrupt control circuit for preparing a vector corresponding to an interrupt factor related to transmission and reception from the communication line control circuit, and generating an interrupt to the microprocessor In the communication control device, wherein the microprocessor connected to one internal bus identifies an interrupt factor by a vector from the interrupt control circuit, the communication line control circuit is configured to connect the character from the serial communication line. The received character generated by receiving Means for the interrupt control circuit to issue a read instruction of the received character to the communication line control circuit in the interrupt response cycle of the microprocessor for the interrupt requesting the request, and the communication line control circuit outputs to the internal bus by this means. And a means for causing the microprocessor to read the received character as a part of the vector. 2. A means for writing a transmission character to the interrupt control circuit before the microprocessor recognizes an interrupt requesting a transmission character from the communication line control circuit, and the interrupt control circuit is configured to write the transmission character. And a means for holding the transmission character, and a microprocessor for an interrupt requesting the transmission character from the communication line control circuit, makes the transmission character held by the interrupt control circuit part of the vector in an interrupt response cycle. 2. The communication control device according to claim 1, further comprising means for writing to the communication line control circuit at the same time as being read by the microprocessor.