JPH0520095A - Interruption signal processing circuit - Google Patents

Abstract

PURPOSE:To automatically decide the active state of the interruption signal of each device and inform a CPU of that by deciding and storing the active level of an interruption request signal in a power-ON resetting period. CONSTITUTION:When a device is powered ON and a power-ON reset signal 9 goes down to a low level, a detection period generating circuit 1 is actuated to hold a timing signal 12 at a high level. At this time, the interruption request signal 10 is gated by an AND gate 2 and a signal level corresponding to the signal level of the interruption request signal 10 is latched by a latch circuit 3. When an interruption request signal 10 whose signal level is different from the signal level 13 held by the latch circuit 13, the interruption signal 17 is outputted while held at the high level. Thus, while the system is actuated, the relation between the held signal level 13 and the signal level of the actual interruption request signal 10 is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt signal processing circuit for automatically judging the active level of an interrupt signal of various devices which generate an interrupt request and accepting the interrupt request.

[0002]

2. Description of the Related Art Some information processing systems such as computers employ a method of detecting the occurrence of an event by an interrupt signal or the like and controlling the operation of the system by the interrupt processing. In such an information processing system, there are a plurality of devices such as a timer, a keyboard, and various peripheral circuits as devices that generate an interrupt signal, and the level of the interrupt signal at which each interrupt becomes active, that is, active. -It is very often that each device has a high level or an active low level. In such a case, at the system design stage, the side that accepts the interrupt signal determines the signal level of the interrupt signal for each device, or the condition is set in the interrupt register, and the system is activated after the system is started. The active level of the interrupt signal is set in the pre-processing stage.

[0003]

However, if the interrupt signal level is fixed at the time of system design as in the former case of the conventional example, it cannot be changed later. Further, like the latter, when various conditions are set in the register in the preprocessing of the system to set the signal level of the interrupt signal, a predetermined condition value must be written in the register each time the system is started. There is a problem.

The present invention has been made in view of the above conventional example, and detects the active level of the interrupt signal from each device during power-on reset, and automatically detects the active state of the interrupt signal of each device. CPU to judge
It is an object of the present invention to provide an interrupt signal processing circuit that can notify the user.

[0005]

In order to achieve the above object, the interrupt signal processing circuit of the present invention has the following configuration. That is, various devices that generate interrupt requests and CP
An interrupt signal processing circuit interposed between U and for processing an interrupt signal, the power-on reset means outputting a power-on reset signal when the power of the device is turned on, and the power-on reset period. Storage means for discriminating and storing the active level of each interrupt request signal of the various devices, and whether or not the interrupt request signal is output from the various devices according to the signal level stored in the storage means. Means for detecting and notifying the CPU.

[0006]

In the above structure, the active level of each interrupt request signal of each device is discriminated and stored within the power-on reset period when the power of the apparatus is turned on. According to the stored signal level, it detects whether an interrupt request signal is output from various devices and notifies the CPU of the generation of the interrupt request.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

Before describing the configuration of the interrupt signal processing circuit of this embodiment, the overall configuration of the circuit using this interrupt signal processing circuit will be described with reference to FIG.

In FIG. 3, 301 is a power supply for supplying power to the entire apparatus, and 302 is a power switch for turning on / off the power supply 301. 303 is power on
In the reset circuit, when the power switch 302 of the power source 301 is turned on, the power-on reset signal 9 having a predetermined pulse width is output at a low level. Each of 304-306 represents a respective device, and each of these devices can generate an interrupt request. 307-30
Each of 9 is an interrupt signal processing circuit provided corresponding to each device, the details of which are shown in FIG. Three
Reference numeral 10 denotes a priority encoder which inputs an interrupt signal 11 from each of the interrupt signal processing circuits 307 to 309, determines the priority order thereof, and outputs an interrupt request to the CPU 311.

FIG. 1 is a block diagram of an interrupt signal processing circuit (307 to 309) according to an embodiment of the present invention, and FIG. 2 is a timing chart showing how the circuit of FIG. 1 operates.

In FIG. 1, reference numeral 1 is a detection period generator, which is an interrupt request signal 10 within the power-on reset time.
The timing signal 12 is output to detect whether the signal is at a high level or a low level. 2 is AN
The D gate outputs the interrupt request signal level to the latch 3 during the detection period (when the timing signal 12 is at the high level). A latch circuit 3 latches the signal level of the interrupt request signal 10 output from the AND gate 2 during the detection period. Reference numerals 4 and 5 are inverter circuits, 6 and 7 are AND gates, and 8 is an OR gate.

Reference numeral 9 is a power-on reset signal, and 10 is an interrupt request signal output from the corresponding device. Reference numeral 12 denotes a timing signal indicating that the latch circuit 3 is detected, and 13 is a timing signal detected during the detection period.
Indicates the signal level that is latched at, and this signal level is held during system startup.

The configuration example of FIG. 1 will be described below with reference to the timing chart of FIG.

First, when the power switch 302 of the system is turned on at timing T1 and the power is turned on, the power-on reset circuit 303 outputs the power-on reset signal 9 at a low level to start the power-on reset period. . When the power-on reset signal 9 becomes low level, the detection period generation circuit 1 is activated, and the timing signal 12 becomes high level at timing T2. The interrupt request signal 10 at this time is gated by the AND gate 2, and if the interrupt request signal 10 is high level, a high level signal is output, and if the interrupt request signal 10 is low level, a low level signal is output from the AND gate 2. Therefore, the state of the interrupt request signal 10 during this detection period is latched and held by the latch circuit 3, and the signal level thereof is output from the latch circuit 3 as the hold signal level 13 during system startup.

By the way, while the power-on reset signal 9 is at the low level, each device is naturally in the reset state and the interrupt request signal 10 should not be active. That is, the fact that each of these devices actually outputs the interrupt request and activates the interrupt signal 10 is opposite to the signal level currently held in the latch circuit 3. For example, as shown in FIG. 2, when the signal level of the interrupt request signal 10 during this detection period is low, this device actually outputs the interrupt request signal 1
When 0 is activated, this interrupt request signal 10
The signal level of should be high level.

To specifically explain this case, at the timing of FIG. 2, the holding signal level 13 output from the latch circuit 3 is at a low level, so that the output of the AND gate 7 is always fixed at a low level. On the other hand, since the hold signal level 13 is inverted by the inverter circuit 4, the output of the AND gate 6 depends on the state of the interrupt request signal 10. Therefore, if the interrupt request signal line 10 is low level, the output of the AND gate 6 also becomes low level, and at this time, the interrupt signal 11 which is the output from the OR gate 8 also becomes low level.

Further, at timing T3, the interrupt request signal 1
When 0 goes high, the output of the AND gate 6 goes high, which causes the interrupt signal 11 to go high. As described above, in this case, the interrupt request signal 1
When 0 is at low level, the corresponding device is not outputting an interrupt request, and when interrupt request signal 10 is at high level, it indicates that an interrupt is requested. Therefore, when an interrupt request is output from the device, the output of the AND gate 6 becomes high level, and the interrupt signal 11 is output as active high.

In this way, this condition is always held while the system is running, and this hold signal level 1
The relationship between 3 and the actual signal level of the interrupt request signal 10 is guaranteed.

FIG. 4 is a flow chart showing the operation of this interrupt signal processing circuit.

When the power of the device is turned on and the power-on reset signal 9 becomes low level, this power-on
The timing signal 12 is output at a high level during the reset period. As a result, the interrupt request signal 1 at this time
A signal level corresponding to the signal level of 0 is latched by the latch circuit 3 (steps S2 and S3). Then, when the interrupt request signal 10 having a signal level different from the holding signal level 13 held in the latch circuit 3 is input in step S4 or step S5, the interrupt signal 11 is output at a high level in step S6.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program for implementing the present invention to a system or an apparatus.

As described above, according to this embodiment, the signal level of the interrupt request signal of each device that generates an interrupt request is detected during the power-on reset, and this is stored and stored in each device. The interrupt request can be accepted according to the active level of the interrupt request signal of. As a result, it is possible to design the system with a higher degree of freedom, and it is possible to determine the interrupt request of each device without setting the condition of the interrupt register by software or the like.

[0023]

As described above, according to the present invention, the active level of the interrupt signal from each device is detected during the power-on reset, and the active state of the interrupt signal of each device is automatically determined. Then, the CPU can be notified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an interrupt signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the interrupt signal processing circuit of this embodiment.

FIG. 3 is a block diagram showing an overall configuration of an apparatus using the interrupt signal processing circuit of this embodiment.

FIG. 4 is a flowchart illustrating an operation of the interrupt signal processing circuit according to the present exemplary embodiment.

[Explanation of symbols]

1 Detection period generation circuit 2, 6, 7 AND gate 3 Latch circuit 4,5 inverter circuit 8 OR gate 9 Power-on reset signal 10 Interrupt request signal 11 Interrupt signal 12 Timing signal 13 Hold signal level 301 power supply 302 power switch 303-306 devices 307-309 Interrupt signal processing circuit 310 priority encoder 311 CPU

Claims (2)

[Claims] 1. Various devices that generate interrupt requests and C
An interrupt signal processing circuit intervening with the PU for processing an interrupt signal, the power-on reset means outputting a power-on reset signal when the power of the device is turned on, and within the power-on reset period. A storage means for discriminating and storing the active level of each interrupt request signal of the various devices, and detecting whether or not the interrupt request signal is output from the various devices according to the signal level stored in the storage means. And means for notifying the CPU of the interrupt signal processing circuit. 2. The active level of the interrupt request signal from the various devices is determined as being the inversion of the signal level of the interrupt request signal within the power-on reset period. The interrupt signal processing circuit according to Item 1.