JPH05199097A - Input protection circuit and output buffer circuit - Google Patents

Abstract

PURPOSE:To provide the input protection circuit and the output buffer circuit not giving any effect on the operation and the characteristic of the integrated circuit device. CONSTITUTION:An input signal 11 is connected to a drain of an NMOSTQn, of the input protection circuit 1, a gate of an NMOSTQn is connected to a node V11 via a resistor 11, and a source of an NMOSTQn11 connects to a ground voltage VSS. The node V11 is a node connecting to a constant voltage source with a lower potential than the ground voltage VSS. When a signal with an abnormally high voltage such as surge is inputted externally to an input signal I1 of the input protection circuit, a high voltage is applied to a drain of the NMOSTQn11, the voltage of the NMOSTQn11 is boosted and a current flows to the source of the NMOSTQn11 connecting to the ground voltage VSS from the drain of the NMOSTQn11 to protect the internal circuit connecting to the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit and an output buffer circuit.

[0002]

2. Description of the Related Art In recent years, the development of semiconductor integrated circuit devices has been remarkable, and an input protection circuit and an output buffer circuit of the integrated circuit device are important circuit parts for protecting the integrated circuit device from an abnormal signal from the outside such as a surge. is there.

First, a conventional input protection circuit will be described with reference to FIG. 11 showing a conventional example.

In this input protection circuit, an input signal I11 is connected to the drain of an N-channel type MOS transistor (NMOST) Qn111, and the gate of the NMOSTQn111 has a resistor R.
It is connected to the ground voltage VSS via 111 and the NMOS TQn111
The source of is connected to the ground voltage VSS.

When an abnormally high voltage signal such as a surge is input to the input signal I11 of the input protection circuit from the outside, the NMO
A high voltage is applied to the drain of STQn111, which causes NMOS TQn1
The voltage of the gate of 11 is raised and the NMOS TQn111 is connected to the ground voltage VSS from the drain of the NMOS TQn111.
The current flowing through the source protects the internal circuit to which the input signal is connected.

Next, regarding the conventional output buffer circuit,
This will be described with reference to the figure showing the conventional example of FIG.

In this output buffer circuit, the control signal A12 is input to the NOT circuit that outputs the node N121, and the node N12
The node N121 and the control signal B12 are input to the NAND circuit that outputs 2 and the node N122 is input to the NOT circuit that outputs the node N123. Then, the control signal A12 and the control signal B12 are input to the NAND circuit that outputs the node N124, and the NAND circuit that outputs the node N125 outputs the node N124.
Is entered. The node N123 is input to the gate of the NMOS TQn121, the source of the NMOS TQn121 is connected to the ground voltage VSS, and the drain of the NMOS TQn121 is connected to the output signal O12. Further, the node N125 is input to the gate of the NMOS TQn122, the drain of the NMOS TQn122 is connected to the power supply voltage VCC, and the source of the NMOS TQn122 is connected to the output signal O12.

When an abnormally high voltage signal such as a surge is input to the output signal O12 of the output buffer circuit from the outside,
A high voltage is applied to the drain of the NMOS TQn121 and the source of the NMOS TQn122, and the gate of the NMOS TQn121 and N
The gate voltage of MOSTQn122 is raised and NMO
NM connected to the ground voltage VSS from the drain of STQn121
Current flows to the source of the OSTQn121 and to the drain of the NMOS TQn122 connected to the power supply voltage VCC from the source of the NMOS TQn122 to protect the internal circuit to which the output signal is connected.

The operation of the output buffer circuit will be briefly described. The control signal A12 is an output signal level control signal and the control signal B12 is an output signal control signal. Control signal B
When the logic voltage of 12 is "L", the logic voltage of the node N123 and the node N125 becomes "L", and the NMOS TQn121
And the NMOS TQn122 are both off, and the output signal O12 is in a high impedance state. When the logic voltage of the control signal B12 is "H", the output signal O12 is in the output state, and when the logic voltage of the control signal A12 is "L", the node N123.
, The logic voltage of the node N125 becomes "L", and the output signal O12 becomes the output state of the logic voltage "L". When the logic voltage of the control signal A12 is "H", the logic voltage of the node N123 is "L", the logic voltage of the node N125 is "H", and the output signal O12 is in the output state of the logic voltage "H". ..

[0010]

In the above-mentioned conventional input protection circuit, when the potential level of the input signal given from the outside is lower than the ground voltage, for example, in the case of the embodiment of the input protection circuit of FIG. A current flows from the ground voltage VSS which is the source to the input signal I11 which is the drain of the NMOS TQn111. At this time, if the substrate voltage is applied to the NMOS TQn111, the substrate current flows and the substrate voltage becomes shallow. Therefore, the operation and characteristics of the integrated circuit device are affected. The same applies to the case of the conventional output buffer circuit, and when the potential level of the output signal given from the outside is lower than the ground voltage, the output buffer circuit of FIG. 12 changes the source voltage of the NMOS TQn121 from the ground voltage VSS to the drain of the NMOS TQn121. A current flows through a certain output signal O12. Also, from the power supply voltage VCC which is the drain of the NMOS TQn122 to the output signal O1 which is the source of the NMOS TQn122.
Current flows to 2. At this time, NMOSTQn121, NMO
When the substrate voltage is applied to STQn122, the substrate current flows, the substrate voltage becomes shallow, and the current consumption increases. Therefore, the operation and characteristics of the integrated circuit device are affected. Further, in the case of this embodiment, the output capacitance increases because the drain of the NMOS TQn121 that outputs the logic voltage "L" and the source of the NMOS TQn122 that outputs the logic voltage "H" are both connected to the output signal O12. There was a point.

[0011]

In the input protection circuit of the present invention, the input signal is connected to the drain of the NMOST, the source of the NMOST is connected to the ground voltage, and the NMO is connected.
The structure is such that the gate of ST is connected to a voltage source lower than the ground voltage.

In the input protection circuit of the present invention, the input signal is first
Of the first NMO connected to the drain of the NMOST of
The source of ST is connected to the drain of the second NMOST, the source of the second NMOST is connected to the ground voltage, the gate of the first NMOST is connected to a voltage source lower than the ground voltage, and the second The gate of the NMOST is connected to the ground voltage.

In the input protection circuit of the present invention, the input signal is the first
Connected to the drain and gate of the NMOST of
The source of the NMOST is connected to the drain of the second NMOST, the source of the second NMOST is connected to the ground voltage, and the gate of the second NMOST is connected to the ground voltage.

The output buffer circuit of the present invention comprises a first NM
The gate and source of the OST are connected to the output signal, the drain of the first NMOST is connected to the source of the second NMOST, and the drain of the second NMOST is connected to the power supply voltage.

The output buffer circuit of the present invention is an NMOST.
The source or drain of N is connected to the output signal,
The configuration is such that the signal input to the gate of the MOST is connected to a voltage source whose logic voltage of "L" is lower than the ground voltage.

The output buffer circuit of the present invention comprises a first NM
The drain or source of the OST is connected to the output signal,
The signal input to the gate of the first NMOST is the second
Of the second NMOST is connected to the source or the drain of the second NMOST, the drain or the source of the second NMOST is connected to the output signal, and the gate of the second NMOST is connected to the ground voltage.

The output buffer circuit of the present invention comprises a first NM
The drain of the OST is connected to the output signal, and the first N
The signal input to the gate of the MOST is the second NMOST
Of the second NMOST, the drain of the second NMOST is connected to the output signal, and the gate of the second NMOST is connected to the opposite phase signal of the output signal.

The output buffer circuit of the present invention comprises a first NM
The drain of the OST is connected to the output signal, and the first N
The source of the MOST is connected to the drain of the second NMOST and the source of the third NMOST, and the second NM
The source of OST is connected to the ground voltage, and the third NM
The drain of the OST is connected to the power supply voltage.

[0019]

With the input protection circuit and the output buffer circuit having such a configuration, even when the potential levels of the input signal and the output signal given from the outside are lower than the ground voltage, the substrate voltage does not become shallow, and the consumption is reduced. The current is small and the operation and characteristics of the integrated circuit device are stable. Further, the output buffer circuit has a small output capacity.

[0020]

First, a first embodiment of the input protection circuit of the present invention will be described with reference to FIG.

In this input protection circuit, the input signal I1 is NMO.
It is connected to the drain of STQn11 and the gate of NMOSTQn11 is connected to the node V11 via the resistor R11.
The source of Qn11 is connected to the ground voltage VSS.
Here, the node V11 is a node connected to a constant voltage source having a potential lower than the ground voltage VSS.

When an abnormally high voltage signal such as a surge is input to the input signal I1 of this input protection circuit, the NMO
A high voltage is applied to the drain of STQn11, which causes NMOS TQn11
The voltage of the gate is raised and a current flows from the drain of the NMOS TQn11 to the source of the NMOS TQn11 connected to the ground voltage VSS, thereby protecting the internal circuit to which the input signal is connected.

The characteristic of this input protection circuit is that even if the input signal I1 has a potential lower than the ground voltage VSS, the input signal I1
If the potential of the node V11 is lower than the potential of
From the ground voltage VSS which is the source of STQn11 to NMOS TQn1
No current flows in the input signal I1 which is the drain of 1, so that even if the substrate voltage is applied to the NMOS TQn11, the substrate current does not flow, the substrate voltage does not become shallow, and the current consumption is small.

Next, a second embodiment of the input protection circuit of the present invention will be described with reference to FIG. In this input protection circuit, the input signal I2 is connected to the drain of the NMOS TQn21, and the gate of the NMOS TQn21 is connected to the node V via the resistor R21.
21 connected to the source of NMOS TQn21 (node N21)
Is connected to the drain of NMOS TQn22,
The gate of 22 is connected to ground voltage VSS via resistor R22,
The source of the NMOS TQn21 is connected to the ground voltage VSS. Here, the node V21 is a node connected to a constant voltage source having a potential lower than the ground voltage VSS.

When an abnormally high voltage signal such as a surge is input to the input signal I2 of the input protection circuit, NMO
A high voltage is applied to the drain of STQn21, causing an NMOS TQn21
The gate voltage of the NMOS TQn22 is raised, a high voltage is applied to the drain of the NMOS TQn22, the gate voltage of the NMOS TQn22 is raised, and the NMO of the drain of the NMOS TQn21 is increased.
By flowing a current through the drain of STQn22 to the source of NMOS TQn22 connected to the ground voltage VSS,
The internal circuit connected to the input terminal is protected.

The feature of this input protection circuit is that the potential of the node V21 is lower than the potential of the input signal I2 even if the input signal I2 is lower than the ground voltage VSS as in the first embodiment. For example, from the source of NMOS TQn21 to NMOS
No current flows through the drain of TQn21, so the NMOST
Even if the substrate voltage is applied to Qn21, the substrate current does not flow, the substrate voltage does not become shallow, and the current consumption is small.

Next, a third embodiment of the input protection circuit of the present invention will be described with reference to FIG. In this input protection circuit, the input signal I3 is connected to the drain and gate of the NMOS TQn31, and the source (node N31) of the NMOS TQn31 is N.
It is connected to the drain of MOSTQn32, the gate of NMOSTQn32 is connected to the ground voltage VSS via the resistor R31, and NM
The source of OSTQn31 is connected to the ground voltage VSS.

When an abnormally high voltage signal such as a surge is input to the input signal I3 of the input protection circuit, the NMO
A high voltage is applied to the drain and gate of STQn31, and a high voltage is applied to the drain of NMOS TQn32.
The gate voltage of OSTQn32 is raised and the NMOST
A current flows from the drain of Qn31 through the drain of NMOS TQn32 to the source of NMOS TQn32 connected to the ground voltage VSS, thereby protecting the internal circuit connected to the input terminal.

This input protection circuit is characterized in that even if the input signal I3 has a potential lower than the ground voltage VSS, the input signal I3
Is input to the drain and gate of the NMOS TQn31, no current flows from the source of the NMOS TQn31 to the drain of the NMOS TQn31. Therefore, even if the substrate voltage is applied to the NMOS TQn21, the substrate current does not flow and the substrate voltage becomes shallow. Of course, the current consumption is low. Compared with the first and second embodiments, a constant voltage source having a potential lower than the ground voltage VSS is not required, and the same effect as the first and second embodiments is obtained.

Next, a first embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A4 is input to the NOT circuit that outputs the node N41, and the node N42
Node N41 and control signal B
4 is input and a node is connected to the NOT circuit that outputs the node N43.
N42 is input, the control signal A4 and the control signal B4 are input to the NAND circuit that outputs the node N44, and the node N44 is input to the NOT circuit that outputs the node N45.
Node N43 is input to the gate of TQn41, and NMOS TQn4
The source of 1 is connected to the ground voltage VSS, the drain of NMOSTQn41 is connected to the output terminal O4, the node N45 is input to the gates of NMOSTQn42 and NMOSTQn43, and the drains of NMOSTQn42 and NMOSTQn43 are connected to the power supply voltage VCC. , The source of NMOSTQn43 is connected to the drain of NMOSTQn44,
Source of Qn42 and NMOS TQn Source and NMOS TQn
The gate of 43 is connected to the output terminal O4.

When an abnormally high voltage signal such as a surge is input to the output terminal O4 of the output buffer circuit from the outside, N
A high voltage is applied to the drain of the MOSTQn41, the source of the NMOSTQn42 and the source of the NMOSTQn44,
Gate of TQn41 and NMOS Gate of TQn42 and NMO
By raising the gate voltage of STQn43,
The drain of the NMOS TQn41 is connected to the source of the NMOS TQn41 connected to the ground voltage VSS, the source of the NMOS TQn42 is connected to the drain of the NMOS TQn42 connected to the power supply voltage VCC, and the source of the NMOS TQn44 is connected to the NMOS TQn44.
NM connected to power supply voltage VCC through the source of Qn43
A current flows through the drain of OSTQn43, and the internal circuit to which the output signal is connected is protected.

The operation of the output buffer circuit will be briefly described. The control signal A4 is an output signal level control signal and the control signal B4 is an output signal control signal. Control signal B4
, The logic voltage of the node N43 and the logic voltage of the node N45 are "L", the NMOS TQn41, the NMOS TQn42 and the NMOS TQn43 are all off, and the output terminal O4 is in a high impedance state. When the logic voltage of the control signal B4 is "H", the output terminal O4 is in the output state, and when the logic voltage of the control signal A4 is "L", the logic voltage of the node N43 is "H" and the node N45. When the logic voltage of the node N43 is "L", the output terminal O4 is in the output state of the logic voltage "L", and the logic voltage of the control signal A4 is "H", the logic voltage of the node N43 is "L" and the logic voltage of the node N45 is The logic voltage becomes "H", and the output terminal O4 becomes the output state of the logic voltage "H".

The characteristic of this output buffer circuit is that when the output terminal O4 is at a potential lower than the ground voltage VSS, the NMO
Regarding STQn41 and NMOS TQn42, each NM
A current flows through the OST. However, regarding the NMOS TQn44, since the output terminal O4 is input to the drain and gate of the NMOS TQn44, the source of the NMOS TQn43 becomes N.
No current flows in the drain of MOSTQn43, so NM
Even if the substrate voltage is applied to OSTQn43, the substrate current does not flow, the substrate potential does not easily become shallow, and the current consumption is small.

Next, a second embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A5 is input to the NOT circuit which outputs the node N51, and the node N52
Node N51 and control signal B in the AND circuit that outputs
5 is input to the NOT circuit that outputs the node N53 as a node
N52 is input, the control signal A5 and the control signal B5 are input to the NAND circuit that outputs the node N54, and the node N54 is input to the NOT circuit that outputs the node N55.
Node N53 is input to the gate of TQn53, and NMOS TQn5
The source of 3 is connected to the ground voltage VSS, the drain of the NMOS TQn53 is connected to the output terminal O5, the node N55 is input to the gate of the NMOS TQn54, the drain of the NMOS TQn54 is connected to the power supply voltage VCC, and the source of the NMOS TQn54 is output terminal O5. It is a configuration connected to. However, the node
The source and NMOS of each NMOS TQn51 of the NOT circuit that outputs N53 and the NOT circuit that outputs the node N55
The source of TQn52 is a node V51 connected to a constant voltage source having a potential lower than the ground voltage VSS.

When an abnormally high voltage signal such as a surge is input to the output terminal O5 of the output buffer circuit from the outside, N
A high voltage is applied to the drain of MOSTQn53 and the source of NMOSTQn54, and the gate of NMOSTQn53 and NMOS
The gate voltage of TQn54 is raised and NMOS TQn53
NMOS TQn5 connected from ground drain to ground voltage VSS
Current flows to the source of 3 and to the drain of the NMOS TQn54 connected to the power supply voltage VCC from the source of the NMOS TQn54, thereby protecting the internal circuit connected to the output terminal.

The operation of this output buffer circuit is similar to that of the first embodiment, and the control signal A5 is the output signal level control signal and the control signal B5 is the output signal control signal. When the logic voltage of the control signal B5 is "L", the output terminal O5 is in a high impedance state. When the logic voltage of the control signal B5 is "H", the output terminal O4 is in the output state, and when the logic voltage of the control signal A5 is "L", the output terminal O5 is in the output state of the logic voltage "L". When the logic voltage of the control signal A5 is "H", the output terminal O5 is in the output state of the logic voltage "H".

The feature of this output buffer circuit is that even if the output terminal O5 has a potential lower than the ground voltage VSS, the NMO
Since the logic voltage of "L" at the gates of STQn53 and NMOS TQn54 is a potential lower than the ground voltage VSS (potential of the constant voltage source node V51 lower than the ground voltage VSS), the NMOS TQ
From the source of n53 to the drain of NMOS TQn53, and N
No current flows from the drain of the MOSTQn54 to the source of the NMOSTQn54.
Even if the substrate voltage is applied to Qn54, the substrate current does not flow, the substrate potential does not easily become shallow, and the current consumption is small.

Next, a third embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A6 is input to the NOT circuit which outputs the node N61, and the node N62
The node N61 and control signal B
6 is input and the node is connected to the NOT circuit that outputs the node N63.
N62 is input, the control signal A6 and the control signal B6 are input to the NAND circuit that outputs the node N64, and the node N64 is input to the NOT circuit that outputs the node N65.
Node N63 is input to the gate of TQn63, and NMOS TQn6
The source of 3 is connected to the ground voltage VSS, the drain of NMOS TQn63 is connected to the output terminal O6, the node N65 is input to the gate of NMOS TQn64, the drain of NMOS TQn64 is connected to the power supply voltage VCC, and the source of NMOS TQn64 is the output terminal O6. , The gate of the NMOS TQn65 is connected to the ground voltage VSS, the source of the NMOS TQn65 is connected to the node N63, the drain of the NMOS TQn65 is connected to the output terminal O6, and the gate of the NMOS TQn66 is connected to the ground voltage VS.
It is connected to S, the drain of the NMOS TQn66 is connected to the node N65, and the source of the NMOS TQn66 is connected to the output terminal O6.

When an abnormally high voltage signal such as a surge is input from the outside to the output terminal O6 of this output buffer circuit,
The drain of NMOS TQn63, the source of NMOS TQn64,
A high voltage is applied to the drain of NMOS TQn65 and the source of NMOS TQn66, and the gate of NMOS TQn63 and NM
OSTQn64 gate, NMOS TQn65 gate, and N
The gate voltage of MOSTQn66 is raised and NMOS
NMO connected from the drain of TQn63 to the ground voltage VSS
By flowing a current to the source of STQn63 and from the source of NMOS TQn64 to the drain of NMOS TQn64 connected to the power supply voltage VCC, the internal circuit connected to the output terminal is protected.

The operation of this output buffer circuit is similar to that of the first embodiment. The feature of this output buffer circuit is that when the output terminal O6 is at a potential lower than the ground voltage VSS, a current flows through the NMOS TQn66 and the NMOS TQn65 and the potential at the nodes N63 and N65 becomes lower than the ground voltage VSS, and the drain of the NMOS TQn63 from the source of the NMOS TQn63. And from the drain of NMOST Qn64 to NMOST
It is difficult for the current to flow to the source of Qn64, so the NMOST
Even if the substrate voltage is applied to the Qn63 and the NMOS TQn64, the substrate current does not flow and the substrate voltage does not easily become shallow, and the current consumption is small. NMOS TQn66, NMOS TQn65 and NMO
The transistor size is designed so that the current flowing through STQn62 and NMOS TQn61 is reduced. Also, the NMOS TQn66 and NMOS TQn65 of this output buffer circuit configuration are
Plays the role of NMOST in the case of the above surge.
The voltage of the gate of Qn63 (node N63) and the gate of NMOS TQn64 (node N65) is easily lifted, and it is also resistant to surge.

Next, a fourth embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A7 is input to the NOT circuit which outputs the node N71, and the node N72
Node N71 and control signal B in the AND circuit that outputs
7 is input to the NOT circuit that outputs the node N73 as a node
N72 is input, the control signal A7 and the control signal B7 are input to the NAND circuit that outputs the node N74, and the node N74 is input to the NOT circuit that outputs the node N75.
Node N73 is input to the gate of TQn73, and NMOS TQn7
The source of 3 is connected to the ground voltage VSS, the drain of the NMOS TQn73 is connected to the output terminal O7, the node N75 is input to the gate of the NMOS TQn74, the drain of the NMOS TQn74 is connected to the power supply voltage VCC, and the source of the NMOS TQn74 is output terminal O7. , The gate of the NMOS TQn75 is connected to the node N76, and the source of the NMOS TQn75 is connected to the node N76.
Connected to 73, the drain of NMOS TQn75 is output terminal O7
, The gate of the NMOS TQn76 is connected to the node N76, the drain of the NMOS TQn76 is connected to the node N75, the source of the NMOS TQn76 is connected to the output terminal O7, and the output terminal O7 is input to the NOT circuit that outputs the node N76. It has a different structure.

When an abnormally high voltage signal such as a surge is input to the output terminal O7 of the output buffer circuit from the outside, N
A high voltage is applied to the drain of the MOSTQn73 and the source of the NMOSTQn74, and the gate of the NMOSTQn73 and the NMOS
The gate voltage of TQn74 is raised and the NMOS TQn73
NMOS TQn7 connected from ground drain to ground voltage VSS
By flowing a current to the source of 3 and to the drain of the NMOS TQn74 connected to the power supply voltage VCC from the source of the NMOS TQn74, the internal circuit connected to the output terminal is protected.

The operation of this output buffer circuit is similar to that of the first embodiment. The feature of this output buffer circuit is that even if the output terminal O7 is at a potential lower than the ground voltage VSS, the node N76 becomes a logic voltage “H”, the nodes N73 and N75 are at a potential lower than the ground voltage VSS, and the NMOS
From the source of TQn73 to the drain of NMOS TQn73 and N
It is difficult for current to flow from the drain of the MOSTQn74 to the source of the NMOSTQn74.
Even if the substrate voltage is applied to STQn74, the substrate current does not flow, the substrate voltage does not easily become shallow, and the current consumption is small. Here, the threshold value of the NOT circuit that outputs the node N76 is designed to be a value close to the ground voltage VSS so that the logic voltage becomes "H" only when the output terminal O7 is lower than the ground voltage VSS. In addition, actually, the negation circuit which outputs the node N76 and the current flowing through the NMOS TQn71 and the NMOS TQn72 are designed to be small.

Next, a fifth embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A8 is input to the NOT circuit which outputs the node N81, and the node N82
Is connected to the logical AND negation circuit that outputs
8 is input, and the node is connected to the NOT circuit that outputs the node N83.
N82 is input, the control signal A8 and the control signal B8 are input to the NAND circuit that outputs the node N84, and the node N84 is input to the NOT circuit that outputs the node N85.
Node N83 is input to the gate of TQn81, and NMOS TQn8
The source of 1 is connected to the ground voltage VSS, the drain of NMOS TQn81 is connected to the source of NMOS TQn83, and NMO
Node N85 is input to the gate of STQn82, and NMOS TQ
The drain of n82 is connected to the power supply voltage VCC, and NMOSTQn
The source of 82 is connected to the source of NMOS TQn83,
The control signal B8 is input to the gate of the OSTQn83, and the NMOS
The drain of TQn83 is connected to the output terminal O8.

When an abnormally high voltage signal such as a surge is input to the output terminal O8 of the output buffer circuit, N
High voltage is applied to the drain of MOSTQn83,
The gate voltage of Qn83 is raised, and further, NMOS
A high voltage is applied to the drain of TQn81 and the source of NMOS TQn82, and the gate of NMOS TQn81 and NMOS TQn82
The gate voltage is raised and the drain voltage of NMOS TQn83 passes through the drain of NMOS TQn81 to the ground voltage VS.
To the source of NMOS TQn81 connected to S, and NMO
A current flows from the drain of STQn83 through the source of NMOS TQn82 to the drain of NMOS TQn82 connected to the power supply voltage VCC, thereby protecting the internal circuit to which the output signal is connected.

The operation of this output buffer circuit is similar to that of the first embodiment. This output buffer circuit is characterized by an NMOST for outputting a logical voltage "L".
NM for outputting the drain of Qn81 and logic voltage "H"
Since the source of the OSTQn82 is not directly connected to the output terminal O8 but is connected to the output terminal O8 via the NMOS TQn83, the output capacitance of the output terminal O8 becomes small.

Next, a sixth embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A9 is inputted to the NOT circuit which outputs the node N91, and the node N92 is supplied.
The node N91 and the control signal B
9 is input and the node is connected to the NOT circuit that outputs the node N93.
N92 is input, the control signal A9 and the control signal B9 are input to the logical sum NOT circuit that outputs the node N94, and the node N94 is input to the NOT circuit that outputs the node N95.
Node N93 is input to the gate of TQn92, and NMOS TQn9
The source of 2 is connected to the ground voltage VSS, the drain of NMOS TQn92 is connected to the source of NMOS TQn94, and NMO
The node N95 is input to the gate of STQn93, and the NMOS TQ
The drain of n93 is connected to the power supply voltage VCC, and NMOSTQn
The source of 93 is connected to the source of NMOS TQn94, and the control signal B9 is input to the NOT circuit that outputs the node N96.
The node N96 is input to the NOT circuit that outputs the node N97, and the node N97 is input to the gate of the NMOS TQn94.
The drain of the NMOS TQn94 is connected to the output terminal O9. However, the source of the NMOS TQn91 of the NOT circuit that outputs the node N97 is the node V91 connected to the constant voltage source whose potential is lower than the ground voltage VSS.

When an abnormally high voltage signal such as a surge is input to the output terminal O9 of this output buffer circuit from the outside, N
High voltage is applied to the drain of MOSTQn94,
The gate voltage of Qn94 is raised, and further, NMOS
A high voltage is applied to the drain of TQn92 and the source of NMOS TQn93, and the gate of NMOS TQn92 and NMOS TQn93
The gate voltage is raised, and the drain voltage of the NMOS TQn94 passes through the drain of the NMOS TQn92 to the ground voltage VS.
To the source of NMOS TQn92 connected to S, and NMO
A current flows from the drain of STQn94 through the source of NMOS TQn93 to the drain of NMOS TQn93 connected to the power supply voltage VCC, thereby protecting the internal circuit to which the output signal is connected.

The operation of this output buffer circuit is similar to that of the first embodiment. This output buffer circuit is characterized by an NMOST for outputting a logical voltage "L".
NM for outputting the drain of Qn92 and logic voltage "H"
Since the source of OSTQn93 is not directly connected to the output terminal O9 but is connected to the output signal O9 via the NMOS TQn94, the output capacitance of the output terminal O9 becomes small. Even if the output terminal O9 has a potential lower than the ground voltage VSS, the NMO
Since the logic voltage of “L” at the gate of STQn94 is lower than the ground voltage VSS, the current does not flow from the source to the drain of the NMOS TQn94 and the substrate current does not flow even if the substrate voltage is given to the NMOS TQn94, and the substrate voltage is It is not shallow and consumes less current.

Next, a seventh embodiment of the output buffer circuit of the present invention will be described with reference to FIG.

In this output buffer circuit, the control signal A10 is input to the NOT circuit which outputs the node N101,
The node N101 and the control signal B10 are input to the logical sum NOT circuit that outputs 2 and the node N102 is input to the logical NOT circuit that outputs the node N103, and the control signal is input to the logical sum NOT circuit that outputs the node N104. A10 and the control signal B10 are input, the node N104 is input to the NOT circuit that outputs the node N105, the node N103 is input to the gate of the NMOS TQn103, the source of the NMOS TQn103 is connected to the ground voltage VSS, and the drain of the NMOS TQn103 is connected to the NMOS TQn105. Connected to the source of the NMOS TQn104 and the gate of the node N10
5 is input, the drain of NMOS TQn104 is the power supply voltage VC
C is connected, and the source of NMOSTQn104 is NMOSTQn
The control signal B10 is input to the NOT circuit that is connected to the source of 105 and outputs the node N106, and the node N106 is input to the NOT circuit that outputs the node N107.
Node N107 is input to the gate of the NMOS TQn105, the drain of the NMOS TQn105 is connected to the output terminal O10, the source of the NMOS TQn106 is connected to the node N107, the drain of the NMOS TQn106 is connected to the output terminal O10, and the gate of the NMOS TQn106 is the reverse of the output terminal O10. This is a configuration in which a phase signal is input.

When an abnormally high voltage signal such as a surge is input to the output terminal O10 of this output buffer circuit from the outside,
High voltage is applied to the drain of NMOS TQn105,
The gate voltage of STQn105 is raised and N
A high voltage is applied to the drain of the MOSTQn103 and the drain of the NMOSTQn104, and the gate of the NMOSTQn103 and N
The gate voltage of MOSTQn104 is raised and NMO
From the drain of STQn105 to the source of NMOSTQn103 connected to the ground voltage VSS through the drain of NMOSTQn103, and from the drain of NMOSTQn105 to NMOSTQ.
NMO connected to power supply voltage VCC through the source of n104
The current flowing through the drain of STQn104 protects the internal circuit to which the output signal is connected.

The operation of this output buffer circuit is similar to that of the first embodiment. This output buffer circuit is characterized by an NMOST for outputting a logical voltage "L".
N for outputting the drain of Qn103 and logic voltage "H"
Since the source of the MOSTQn104 is not directly connected to the output terminal O10 but is connected to the output terminal O10 via the NMOSTQn105, the output capacitance of the output terminal O10 is small.
Even if the output terminal O10 has a potential lower than the ground voltage VSS, the node N109 becomes the logic voltage “H” and the NMOS TQn
The gate of 105 has a potential lower than the ground voltage VSS of the output terminal O10, current does not flow from the source to the drain of the NMOS TQn105, and the substrate current does not flow even if the substrate voltage is given to the NMOS TQn105, and the substrate voltage does not become shallow and is consumed. The current is also small. Here, the threshold value of the NOT circuit that outputs the node N109 is designed to be a value close to the ground voltage VSS, and only when the output terminal O10 has a potential lower than the ground voltage VSS, the logical voltage “H” is set.
I am trying to be. Further, in reality, the negation circuit which outputs the node N109 and the current flowing through the NMOS TQn102 are designed to be small.

[0060]

As described above, by using the input protection circuit and the output buffer circuit of the present invention, the substrate voltage becomes shallow even when the potential levels of the input signal and the output signal given from the outside are lower than the ground voltage. In addition, the operation and characteristics of the integrated circuit device are stabilized and the output capacitance is reduced, which is a great effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an input protection circuit of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the input protection circuit of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the input protection circuit of the present invention.

FIG. 4 is a circuit diagram showing a first embodiment of an output buffer circuit of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the output buffer circuit of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the output buffer circuit of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the output buffer circuit of the present invention.

FIG. 8 is a circuit diagram showing a fifth embodiment of the output buffer circuit of the present invention.

FIG. 9 is a circuit diagram showing a sixth embodiment of the output buffer circuit of the present invention.

FIG. 10 is a circuit diagram showing a seventh embodiment of the output buffer circuit of the present invention.

FIG. 11 is a circuit diagram showing a conventional input protection circuit.

FIG. 12 is a circuit diagram showing a conventional output buffer circuit.

[Explanation of symbols]

 I1 Input signal V11 Node R11 Resistance Qn11 N-channel MOS transistor VSS Ground voltage

Claims (10)

[Claims] 1. An input signal is connected to a drain of an N-channel MOS transistor, and the N-channel MOS transistor is connected.
An input protection circuit, wherein a source of the transistor is connected to a ground voltage and a gate of the N-channel type MOS transistor is connected to a voltage source lower than the ground voltage. 2. An input signal is connected to a drain of a first N-channel type MOS transistor, a source of the first N-channel type MOS transistor is connected to a drain of a second N-channel type MOS transistor, and The source of the second N-channel MOS transistor is connected to the ground voltage, the gate of the first N-channel MOS transistor is connected to a voltage source lower than the ground voltage, and the gate of the second N-channel MOS transistor is connected. An input protection circuit characterized by being connected to a ground voltage. 3. An input signal is connected to a drain and a gate of a first N-channel type MOS transistor, and a source of the first N-channel type MOS transistor is a second N-channel type MOS transistor.
A drain of the channel type MOS transistor, a source of the second N channel type MOS transistor connected to a ground voltage, and a gate of the second N channel type MOS transistor connected to a ground voltage. Input protection circuit. 4. A gate and a source of a first N-channel MOS transistor are connected to an output signal, and the first N-channel MOS transistor is connected to an output signal.
The drain of the channel type MOS transistor is the second N
Connected to the source of the channel type MOS transistor,
An output buffer circuit, wherein the drain of the second N-channel type MOS transistor is connected to a power supply voltage. 5. The source or drain of the N-channel type MOS transistor is connected to an output signal, and the signal input to the gate of the N-channel type MOS transistor is connected to a voltage source whose logic voltage of "L" is lower than ground voltage. An output buffer circuit characterized by the above. 6. A drain or a source of the first N-channel MOS transistor is connected to an output signal, and a signal input to the gate of the first N-channel MOS transistor is of a second N-channel MOS transistor. A second N-channel type M transistor connected to a source or a drain, the drain or source of the second N-channel type MOS transistor connected to the output signal,
An output buffer circuit in which a gate of an OS transistor is connected to a ground voltage. 7. A drain of the first N-channel MOS transistor is connected to an output signal, and a signal input to the gate of the first N-channel MOS transistor is connected to a source of the second N-channel MOS transistor. An output, wherein the drain of the second N-channel type MOS transistor is connected to the output signal, and the gate of the second N-channel type MOS transistor is connected to a reverse phase signal of the output signal. Buffer circuit. 8. A drain of the first N-channel MOS transistor is connected to an output signal, and a source of the first N-channel MOS transistor is a drain of the second N-channel MOS transistor and a third N-channel. Type MOS transistor, the source of the second N-channel type MOS transistor is connected to the ground voltage, and the drain of the third N-channel type MOS transistor is connected to the power supply voltage. Output buffer circuit. 9. The output buffer according to claim 8, wherein the logic voltage of "L" of the signal input to the gate of the first N-channel MOS transistor is connected to a voltage source lower than the ground voltage. circuit. 10. A gate of a first N-channel MOS transistor is connected to a source of a fourth N-channel MOS transistor, and the fourth N-channel MOS transistor is connected.
9. The drain of the transistor is connected to an output signal, and the gate of the fourth N-channel type MOS transistor is connected to a reverse phase signal of the output signal.
The output buffer circuit described.