JPH05198794A - Mis-type field-effect transistor - Google Patents

Abstract

PURPOSE:To provide an MIS-type field effect transistor, reliability of which is increased by suppressing the generation of hot carriers to prevent the deterioration of device performance. CONSTITUTION:An MIS-type field-effect transistor is formed in such a manner that a gate-insulating film beneath a gate 2 is thick on a source side A1 (T1) and thin on a drain side A2, (T2), so that there is a difference in threshold voltage Vth between the thick film part A1 and the thin film part A2. Therefore, it acts just like a plurality of MIS-type field-effect transistors each having a different threshold voltage Vth, and a region in which pinch-off is liable to take place is dispersed into plural places, so that the generation of hot carriers conventionally concentrated into only drain end is dispersed and at the same time reduced, thereby preventing the deterioration of initial characteristics. Besides, the film thickness of a source of a gate-insulating film may be maintained to the same thickness as before, so that the generation of a leakage current and the increase of parasitic capacitance of a transistor may be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to a MIS field effect transistor (MISFET) element, and particularly to the reliability of a MIS field effect transistor having a short gate length, which is significantly deteriorated in performance by hot carriers. Technology related to improvement and extension of life.

[0002]

2. Description of the Related Art Ultra-high speed digital device series "Ultra-high speed MOS device" (Baifukan), page 259, as shown in FIG.
By dividing the voltage by inserting a dummy element, the voltage applied to a single MIS field effect transistor is reduced and hot carriers are suppressed. However, in this circuit configuration, the maximum value of the drain current is also limited, and high speed is sacrificed.

[0003]

In the submicron MIS field effect transistor element, since the gate length (channel length) is short, there is a region where the electric field strength is large in the vicinity of the drain diffusion layer. Carriers that have passed through a region having a high electric field strength thus obtain high energy and generate so-called hot carriers. Therefore, the initial characteristics such as a decrease in the transconductance of the MIS field effect transistor and a change in the threshold voltage are deteriorated, leading to a decrease in the reliability (for example, page 66 of the LSI Handbook issued by Ohmsha).
Page 67).

The present invention has been made in view of the above circumstances, and an object thereof is to provide a MIS field effect transistor element which suppresses deterioration due to hot carriers and has high reliability. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, since the MIS field-effect transistor of the present invention is formed so that the film thickness of the gate insulating film varies between the gate and the drain, the easiness of forming the inversion layer changes.

[0006]

In the MIS field effect transistor, since the film thickness of the gate insulating film is formed so as to change under the gate, it behaves as if a plurality of transistors having different threshold voltages Vth were formed. Therefore, the threshold voltage Vth ₁ becomes high in the thick film portion, and the region where pinch-off is likely to occur when the gate voltage is applied is divided into a plurality of places, which are conventionally concentrated in one place at the drain end. Generation of hot carriers is reduced.

[0007]

(First Embodiment) A first embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a sectional view showing the structure of a MIS field effect transistor element 1 according to the present invention. FIG. 2 is a sectional view showing an operating state of the MISFET when a predetermined voltage is applied between the source and drain of the MIS field effect transistor element 1. Figure 1
As shown in FIG. 3, in the MIS field effect transistor device 1 of the present invention, the gate insulating film 3 under the gate electrode 2 has a thick (T1) region A1 on the source region 6 side and a thin (T2) region A2 on the drain region 5 side. It is formed by being divided into two regions. Thus, by increasing the film thickness T1 on the source region 6 side with respect to the film thickness T2 on the drain region 5 side,
There is a difference in the electric field strength of the gate, the inversion layer (channel) 7 is easily formed on the drain side (FIG. 2), and it is difficult to form on the source side.

As shown in FIG. 2, when a predetermined voltage is applied between the source and drain and the gate applied voltage is raised,
First, the gate electric field strength under the thin region (A2) of the gate insulating film 3 increases, and an inversion layer (channel) is formed in the A2 region (7a in FIG. 2). When the voltage applied to the gate is further increased, an inversion layer (channel) is also formed under the thick region (A1) of the gate insulating film 3 (7b in FIG. 2). For this reason,
In the MIS field-effect transistor element having the normal structure, the pinch-off occurs only near the drain, whereas the region 8 where the pinch-off easily occurs is divided. When the regions where pinch-off may occur are dispersed at a plurality of locations (two locations) under the gate insulating film 3 in this manner, the voltage gradient in the vicinity of the drain is reduced, the generation of hot carriers is suppressed, and MIS is generated.
Deterioration of the field effect transistor element from the initial characteristics and deterioration of durability are suppressed, and reliability is also improved.

As described above in detail, the MIS field effect transistor 1 according to the first embodiment is formed so that the film thickness T of the gate insulating film 3 changes under the gate (T1, T2). , The thin film portion A2 and the thick film portion A1 have different vertical electric field strengths when a voltage is applied, and it behaves as if a plurality of transistors having different threshold voltages Vth (Vth1, Vth2) are formed. . Therefore, by increasing the film thickness on the source 6 side, this thick film thickness portion A
The threshold voltage Vth1 at 1 becomes high, and it becomes difficult to form a channel at this portion. Therefore, the region where pinch-off is likely to occur is also dispersed at a plurality of locations, so that the generation of hot carriers, which has conventionally been concentrated at one location, is dispersed, and deterioration of initial characteristics is prevented. Further, since the gate insulating film 3 can maintain the film thickness on the source 6 side at the film thickness T1 as in the conventional case, an increase in leak current and an increase in parasitic capacitance of the transistor do not occur.

3 to 5 are vertical cross-sectional views of a semiconductor device for showing an example of manufacturing steps of the MIS field effect transistor shown in FIG. In forming the stepped gate insulating film 3, a thin portion of the gate insulating film 9 is formed on the semiconductor substrate 4 by oxidizing the silicon semiconductor substrate. A mask material 10 such as silicon nitride (Si ₃ N ₄ ) is deposited on this and patterning is performed to obtain a semiconductor element cross-sectional structure shown in FIG. When the silicon substrate is oxidized again, the oxide film in the portion not covered with the mask material becomes thick, and the semiconductor device structure shown in FIG. 4 in which the gate insulating film with steps is formed is obtained. After that, the mask material 10 is removed by etching or the like, and a gate material 12 such as polycrystalline silicon is deposited. The gate material is patterned to form a gate electrode, and impurities in the source / drain portions are introduced to obtain the MIS field effect transistor element structure shown in FIG.

Further, as shown in FIG. 16, the semiconductor substrate 4
The stepwise gate insulating film can also be formed by forming the thin gate insulating film 9 on the upper surface and then depositing the insulating material 11 and performing patterning.

FIGS. 6 and 7 are respectively the first and second MIS field effect transistors according to the first embodiment shown in FIG.
A modification of is shown. Of these, in FIG. 6, the gate insulating film 3 formed in a two-step structure in the embodiment of FIG. 1 is formed into a step-shaped (four steps in the illustrated example) gate insulating film 3a having finer steps. The point that a gate electrode is formed thereon (at least the lower surface of the gate electrode 2a is stepped) is different from the first embodiment. By changing the film thickness of the gate insulating film 3a in multiple stages as in this modification, the deterioration of the initial characteristics of the transistor can be further suppressed as compared with the first embodiment. The steps shown in FIGS. 3 and 4 may be repeated to increase the thickness of the gate insulating film.

FIG. 7 is a sectional view of a semiconductor device according to a second modification of the first embodiment. In the semiconductor device of the second modification, the film thickness of the gate oxide film 3b below the gate electrode 2b is gradually reduced from the source region 6 side toward the drain region 5 side. By continuously changing the film thickness of the gate insulating film 3b as described above, in the first embodiment (FIG. 1) or the first modification (FIG. 6), the region where hot carrier generation is concentrated is substantially reduced. The loss of the initial characteristics of the MIS field-effect transistor can be prevented. In order to form such a gate insulating film, bird's beak at the time of thermal oxidation of the silicon substrate or reflow of a low melting point material may be used.

(Second Embodiment) FIG. 8 is a sectional view of a MIS field effect transistor 13 according to a second embodiment of the present invention. The MIS field-effect transistor 13 shown in the second embodiment uses a self-alignment sidewall forming technique for forming a step in a gate insulating film in order to realize the first embodiment. That is, this MIS
In the field effect transistor 13, the gate electrode 14 is composed of the original gate electrode body 14a and conductive gate sidewall portions 14b provided on both side surfaces thereof, and the lower end surface of the sidewall 14b is the gate electrode body 14a.
The gate insulating film 15 is formed so as to project downward from the lower end surface of the gate insulating film 15. With the MIS field effect transistor 13 having such a structure, the same effect as that of the first embodiment can be expected. MIS like this
Since the field effect transistor does not require a step of changing the gate insulating film thickness under the gate electrode, the MI having a short gate length is used.
It is easy to apply to the S field effect transistor, and is more effective for higher integration and higher speed of the integrated circuit.

9 and 10 show that in the manufacturing process of the MIS field effect transistor 13 shown in the second embodiment, the conductive side wall 14b is formed on the side surface of the main body 14a forming the original gate electrode. FIG. 6 is a step view showing a process up to forming a new gate electrode 14. The gate electrode 14 is formed by the following procedure. First, a thick gate insulating film 16 (corresponding to the film thickness of the thick insulating film on the lower side of the main body 14a) is formed on the semiconductor substrate 4, and a gate material is deposited on the gate insulating film 16 and then patterned to form a gate. The electrode 14a is formed. Further, the gate insulating film 16 is etched using the gate electrode 14a as a mask to obtain the semiconductor element structure shown in FIG. A conductive layer (for example, a polysilicon layer) is deposited on the entire surface of the semiconductor device having the structure shown in FIG. 9, and anisotropic etching is performed on the conductive layer to form conductive sidewalls (14).
b) Get the structure. Since the sidewall 14b thus configured is conductive, it cooperates with the gate electrode 14a to function as a new gate electrode 14. Then, impurities are introduced into the source region / drain region to form the structure shown in FIG.
The MIS field effect transistor device structure shown in FIG.

(Third Embodiment) FIG. 11 shows the gate insulating film 3 of the first embodiment while shortening the gate length to achieve high integration.
5 shows a cross section of the MIS field effect transistor 17 of the third embodiment in which the characteristic (shape) on the source region 6 side, that is, the gate insulating film is thicker than the conventional one. This MIS field effect transistor has a gate insulating film 18 on the source region 6 side.
Since the film thickness is large, a leak current is generated and the parasitic capacitance of the gate electrode is reduced.

The MIS field effect transistor 17 having such a structure is formed by the following procedure. First, a thin insulating film (for example, a silicon thermal oxide film) 19 is formed on the semiconductor substrate 4.
Is formed, and a gate electrode material such as refractory metal or silicide is deposited on this. The gate material is patterned to form the gate electrode 20a. Next, the silicon substrate is thermally oxidized or an insulator is deposited to thicken the insulating film in the portion other than the gate electrode 20a (only the film thickness below the gate electrode body 20a is thinned).
The structure shown in is obtained. Next, as in the case of FIG. 10, conductive sidewalls 20b are formed and impurities are introduced into the source / drain regions.
The MIS field effect transistor 17 shown in 3 is formed.
The MIS field effect transistor 17 thus formed
Shows that the shape of the gate insulating film 18, that is, the lower end surface of the gate electrode 20 is stepwise. In particular, since the thickness of the gate insulating film 18 is thicker on the source region 6 side, the parasitic capacitance of the transistor can be suppressed to a small value, and the leak current due to the tunnel effect can be prevented. In addition, by implanting impurities only in the drain side of the gate electrode in advance until the structure shown in FIG. 12 is obtained, the transistor current does not decrease.

FIG. 14 is a modification of the second embodiment shown in FIG.
FIG. 15 is a modification of the third embodiment shown in FIG. After forming the sidewalls in each fabrication process, the central portion of the gate electrode is patterned and impurities are introduced to form two MISs.
It is used as a field effect transistor. In FIG. 15, the center is the drain, and in FIG. 14, the source. Further, instead of patterning the central portion of the gate electrode, a temporary material is formed in the central portion, the gate electrode body and its sidewall are formed as double sidewalls to the temporary material, and then the temporary material is formed. A similar structure can be achieved by etching away the material.

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Needless to say. Further, when manufacturing the MIS field effect transistor of each of the above-described embodiments, various other processes can be used without being limited to the exemplified manufacturing process.

In the above description, the case where the invention made by the present inventor is mainly applied to the background has been described, but the present invention is not limited thereto, and MI
The S field effect transistor can be generally used.

[0021]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor device of the present invention is
Since the IS field effect transistor is formed such that the film thickness of the gate insulating film changes under the gate, it behaves as if a plurality of MOS transistors having different apparent threshold voltages Vth were formed, and pinch-off occurred. The easy regions are also dispersed in a plurality of locations, and the generation of hot carriers, which has conventionally been concentrated in one location at the drain end, is dispersed and mitigated, and the deterioration of the initial characteristics is suppressed. In addition, since the source film thickness of the gate insulating film can be maintained at the conventional film thickness, there is no occurrence of leak current or increase of the parasitic capacitance of the transistor.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a MIS field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an operating state of the MIS field effect transistor when a predetermined voltage is applied between the source and drain of the MIS field effect transistor of the present invention.

FIG. 3 is a cross-sectional view showing a state in which a mask material 10 is placed on the gate insulating film 9 and patterned in the manufacturing process of the MIS field effect transistor 1 of the first embodiment.

4 is a cross-sectional view showing a state in which a stepwise gate oxide film is formed by subjecting the semiconductor element shown in FIG. 3 to thermal oxidation treatment.

5 is a step view showing a state in which a gate electrode is formed after removing the mask material of the semiconductor element shown in FIG. 4 and impurities are introduced into a source / drain to complete a MIS field effect transistor.

FIG. 6 is a step view showing a first modification example in which a gate oxide film according to the first embodiment of the present invention is formed in four steps.

FIG. 7 is a cross-sectional view showing a second modified example in which the gate insulating film is gradually thinned from the source side toward the drain side.

FIG. 8 is a sectional view of a MIS field effect transistor 13 according to a second embodiment of the present invention.

FIG. 9 is a MIS field effect transistor 1 according to a second embodiment.
3 is a cross-sectional view showing a state in which a thick gate insulating film is formed on a semiconductor substrate and a thin gate insulating film is formed by etching using a gate electrode main body formed on the thick gate insulating film as a mask in the manufacturing process of 3.

10 is a cross-sectional view showing a state in which a sidewall material is deposited on the semiconductor element having the structure shown in FIG. 9 and anisotropic etching is performed to form a conductive sidewall structure.

FIG. 11 is a sectional view of a MIS field effect transistor 17 according to a third embodiment of the present invention.

FIG. 12 is a MIS field effect transistor 1 according to a third embodiment.
7 is a cross-sectional view showing a state in which a thin gate insulating film is formed on a semiconductor substrate and a thick gate insulating film is formed by heat treatment using the gate electrode body formed thereon as a mask in the manufacturing process of 7.

13 is a cross-sectional view showing a state in which conductive sidewalls are formed on the semiconductor element of FIG. 12 to complete a MIS field effect transistor.

FIG. 14 shows two MISs with the gate electrode of FIG. 8 separated.
It is sectional drawing which shows the modification which formed the field effect transistor.

FIG. 15 shows two MIs by separating the gate electrode of FIG.
It is sectional drawing which shows the modification which formed the S field effect transistor.

16 is a cross-sectional view showing a modified example of the method of forming the gate insulating film other than that of FIG. 4 according to the first embodiment.

[Explanation of symbols]

1, 13, 17 MIS field effect transistor 2, 14, 20 Gate electrode 3, 15, 18 Gate insulating film 4 Semiconductor substrate 5 Drain region 6 Source region 7 Inversion layer (channel) 8 Pinch off region 9, 19 Thin gate insulating film 10 Mask material 11, 16, 21 Thick gate insulating film T ₁ Thick gate oxide film T ₂ Thin gate oxide film A 1 Thick region of gate insulating film A 2 Thin region of gate insulating film

Claims (4)

[Claims] 1. A MIS-type field effect transistor, wherein a film thickness of a gate insulating film is formed so as to change between a source and a drain. 2. The MIS type field effect transistor according to claim 1, wherein the gate insulating film is formed so as to be thin at least at a drain end. 3. The MIS field effect transistor according to claim 1, wherein the gate insulating film is formed so that the film thickness is increased at least at the source end. 4. The M according to claim 1, wherein a conductive sidewall is formed on the gate electrode so that the thickness of the gate insulating film varies between the source and the drain.
IS type field effect transistor.