JPH05198776A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a manufacturing period by conducting the step of forming a ROM after an interlayer insulating film is formed. CONSTITUTION:A gate electrode 6, a gate insulating film 5, n-type source, drain regions 7 are formed as constituents of a MOS transistor on a p-type Si substrate 1. Then, an interlayer insulating film 8 is formed by using PSG. The film 8 is etched up to a polycrystalline Si film to be used as a gate electrode 6 by using a mask 3 for forming a ROM, P<+> ions are implanted to inject impurity in a channel region. Then, a mask 11 for forming a contact is formed, and a contact hole 12 is formed. It is heat treated to form a depression region 10. Subsequently, after it is covered with an interconnection layer made of Al-Si, a final protective film 16 is formed. Since the ROM is formed after the interlayer insulating film is formed, a time of the step of forming the film 8 can be shortened as compared with a conventional method so far.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask RO manufactured by using a mask made in accordance with stored contents during a manufacturing process.
The present invention relates to a method of manufacturing an integrated circuit device including M.

[0002]

2. Description of the Related Art An integrated circuit device in which a large number of transistors are integrated on one semiconductor substrate may incorporate a transistor having a ROM function for outputting a specific output signal to an input. As a method of making this ROM transistor, generally, a depletion type MOS transistor is formed in a circuit constituted by an enhancement type MOS transistor. This method is shown in FIGS.

FIG. 2 shows an example of forming an n-channel depletion transistor by performing ion implantation for depletion in advance before forming the gate electrode of the MOS transistor. In this case, there is a method of using a p-type Si substrate or a method of forming a p-well in the Si substrate. In the case of FIG. 2, the p-type Si substrate 1 is used and separated by the element isolation insulating film 2. P ⁺ ions 4 are implanted into the region using the mask 3 for forming the ROM transistor
(Fig. 2 (a)). After the ion implantation, a gate electrode 6 is provided on the gate insulating film 5, and then an n-type source / drain region 7,
After forming the interlayer insulating film 8 (FIG. 2 (b)), a contact hole is opened and the Al electrode 9 is brought into contact with the Al insulating film 8 to form a ROM transistor (FIG. 2 (c)). A depletion region 10 is formed between the source / drain regions 7 by the implanted P ⁺ ions 4.

In the case of FIG. 3, after the gate electrode 6 and the source / drain regions 7 are formed, before the interlayer insulating film is formed, ion implantation is performed using the ROM forming mask 3 (see FIG. 3 ( a)). After that, the interlayer insulating film 8 is formed (see FIG.
(b)), A ROM transistor is completed by opening a contact hole and contacting the Al electrode 9 (Fig. 3).
(c)). This method has an advantage over the method of FIG. 2 in that the ROM formation step is performed before the formation of the interlayer insulating film, and therefore the time from the determination of the ROM code to the product shipment can be shortened.

[0005]

However, in the method of FIG. 3, in the case of an integrated circuit device including a ROM transistor, R
Although the time from when the OM code is determined until the product is shipped is shorter than that in the method shown in FIG.
The gate electrode 6 and the source / drain region 7 of the S-transistor stand by with an extremely thin oxide film 5 having a thickness of about 300 Å formed, which causes moisture absorption and element contamination by impurities in the atmosphere. There was a danger.

An object of the present invention is to solve such problems, to shorten the time from determination of the ROM code to product shipment, and to reduce the risk of element contamination until the ROM code is determined. It is to provide a method for manufacturing a circuit device.

[0007]

In order to achieve the above object, the present invention provides a threshold voltage by implanting impurity ions into a channel forming portion of a specific transistor among MOS transistors formed on a semiconductor substrate. In a method of manufacturing an integrated circuit device having a step of adjusting a voltage, an ion implantation of an impurity for adjusting a threshold value is performed including a gate electrode formed on a substrate surface with a gate insulating film interposed therebetween. It is performed after covering with an interlayer insulating film. that time,
The interlayer insulating film covering the gate electrode is PSG or BPSG
Is more effective, and it is effective to reduce the thickness of the interlayer insulating film where ions are implanted immediately before ion implantation. Further, the threshold voltage is adjusted by ion implantation through the thinned interlayer insulating film.
After providing a contact hole in the insulating film on the semiconductor substrate for connecting to the transistor, the entire surface is covered with a film made of a conductive material and the conductive material film is adhered to the insulating film by heat treatment to flatten the surface, It is effective to form a wiring by patterning the film so that the portion filling the recess remains. Alternatively, it is also effective to form the contact hole, cover the entire surface with a tungsten film, etch back the tungsten film to planarize the surface, and form wiring on the planarized surface. Then, it is effective to form a base film before coating with the conductive material film or the tungsten film.

[0008]

Since the gate electrode and the interlayer insulating film have been formed before the ion implantation step for forming the mask ROM, the time from the determination of the ROM code to the shipping of the product can be further shortened. At the same time, during the waiting period until the ROM code is determined, the interlayer insulating film covers the element, so that there is no risk of element contamination due to moisture absorption or impurities in the atmosphere. However, when it is necessary to thin the interlayer insulating film at the ion implantation site to facilitate the implantation, the wiring is formed by fluidizing the wiring material by heat treatment or flattening by etching back the tungsten film. To solve the problem of wiring step coverage caused by unevenness due to a difference in thickness of an interlayer insulating film.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings in which the same parts as those in FIGS. In the embodiment shown in FIG. 1, a MOS transistor is formed on the p-type Si substrate 1 by using the conventional MOS transistor forming process.
A gate electrode 6 having a thickness of 3000Å, a gate insulating film 5 having a thickness of 200Å, an n-type source / drain region 7 are formed as constituent elements of a transistor, and then an interlayer insulating film 8 having a thickness of 7000Å is formed (Fig. 1 (a)). The interlayer insulating film 8 is generally PSG or BPSG in order to prevent contamination from the outside.
Is used. After that, the process of forming the ROM transistor is started. First, the interlayer insulating film 8 in the region for forming the ROM transistor is etched up to the polycrystalline Si film used as the gate electrode 6 by using the ROM forming mask 3 for selecting the portion for forming the ROM transistor. This is because an interlayer insulating film is usually formed with a thickness of at least 5000 Å or more, so even if ROM ion implantation is performed without etching, it will penetrate through the interlayer insulating film and the polycrystalline Si film,
Since it is difficult to introduce impurities into the channel region of a MOS transistor, an acceleration voltage of about 150 keV is sufficient when ion implantation of P ⁺ is performed without an interlayer insulating film on the gate electrode 3. Impurities can be introduced into the channel region (FIG. 1 (b)). However, the interlayer insulating film 8 may be left to a thickness such that impurities can be introduced. Generally, as a mask for forming a ROM transistor, it is necessary to completely deplete between the source and drain of the transistor. Therefore, considering the alignment accuracy of the mask, it is about 0.3 to 0.5 μm wider than the gate electrode width. It has a large opening. Therefore, as shown in the figure, the etching region of the interlayer insulating film is larger than the width of the gate electrode 6, and the ions are not only directly under the gate but also the source
It is also effectively injected into part of the drain. Subsequently, a contact forming mask 11 is formed (FIG. 1C), and a contact hole 12 is formed by etching. And 900 ~
The interlayer insulation film is reflowed by applying a heat treatment at 950 ° C. to make the shape of the upper portion of the concave portion of the ROM portion and the contact hole portion gentle, and at the same time activate the impurities introduced by the ion implantation of the ROM to form the depletion region 10. Formed (Fig. 1 (d)). Subsequently, by sputtering, Al-Si having a thickness of about 0.8 to 1 μm or
A wiring film 9 made of Al-Si-Cu is deposited, a wiring mask 13 is formed on the wiring film 9 (FIG. 1E), and the wiring film 9 is etched by RIE. Basically, since no Al wiring is left in the memory cell including the ROM, the wiring film 9 in the ROM area is entirely etched, and some Al residue 14 is left on the side wall of the recess.
Remains (Fig. 1 (f)). Finally, the final protective film 16 is formed to complete the integrated circuit (FIG. 1 (g)). As described above, in this embodiment, since the ROM forming process is performed after the interlayer insulating film is formed, at least the interlayer insulating film 8 forming process is performed from when the ROM code is determined to when the product is shipped, as compared with the method of FIG. The time can be shortened, and the interlayer insulating film 8 having a gettering action is already formed on the element even in the waiting period until the ROM code is determined.
It is also possible to avoid the risk of element absorption due to moisture absorption or impurities in the atmosphere.

By the way, when the opening diameter of the ROM portion and the contact hole portion formed by the present invention becomes about 0.8 μm or less due to the reduction of the transistor size,
For wiring by sputtering with aspect ratio approaching 1
The Al thin film 9 is not evenly formed in the recesses as shown in FIG. 1 (e), and in the subsequent Al etching process by RIE,
As described above, the ROM portion is entirely etched except for the residue 14 on the side wall, so that the concave portion having an aspect ratio almost the same as that before the Al formation remains, while the contact hole portion 12
Then, as shown in Fig. 1 (f), the actual aspect ratio rather deteriorates. When the final protective film 16 is formed in such a state, the protective film can no longer be formed to a sufficient thickness in the recesses of the ROM transistor portion and the contact hole portion, and in some cases, as shown in FIG. 1 (g). Void 15 is formed on the surface, which is a serious reliability problem. The concave portion of the ROM portion can be flattened by using a conventional flattening technique in the multi-layer wiring process such as a combination of SOG coating and etch back, but the number of steps is increased and the contact is increased. The problem of the aspect ratio of the hole remains. Therefore, in the present invention, after using the means according to the above embodiment, the recesses formed in these interlayer insulating films are filled,
It is also possible to flatten.

An embodiment of the present invention intended for this embedding will be described with reference to FIG. 4 (a) to 4 (d), the same steps as those of FIGS. 1 (a) to 1 (d) shown in the previous embodiment are performed. In this state, the contact holes and RO
About the thickness of the interlayer insulating film 8 in the M part (about 0.6 to 0.7 μm)
Is formed. Then, the wiring forming process is started. First, a barrier metal film 17 made of Ti, TiN or a laminated metal of these is formed by a sputtering method in a range of 0.1 to 0.2 μm
Formed with a thickness of. After that, an alloy film 9 containing Al is formed to a thickness of about 0.6 to 1.0 μm by a sputtering method (FIG. 4 (e)). At this time, the coverage of the metal film is not as good as in the prior art. Then, this substrate is vacuumed for 500 to 55
Heat treatment at 0 ° C. is performed for about 3 to 5 minutes. Since this heat treatment is performed in an extremely short time, a rapid heating furnace using an infrared lamp as a heat source is used as the heat treatment furnace. By doing so, the alloy film 9 on the surface is fluidized, moves to the recess, and is embedded to make the element surface flat (FIG. 4 (f)). The material of the alloy film 9 at this time is Al-Si, Al-Si-Cu, Al.
-Ge or the like is used. After that, the unnecessary metal film 9 is etched by using the wiring mask 13 formed by patterning (FIG. 4G). Then, as a final step, the surface protection film 16 is formed by, for example, plasma CVD (FIG. 4).
(h)). Also in this case, the coverage of the protective film is good in accordance with the flatness of the base, and the problem of reliability can be avoided.

Another embodiment of the present invention for the purpose of embedding and flattening will be described with reference to FIG. The process up to FIG. 5 (d) is the same as in the previous embodiment. Subsequently, before the wiring forming step, the tungsten film 18 is formed on the entire surface. In this case, the tungsten film is formed by CVD, for example, using WF ₆ as a source gas and SiH ₄ and H ₂ as a reducing gas under the conditions of a substrate temperature of 400 to 500 ° C. and a pressure of several tens Torr. It is possible. In this embodiment, in order to improve the adhesion between the tungsten and the substrate, a barrier metal film 17 made of Ti, TiN or a laminated metal thereof is sputtered to a thickness of about 0.1 μm before forming the tungsten film 18. Is forming. Since the tungsten film 18 formed by the CVD method has excellent step coverage,
It is possible to fill not only the concave portion 19 formed in the portion but also the concave portion 12 of the contact hole portion having a large aspect ratio without voids (FIG. 5 (e)). There is also another method of forming the tungsten film 18 by using WF ₆ and H ₂ gas and selectively forming only on the Si substrate or the polycrystalline Si film. In this case, as described above, the interlayer insulating film in the ROM area is formed. Since the etched portion of 8 is larger than the width of the gate electrode 6 by about 0.5 μm, when the tungsten film 18 is selectively formed, a gap is generated between the tungsten film 18 and the recess 19 of the interlayer insulating film 8 as shown in FIG. In the present invention, it is preferable to form the entire surface of tungsten because it becomes easier. After that, when the tungsten film 18 is entirely etched back to form a structure in which the tungsten film is embedded only in the concave portion, the device surface becomes extremely flat (FIG. 5 (f)). After that, a metal film 9 of Al or the like is formed on the entire surface by sputtering, and the unnecessary metal film 9 is etched using the wiring mask 13 formed by patterning (FIG. 5G). Then, as a final step, the surface protective film 16 is formed by, for example, plasma CVD (FIG. 5 (h)). At this time, since the element surface is sufficiently flattened, the protective film
16 coverage is good and reliability issues are avoided.
The formation of a tungsten film by the CVD method is well known as a means for filling the contact hole 12 having a large aspect ratio. In the present invention, however, the filling of the contact hole 12 and the filling of the recess 19 in the ROM portion are performed at the same time. Therefore, when the ROM formation step is performed after the interlayer insulating film 8 is formed, the element surface can be flattened without increasing the number of steps, thereby improving the reliability of the wiring and the element. it can.

[0013]

According to the present invention, the ROM forming process is performed after the interlayer insulating film is formed. Therefore, the manufacturing period from the determination of the ROM code to the shipment of the product can be shortened, and at the same time, the ROM can be manufactured. Even during the waiting period until the code is determined, the interlayer insulating film having a gettering action is already formed on the device, so that problems such as moisture absorption and device contamination due to impurities in the atmosphere can be solved.

Further, the step of forming the ROM is carried out after the formation of the interlayer insulation, and the recesses formed on the ROM transistor are filled and flattened by utilizing the fluidization by heat treatment of the metal wiring itself or before forming the metal wiring. Since the film formation and the etch back are performed simultaneously, the reliability of the wiring and the element itself can be improved without adding a new flattening step in addition to the above-described effects.

[Brief description of drawings]

FIG. 1 is a sectional view showing a step of forming a ROM transistor portion according to an embodiment of the present invention in the order of (a) to (g).

FIG. 2 is an example of a conventional ROM transistor portion forming process.
Sectional views shown in order of (a) to (c)

3A to 3C are sectional views showing another example of a conventional ROM transistor portion forming step in the order of (a) to (c).

FIG. 4 is a sectional view showing a step of forming a ROM transistor portion according to another embodiment of the present invention in the order of (a) to (h).

FIG. 5 is a sectional view showing a step of forming a ROM transistor of still another embodiment of the present invention in the order of (a) to (h).

FIG. 6 is a cross-sectional view for explaining the advantages of the process of FIG.

[Explanation of symbols]

1 Silicon Substrate 3 ROM Transistor Forming Mask 4 P ⁺ Ion 5 Gate Insulating Film 6 Gate Electrode 7 Source / Drain Region 8 Interlayer Insulating Film 9 Wiring Film 10 Depletion Region 11 Contact Hole Forming Mask 12 Contact Hole 13 Wiring Forming Mask 16 Final protective film 17 Barrier metal film 18 Tungsten film

Claims (6)

[Claims] 1. A method of manufacturing an integrated circuit device comprising a step of adjusting a threshold voltage by implanting impurity ions into a channel forming portion of a specific transistor among MOS transistors formed on a semiconductor substrate. An integrated circuit device characterized in that ion implantation of impurities for adjusting a value is performed after the substrate surface is covered with an interlayer insulating film including a gate electrode formed thereon via a gate insulating film. Manufacturing method. 2. The method of manufacturing an integrated circuit device according to claim 1, wherein the interlayer insulating film covering the gate electrode is made of PSG or BPSG. 3. The method for manufacturing an integrated circuit device according to claim 1, wherein the thickness of the interlayer insulating film at the portion where the ions are implanted is reduced immediately before the ion implantation. 4. A contact hole is formed in an insulating film on a semiconductor substrate for connecting to a MOS transistor whose threshold value is adjusted by ion implantation through a thinned interlayer insulating film, and then the entire surface is made of a conductive material. 4. The integrated circuit according to claim 3, wherein the conductive material film is covered with a film made of, and the conductive material film is brought into close contact with the insulating film by heat treatment, the surface is flattened, and the film is patterned so that a portion filling the recess remains. Method of manufacturing circuit device. 5. A contact hole is formed in an insulating film on a semiconductor substrate for connection to a MOS transistor whose threshold is adjusted by ion implantation through a thinned interlayer insulating film, and then the entire surface is covered with a tungsten film. 4. The method of manufacturing an integrated circuit device according to claim 3, wherein the tungsten film is etched back to planarize the surface and wiring is formed on the planarized surface. 6. The method of manufacturing an integrated circuit device according to claim 4, wherein the base film is formed before the coating of the conductive material film or the tungsten film.