JPH05198199A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device which has a redundant circuit capable of replacing a defect bit of an arbitrary memory block by a redundant word line of other memory block. CONSTITUTION:The addressing system of redundant word lines RWLa and RWLb are independently provided with respect to the addressing system of a word line WL of memory cell array blocks 1a and 1b. The outputs of replacing circuits 10a and 10b which include redundant type selecting circuits 3a and 3b and replace address program circuits 4a and 4b are respectively given to the direct redundant word lines RWLa and RWLb without going through decoders 2a and 2b as redundant word line activation signals RAa and RAb. Moreover, the output of a normal memory cell non-selecting circuit 11 is given to the decoders 2a and 2b as decoder non-activation signal DA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundancy circuit.

[0002]

2. Description of the Related Art Semiconductor memory devices having a redundancy circuit have been developed in order to improve the yield of semiconductor memory devices. When the redundancy circuit is used, when a word line of the semiconductor memory device or a memory cell connected to the word line has a defect, the word line can be replaced with the redundant word line. Thereby, the defective word line or memory cell can be relieved.

FIG. 7 is a diagram showing a structure of a main part of a conventional semiconductor memory device having a redundancy circuit.

The memory array 1 includes a plurality of word lines WL,
A plurality of bit line pairs BL intersecting a plurality of word lines WL,
And a plurality of memory cells MC provided at their intersections
including. Further, the memory array 1 has a redundant word line RWL.
including. The memory cell MC is also connected to the redundant word line RWL.

A decoder 2 and a sense amplifier section 13 are connected to the memory array 1. Sense amplifier 13 includes a plurality of sense amplifiers and a plurality of transfer gates connected to a plurality of bit line pairs BL, and a decoder.

This semiconductor memory device is provided with a replacement circuit 10. The replacement circuit 10 includes a redundancy selection circuit 3,
Includes replacement address program circuit 4 and NAND circuit 5. Replacement circuit 10 and redundant word line RWL form a redundancy circuit.

Next, the operation of the semiconductor memory device of FIG. 7 will be described. The decoder 2 selects one of the plurality of word lines WL in the memory array 1 in response to the X address signal XA,
The potential of the word line WL is raised to "H". As a result, data is read from the memory cell MC connected to the word line WL to the corresponding bit line pair BL. Those data are amplified by the sense amplifier included in the sense amplifier unit 13. The decoder included in the sense amplifier unit 13 turns on one of the plurality of transfer gates in response to the Y address signal YA. As a result, one data is output.

When there is a defect related to a word line WL, the redundant word line RW is used instead of the word line WL.
L is used. In this case, the output of the redundancy selection circuit 3 becomes "H". Further, the replacement address program circuit 4 is programmed with the address of the word line WL to be replaced.

When the address designated by the X address signal XA matches the address programmed in the replacement address program circuit 4 (replacement address), the output of the replacement address program circuit 4 becomes "H". When the outputs of the redundancy selection circuit 3 and the replacement address program circuit 4 become "H", the output of the NAND circuit 5 (decoder deactivation signal DA) becomes "L". As a result, the decoder 2 is deactivated and all the word lines WL are in the non-selected state. Further, the potential of the redundant word line RWL rises to "H".

In this way, the defective word line WL
Or a word line WL connected to a defective memory cell
Is selected, the redundant word line RWL is selected instead of the word line WL.

Although the memory array 1 may include a redundant bit line pair in some cases, the redundant bit line pair is omitted in FIG.

FIG. 8 is a circuit diagram showing a detailed structure of the redundancy selection circuit 3. The redundancy selection circuit 3 includes a fuse 3
1, MOS capacitor 32, high resistance 33, P-channel transistors 34 and 35, and N-channel transistor 3
Including 6.

In the normal state, that is, when the redundant word line RWL is not used (when redundancy is not selected), the fuse 3 is used.
1 is in the connected state. Therefore, the potential of the node N1 is at the ground level, and the NAND circuit 5 of FIG.
A signal of "L" is input to. As a result, the decoder inactivation signal DA becomes "H", and the potential of the redundant word line RWL does not rise.

When the redundant word line RWL is used (when redundancy is selected), the fuse 1 is blown. When the power supply is turned on and the increase in the power supply voltage is moderate, the potential of the node N1 rises toward “H” due to the current flowing through the high resistance 33, and the increase in the power supply voltage is rapid. In this case, the potential of the node N1 rises toward "H" due to capacitive coupling by the MOS capacitor 32.
Further, the positive feedback circuit constituted by the transistors 34, 35 and 36 makes the potential of the node N1 completely "H".
To reach.

In this way, the output of the redundancy selecting circuit 3 becomes "L" when the redundancy is not selected, and the output of the redundancy selecting circuit 3 becomes "H" when the redundancy is selected.

FIG. 9 is a circuit diagram showing a detailed structure of the redundant address program circuit 4. The circuit portion A includes a fuse 41, a MOS capacitor 42, a high resistance 43, P channel transistors 44 and 45, and an N channel transistor 46. The circuit portion B includes a fuse 51, a MOS capacitor 52, a high resistance 53, a P-channel transistor 54,
55 and N-channel transistor 56. The configurations and operations of the circuit parts A and B are similar to those of the redundancy selection circuit 3 of FIG.

Therefore, the potential of the node N3 of the circuit portion A becomes "L" when the fuse 41 is connected, and becomes "H" when the fuse 41 is cut. Similarly, the potential of the node N5 of the circuit portion B becomes "L" when the fuse 51 is in the connected state, and becomes "H" when the fuse 51 is cut.

P-channel transistors 61 and 62 and N-channel transistors 71 and 72 are connected between the input terminal I1 and the output terminal O1. P-channel transistors 63 and 64 and N-channel transistors 73 and 74 are connected between the input terminal I2 and the output terminal O1. P-channel transistors 65 and 66 and N-channel transistors 75 and 7 are provided between the input terminal I3 and the output terminal O1.
6 is connected. P-channel transistors 67 and 68 and N-channel transistors 77 and 78 are connected between the input terminal I4 and the output terminal O1.

The gates of the transistors 61, 73, 65 and 77 are connected to the node N3 of the circuit portion A, and the gates of the transistors 71, 63, 75 and 67 are connected to the node N4 of the circuit portion A. Transistors 62, 64, 76,
The gate of 78 is connected to the node N5 of the circuit portion B, and the gates of the transistors 72, 74, 66 and 68 are connected to the node N6 of the circuit portion B.

Replacement address program circuit 4 shown in FIG.
Is a program circuit for the X address signals X0 and X1. A programming method in this programming circuit will be described.

First, the predecode signals X0.X1, X0
-/ X1, /X0.X1, /X0./X1 are defined as follows.

When X0 = “H” and X1 = “H”, X0 · X1 = “H” X0 = “H” and X1 = “L”, X0 · / X1 = “H” X0 = “L” , X1 = "H", /X0.X1="H "X0 =" L ", X1 =" L ", /X0./X1="H" Predecode signals X0.X1, X0 .. / X1, / X0
Each of X1, /X0./X1 becomes "L" under the conditions other than the above.

Predecode signals X0 and X are applied to input terminal I1.
1 is coupled to the input terminal I2 and the predecode signal X0.
/ X1 is coupled and the predecode signal / is applied to the input terminal I3.
It is assumed that X0.X1 are coupled and the predecode signal /X0./X1 is coupled to the input terminal I4.

When the fuses 41, 51 are connected, only the input terminal I1 is connected to the output terminal O1. As a result, the predecode signals X0 and X1 appear at the output terminal O1. Therefore, the output becomes "H" when X0 = "H" and X1 = "H". At this time, the redundant word line RWL
Is selected, it means that the address X0 = X1 = “H” is programmed in the replacement address program circuit 4 by the fuses 41 and 51.

Similarly, when the fuse 41 is cut and the fuse 51 is connected, the predecode signals X0./X1 appear at the output terminal O1. Therefore, X0
Addresses "=" H "and X1 =" L "are programmed. When the fuse 41 is connected and the fuse 51 is blown, the predecode signals / X0 and X1 appear at the output terminal O1. Therefore, X0 = "L",
The address X1 = "H" is programmed. When the fuses 41 and 51 are cut, the output terminal O
1 shows / X0 // X1. Therefore, X0 =
The address X1 = "L" is programmed.

Since the number of X address signals is usually two or more, a plurality of circuits shown in FIG. 9 are provided and the output of each circuit is shown in FIG.
Is input to the NAND gate 5.

When memory array 1 is divided into a plurality of memory blocks, each memory block is provided with redundant word line RWL. In this case, if there is only one replacement circuit 10 shown in FIG. 7, only one defect can be repaired, even though the redundant word lines RWL are present in the number of memory blocks.

Therefore, when memory array 1 is divided into a plurality of memory blocks, replacement circuit 10 is provided for each memory block. As a result, the word line WL in each memory block is replaced by the redundant word line RWL in the same memory block by the corresponding replacement circuit 10. However, at most two redundant word lines are provided in each memory block.

[0029]

As described above, in the conventional semiconductor memory device having the redundancy circuit, the defective memory cell (defective bit) is at most two redundant word lines and the defective memory cell is in the memory block. The defective bit must be repaired by replacing it with a redundant bit line pair.

As the pattern forming the memory cells becomes finer, one defect often causes a plurality of memory cells to become defective. With at most two redundant word lines and redundant bit line pairs, it is difficult to repair a multi-bit defect that spreads in a plane.

As described above, the conventional semiconductor memory device having the redundancy circuit has a problem that it cannot cope with an increase in multi-bit defects due to the miniaturization of a pattern for forming a transistor.

An object of the present invention is to obtain a semiconductor memory device provided with a redundancy circuit capable of repairing a multi-bit defect which spreads in a plane.

Another object of the present invention is to obtain a semiconductor memory device in which a defective bit can be replaced by an arbitrary redundant select line regardless of the memory cell array block.

A further object of the present invention is to enable effective replacement of defective bits in a large number of memory cell array blocks with a small redundancy circuit.

[0035]

A semiconductor memory device according to the present invention includes a plurality of memory cell array blocks, a plurality of first selecting means, a plurality of redundant selecting lines, a plurality of redundant memory cells, and a plurality of redundancy circuit means. , And inactivating means. Each of the plurality of memory cell array blocks includes a plurality of select lines and a plurality of memory cells connected to the select lines. The plurality of first selection units are provided corresponding to the plurality of memory cell array blocks, and each select one of the plurality of selection lines in the corresponding memory cell array block. The plurality of redundant selection lines are provided corresponding to a plurality of predetermined memory cell array blocks. The plurality of redundant memory cells are connected to the plurality of redundant selection lines.

Each of the plurality of redundancy circuit means corresponds to one or a plurality of redundancy selection lines. Each of the plurality of redundancy circuit means corresponds to a setting means in which it is preset whether or not the corresponding one or a plurality of redundant selection lines should be used.
Alternatively, a program means capable of programming an address of a select line to be replaced with a plurality of redundant select lines, and a second select selecting one or more corresponding redundant select lines in response to outputs of the setting means and the program means. And means.

The deactivating means is responsive to the outputs of the plurality of redundancy circuit means, and when one or a plurality of redundancy selection lines is selected by any of the plurality of redundancy circuit means, the plurality of first deactivating means. Deactivate the selection means of.

Each of the second selecting means is set when the redundant selecting line is set in the setting means and the address designated by the externally applied address signal coincides with the address programmed by the programming means. , A redundant select line activation signal for selecting one or more corresponding redundant select lines.

The deactivating means deactivates the plurality of first selecting means when the redundant selecting line activating signal is generated from any of the plurality of redundancy circuit means. And logic gate means for generating.

A semiconductor memory device according to the second invention comprises a plurality of memory cell array blocks, a plurality of first selecting means,
A plurality of redundant selection lines, a plurality of redundant memory cells, a plurality of redundancy circuit means, a deactivating means, and a third selecting means are provided.

Each of the plurality of memory cell array blocks includes a plurality of select lines and a plurality of memory cells connected to the plurality of select lines. The plurality of first selection units are provided corresponding to the plurality of memory cell array blocks, and each select one of the plurality of selection lines in the corresponding memory cell array block. The plurality of redundant selection lines are provided corresponding to the plurality of memory cell array blocks.
The plurality of redundant memory cells are connected to the plurality of redundant select lines. Each of the plurality of redundancy circuit means corresponds to a plurality of redundancy selection lines.

The number of redundancy circuit means is smaller than the number of memory cell array blocks.

Each of the plurality of redundancy circuit means includes a setting means for presetting whether or not a plurality of corresponding redundant selection lines should be used, and a selection line to be replaced by the corresponding redundant selection line. Programmable means for programming an address, and second selecting means for selecting a plurality of corresponding redundant select lines in response to outputs of the setting means and the programming means.

The deactivating means is responsive to the outputs of the plurality of redundancy circuit means, and when the plurality of redundancy selection lines are selected by any of the plurality of redundancy circuit means, the plurality of first selection circuits. Inactivate the means. The third selection means selects any of the plurality of redundant selection lines selected by each second selection means.

[0045]

In the semiconductor memory device according to the first and second aspects of the invention, the addressing system for the redundant selection line is provided independently of the addressing system for the selection line in the memory cell array block, and the selection of the redundant selection line is This is performed by the second selecting means provided separately from the first selecting means. As a result, the address of the select line in any memory cell array block can be programmed in the programming means of each redundancy circuit means. Therefore, a defective bit in a certain memory cell array block can be replaced by an arbitrary redundant selection line regardless of the memory cell array block.

Therefore, it becomes possible to effectively replace a multi-bit defect that spreads in a plane with the miniaturization of the pattern with an arbitrary plurality of redundant selection lines.

Further, in the semiconductor memory device, the select line in each memory cell array block can be replaced with an arbitrary redundant select line, and when the redundant select line is selected, all the first select lines are provided by the deactivating means. Select lines are simultaneously deactivated. Therefore, it is not necessary to provide the redundancy circuit means and the redundancy selection lines in the same number as the number of memory cell array blocks.

Therefore, even in a semiconductor memory device having a large number of memory cell array blocks, the circuit scale and the chip area can be reduced by reducing the number of redundant circuit means and redundant select lines.

[0049]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 is a block diagram showing a configuration of a semiconductor memory device having a redundancy circuit according to an embodiment of the present invention. This semiconductor device is formed on the chip CH.

This semiconductor memory device includes a plurality of memory blocks. In FIG. 1, two memory blocks BKa and B are provided.
Only Kb is shown. The memory block BKa includes a memory cell array block 1a, a decoder 2a, a sense amplifier section 13a, and a sense amplifier activation circuit 8a. Similarly, the memory block BKb includes a memory cell array block 1b, a decoder 2b, a sense amplifier section 13b, and a sense amplifier activation circuit 8b.

Each memory cell array block 1a, 1b
Includes a plurality of word lines WL, a plurality of bit line pairs BL, and a plurality of memory cells MC provided at their intersections. Each sense amplifier unit 13a, 13b includes a plurality of sense amplifiers and transfer gates connected to a plurality of bit line pairs BL, a decoder and a write driver.

Replacement circuit 10a and redundant word line RWLa are provided corresponding to memory block BKa, and replacement circuit 10b and redundant word line RWLb are provided corresponding to memory block BKb. Redundant word line RWLa,
The memory cell MC is also connected to RWLb.

The replacement circuit 10a includes a redundancy selection circuit 3a,
It includes a replacement address program circuit 4a, a NAND circuit 5a and an inverter 6a. Similarly, the replacement circuit 10b
Includes a redundancy selection circuit 3b, a replacement address program circuit 4b, a NAND circuit 5b and an inverter 6b.

Replacement circuit 10a and redundant word line RWL
a constitutes a redundancy circuit corresponding to memory block BKa, and replacement circuit 10b and redundancy word line RWLb constitute a redundancy circuit corresponding to memory block BKb. The configuration and operation of each redundancy selection circuit 3a, 3b are similar to the configuration and operation of the redundancy selection circuit 3 shown in FIG. The configuration and operation of each replacement address program circuit 4a, 4b are similar to the configuration and operation of replacement address program circuit 4 shown in FIG.

Further, all memory blocks BKa,
A normal memory cell non-selection circuit 11 is provided commonly to BKb. The normal memory cell non-selection circuit 11 is a NAND
It includes a circuit 7 and an inverter 8.

An externally applied X address signal XA is applied to each of the decoders 2a and 2b, and an X address signal XA and an externally applied Z address signal (block address signal) ZA are applied to each of the replacement address program circuits 4a and 4b. Is given to each sense amplifier section 13a, 13
An externally applied Y address signal YA is applied to b. The Z address signal ZA is applied to the block selector 9.

The outputs of the redundancy selecting circuit 3a and the replacement address program circuit 4a are applied to the input terminal of the NAND circuit 5a, and the output signal / RAa of the NAND circuit 5a is 1 of the NAND circuit 7 of the normal memory cell non-selecting circuit 11. One input terminal and the inverter 6a. The output of inverter 6a is applied to redundant word line RWLa and sense amplifier activation circuit 8a as redundant word line activation signal RAa.

Similarly, the outputs of the redundancy selection circuit 3b and the replacement address program circuit 4b are the NAND circuit 5b.
Of the output signal of the NAND circuit 5b
RAb is normally applied to another one input terminal of NAND circuit 7 of memory cell non-selection circuit 11 and inverter 6b. The output of inverter 6b is applied to redundant word line RWLb and sense amplifier activation circuit 8b as redundant word line activation signal RAb.

The replacement address program circuit 4a,
When the output of 4b is 1 or more, the NAND circuits 5a,
Two or more input terminals of 5b are required.

On the other hand, the output of the normal memory cell non-selection circuit 11 is used as a decoder inactivation signal DA for the decoders 2a and 2a.
b and sense amplifier activation circuits 8a and 8b. Sense amplifier activation circuit 8a applies sense amplifier inactivation signal SAa to sense amplifier portion 13a in response to block selection signal BSa, redundant word line activation signal RAa and decoder inactivation signal DA. Similarly, the sense amplifier activation circuit 8b outputs the block selection signal BS
b, the redundant word line activation signal RAb and the decoder deactivation signal DA in response to the sense amplifier deactivation signal S.
Ab is supplied to the sense amplifier unit 13b.

FIG. 2 shows a detailed circuit configuration of the sense amplifier activation circuit 8a. The sense amplifier activation circuit 8a is
It includes CMOS transfer gates 81 and 82 and inverters 83 and 84.

When the redundant word line activation signal RAa is "H", the CMOS transfer gate 81 is turned on and the CMOS transfer gate 82 is turned off. As a result, the decoder inactivation signal DA is output from the node N10.
An inverted signal of is output as a sense amplifier activation signal SAa. When the redundant word line activation signal RAa is "L", the CMOS transfer gate 81 is turned off and C
The MOS transfer gate 82 turns on. As a result, the block selection signal BSa is output from the node N10 as the sense amplifier activation signal SAa.

The structure and operation of sense amplifier activating circuit 8b are similar to those of sense amplifier activating circuit 8a.

Next, the operation of the semiconductor memory device shown in FIG. 1 will be described. When all the redundant word lines RWLa and RWLb are not used (when the redundancy is not selected), the outputs of the redundancy selection circuits 3a and 3b are "L", and the NAND circuits 5a and 5a,
The output of 5b is "H". Therefore, the redundant word line activation signals RAa and RAb are "L", and the decoder deactivation signal DA is "H". As a result, the decoders 2a and 2b are activated. Further, the block selection signals BSa and BSb from the sense amplifier activation circuits 8a and 8b are the sense amplifier activation signals SAa and SA.
It is output as b.

For example, when memory block BKa is designated by Z address signal ZA, block selection signal BS
a becomes "H", and the block selection signal BSb becomes "L". As a result, the sense amplifier unit 13a becomes active and the sense amplifier unit 13b becomes inactive. The decoder 2a selects one of the plurality of word lines WL in the memory cell array block 1a in response to the X address signal XA, and raises its potential to "H". As a result, data is read from the memory cell MC connected to the word line WL to the corresponding bit line pair BL.

In the read operation, those data are amplified by the sense amplifier included in the sense amplifier section 13a. The decoder included in the sense amplifier unit 13 turns on one of the plurality of transfer gates in response to the Y address signal YA. As a result, one data is output. At this time, the redundant word line activation signals RAa, R
Since Ab is "L", redundant word lines RWLa, RW
Lb is not selected.

When either of the redundant word lines RWLa and RWLb is used (when the redundancy is selected), the output of either of the redundancy selecting circuits 3a and 3b becomes "H". For example, it is assumed that redundant word line RWLa is used.
In this case, the output of the redundancy selection circuit 3a becomes "H".

The replacement address program circuit 4a has an address (replacement address) of the word line WL to be replaced.
Is programmed. Replacement address program circuit 4a
Is not limited to the address of the word line WL in the memory block BKa, but is not limited to the word line W in another memory block BKb.
The address of L can also be programmed.

When the address designated by X address signal XA and Z address signal ZA does not match the replacement address programmed in replacement address program circuit 4a, the output of replacement address program circuit 4a becomes "L", Output signal of NAND circuit 5a / RAa
Becomes "H". In this case, the memory cell array block 1a or 1b is operated by the same operation as when the redundancy is not selected.
The word line WL is selected and the data is read.

When the address designated by X address signal XA and Z address signal ZA matches the replacement address programmed in replacement address program circuit 4a, the output of replacement address program circuit 4a becomes "H", The output signal / RAa of the NAND circuit 5a becomes "L". Therefore, the decoder inactivation signal DA
Becomes "L", and the decoders 2a and 2b are inactivated. Therefore, the word line WL in the memory cell array blocks 1a and 1b is not selected.

On the other hand, redundant word line activation signal RAa attains "H" and the potential of redundant word line RWLa rises to "H". As a result, data is read from the memory cell MC connected to the redundant word line RWLa to the corresponding bit line pair BL.

Further, the sense amplifier activating circuit 8a supplies an inverted signal of the decoder inactivating signal DA to the sense amplifier section 13a as a sense amplifier activating signal SAa. As a result, the sense amplifier unit 13a becomes active.

As a result, the data read onto the bit line pair BL is amplified by the sense amplifier included in the sense amplifier section 13a. The decoder included in the sense amplifier unit 13a turns on one of the plurality of transfer gates in response to the Y address signal YA. Therefore, 1
Two data are output.

When the defective bit is replaced by the redundant word line, that is, when the address designated by the X address signal XA and the Z address signal ZA matches the programmed replacement address, the redundant word line is selected by the block selection signal. It is done independently. At that time, all memory cell array blocks are inactive regardless of the selection of redundant word lines. Therefore, defective bits can be replaced with redundant word lines of different memory blocks.

In the above embodiment, the read operation has been described. However, by using the write driver instead of the sense amplifier during the write operation, the redundancy circuit operates exactly as in the read operation.

FIG. 3 shows a partial configuration of the sense amplifier section 13a. Sense amplifier activation signal SAa is applied to one input terminal of NAND circuit G11 and one input terminal of NAND circuit G12. The other input terminal of NAND circuit G11 is supplied with read / write control signal R / W through inverter G15, and the other input terminal of NAND circuit G12 is directly supplied with read / write control signal R / W. Be done. The output signal of inverter G13 is applied to write driver WD as write driver activation signal WA.
The output signal of inverter G14 is applied to sense amplifier SE as sense amplifier activation signal SA.

During the read operation, read / write control signal R /
W becomes "H". If the sense amplifier activation signal SAa is "H", the sense amplifier activation signal SA is "H".
Becomes As a result, the sense amplifier SE is activated. In the write operation, read / write control signal R / W becomes "L". Sense amplifier activation signal SAa is "H"
If so, the write driver activation signal WA becomes "H". As a result, the write driver WD is activated.

FIG. 4 is a block diagram showing a structure of a semiconductor memory device having a redundancy circuit according to another embodiment of the present invention.

This semiconductor memory device includes 64 memory blocks BK1 to BK64 and 32 replacement circuits R1 to R3.
It includes two and one normal memory cell non-selection circuit 11.
32 redundant word lines RWL1 to RWL32 are provided corresponding to the 32 replacement circuits R1 to R32.

Each of memory blocks BK1 to BK64 has the same structure as memory block BK1a shown in FIG. Each of replacement circuits R1-R32 has the same configuration as replacement circuit 10a shown in FIG. The normal memory cell non-selection circuit 11 has the same configuration as the normal memory cell non-selection circuit 11 shown in FIG.

The inverter included in the replacement circuit R1 (see FIG.
Redundant word line activation signal RA1 output from the reference word) is applied to redundant word line RWL1 and memory block BK1. Redundant word line activation signal RA2 output from the inverter (see FIG. 1) included in replacement circuit R2 is applied to redundant word line RWL2 and memory block BK3. Similarly, the redundant word line activation signal R output from the inverter (see FIG. 1) included in the replacement circuit R32.
A32 is applied to redundant word line RWL32 and memory block BK63.

NAND included in replacement circuits R1 to R32
The output signals / RA1 to / RA32 of the circuit (see FIG. 1) are
It is normally applied to the memory cell non-selection circuit 11. The decoder inactivation signal DA output from the normal memory cell non-selection circuit 11 is applied to all the memory blocks BK1 to BK64.

Any of the redundant word lines RWL1 to RWL3
When 2 is not used, all the redundant word line activation signals RA1 to RA32 are "L" and the decoder deactivation signal DA is "H". As a result, the decoders included in all the memory blocks BK1 to BK64 are activated.

When any of the redundant word lines RWL1 to RWL32 is used, the redundant word line activation signal R
Any of A1 to RA32 becomes “H”. For example,
When the redundant word line RWL1 is used, the redundant word line activation signal RA1 becomes "H".

The replacement address program circuit (see FIG. 1) included in each replacement circuit is programmed with the X address and Z address (replacement address) of the word line to be replaced. The address of the word line in any memory block can be programmed in each replacement address programming circuit. For example, the replacement address program circuit in replacement circuit R1 can be programmed with the address of the word line in memory block BK4. In this case, the word line in the memory block BK4 can be replaced with the redundant word line RWL1.

When the word line in memory block BK4 is replaced by redundant word line RWL1, decoder inactivation signal DA attains "L". As a result, the decoders included in all the memory blocks BK1 to BK64 are inactivated.

In this way, the word line in each memory block can be replaced with an arbitrary redundant word line, and
When the redundant word line is selected, the decoder inactivation signal DA inactivates all the memory blocks BK1 to BK64. Therefore, it is not necessary that the number of replacement circuits and the number of redundant word lines correspond to the number of memory blocks.

In a semiconductor memory device having a large number of memory blocks such as 32 to 128, the number of redundant word lines and replacement circuits can be reduced in order to reduce the circuit scale and the chip area.

FIG. 5 is a block diagram showing a structure of a semiconductor memory device having a redundancy circuit according to still another embodiment of the present invention.

This semiconductor memory device includes 64 memory cell array blocks 101 to 164 and 32 replacement circuits R.
1 to R32 and one normal memory cell non-selection circuit 11
including. This semiconductor memory device is formed on a chip CH.

Memory cell array blocks 101-164
X decoders 201 to 264, Y decoder 3 corresponding to
01-364, sense amplifier / write driver 401-
464, redundant decoders 501 to 564, and block selectors 601 to 664 are provided. Redundant word line groups RWG1 to RWG64 are provided corresponding to the memory cell array blocks 101 to 164. Further, a main decoder 700 is provided.

Memory cell array blocks 101-164
Each include 512 word lines, 64 bit line pairs and a plurality of static memory cells provided at their intersections.

Main decoder 700 decodes externally applied X address signal XA, and applies the decoded signal to X decoders 201-264. Block selectors 601 to 664 generate block selection signals BS1 to BS64, respectively, in response to a Z address signal (block address signal) ZA given from the outside. X
Each of the decoders 201 to 264 selects one word line in the corresponding memory cell array block in response to the corresponding block selection signal and the output signal of the main decoder 700. Each of the Y decoders 301 to 364
In response to an externally applied Y address signal YA, eight bit line pairs in the corresponding memory cell array block are selected.

The X address signal XA is the X address signal X0.
To X9. Y address signal YA is Y address signal Y
Including 0 to Y2. Z address signal ZA includes Z address signals Z0 to Z5.

The redundant word line activation signal output from each replacement circuit is applied to two redundant decoders and two block selectors. For example, the redundant word line activation signal RA1 output from the replacement circuit R1 is generated by the redundant decoder 5
01, 502 and block selectors 601, 602. Redundant word line activation signal RA32 output from replacement circuit R32 is applied to redundant decoders 563 and 564 and block selectors 663 and 664.

Redundant word line activation signals RA1 to RA32 output from all replacement circuits R1 to R32 are applied to normal memory cell non-selection circuit 11.

Normal memory cell non-selection circuit 11 includes an OR circuit G20. The decoder deactivation signal DA output from the normal memory cell non-selection circuit 11 is applied to all block selectors 601 to 664. The block selectors 601 to 664 provide the decoder activation signals DA1 to DA64 to the X decoders 201 to 264, respectively.

Next, the operation of the semiconductor memory device of FIG. 5 will be described. When none of the redundant word line groups RWG1 to RWG64 is used (when redundancy is not selected), the redundant word line activation signals RA1 to RA32 are "L".
As a result, the decoder deactivation signal DA output from the normal memory cell non-selection circuit 11 becomes "L". As a result, the block selectors 601 to 664 are activated. At this time, all the redundant decoders 501 to 564 are in the non-selected state. In addition, decoder activation signals DA1 to DA1
All DA64s are activated.

In response to Z address signal ZA, one of block selection signals BS1 to BS64 attains "H" (selected state). For example, when the block selection signal BS1 becomes "H", the X decoder 201 enters the selected state,
Moreover, the sense amplifier / write driver 401 is activated. The X decoder 201 selects one word line in the memory cell array block 101 and sets its potential to “H”.
Start up. As a result, data is read from the 64 memory cells connected to the selected word line to the corresponding bit line pair. The Y decoder 301 selects eight bit line pairs in the memory cell array 101.

In the read operation, the sense amplifier in sense amplifier / write driver 401 is activated. As a result, the data on the selected eight pairs of bit line pairs is amplified by the sense amplifier and output as data D0 to D7 to the outside.

At the time of writing operation, the write driver in the sense amplifier / write driver 401 is activated. As a result, externally applied data D0 to D7 are written to the selected eight bit line pairs. When any of the redundant word lines of the redundant word line groups RWG1 to RWG64 is used (when redundant is selected), one of the redundant word line activation signals RA1 to RA32 becomes "H". For example, assume that one redundant word line in redundant word line group RWG1 is used. In this case, the output signal of the redundancy selection circuit in the replacement circuit R1 becomes "H".

The address of the word line to be replaced (replacement address) is programmed in advance in the replacement address program circuit in replacement circuit R1. The replacement address program circuit in the replacement circuit R1 is not limited to the word line in the memory cell array block 101, but the address of the word line in the other memory cell array blocks 102 to 164 can be programmed.

When the address designated by X address signal XA and Z address signal ZA does not match the replacement address programmed in the replacement address program circuit in replacement circuit R1, redundant word line activation signal R
A1 becomes "L", and the decoder deactivating signal DA also becomes "L". In this case, one of the word lines in one memory cell array is selected by the same operation as when the redundancy is not selected.

When the address designated by X address signal XA and Z address signal ZA matches the replacement address programmed in the replacement address program circuit in replacement circuit R1, redundant word line activation signal RA.
1 becomes "H", and the decoder deactivation signal DA is also "H".
Becomes

When the memory cell array block 101 is selected, the lowest Z address signal Z0 becomes "L". In this case, the block selection signal BS1 becomes "H" and the block selection signals BS2 to BS64 become "L". As a result, the sense amplifier / write driver 401 is activated, and the sense amplifier / write drivers 402 to 464 are activated.
Becomes inactive. The X decoders 202 to 264 are in the non-selected state. At this time, the decoder activation signal DA1 becomes "L". As a result, the X decoder 201 also goes into a non-selected state.

On the other hand, since redundant word line activation signal RA1 is "H", redundant decoders 501 and 502 are activated. When the lowest Z address signal Z0 is "L", redundant decoder 501 is in the selected state and redundant decoder 502 is in the non-selected state. Therefore, in response to the least significant X address signal X0, the redundant word line group RW
One redundant word line in G1 is selected, and its potential becomes "H". As a result, data is read from the 64 memory cells connected to the selected redundant word line to the corresponding bit line pair. The Y decoder 301 is
Eight pairs of bit line pairs in the memory cell array block 101 are selected.

In the read operation, the sense amplifier in sense amplifier / write driver 401 is activated. As a result, the data on the selected eight pairs of bit line pairs is amplified by the sense amplifier and output as data D0 to D7 to the outside.

At the time of write operation, the write driver in the sense amplifier / write driver 401 is activated. As a result, externally applied data D0 to D7 are written to the selected eight bit line pairs.

As described above, the word line in each memory cell array block can be replaced with an arbitrary word line,
In addition, when the redundant word line is selected, all X decoders 201 to 264 are inactivated. Therefore, the number of replacement circuits does not have to correspond to the number of memory cell array blocks.

In the semiconductor memory device having a large number of memory cell array blocks as in this embodiment, the number of replacement circuits can be reduced in order to reduce the circuit scale and the chip area.

FIG. 6 is a circuit diagram showing in detail the structure of a part of the semiconductor memory device of FIG. FIG. 6 mainly shows a portion related to the memory cell array block 101.

Replacement circuit R1 includes a redundancy selection circuit 31, a replacement address program circuit 41, a NAND circuit G21 and an inverter G22. The replacement address program circuit 41 includes an X address and Z except for the least significant bit.
A replacement address consisting of an address is pre-programmed. Further, replacement address program circuit 41 is supplied with X address signal XA and Z address signal ZA excluding the least significant bit.

The block selector 601 includes NAND circuits G31 and G32, inverters G33 to G36, an OR circuit G37 and an AND circuit G38. NAND circuit G
Z address signals / Z0 to / Z5 are applied to 31. Z address signal / Z0 is applied to one input terminal of AND circuit G38.

Redundant word line group RWG1 includes redundant word line R
It includes WL1a and RWL1b. The redundant decoder 501 is
Two AND circuits G43 and G44 are included corresponding to redundant word lines RWL1a and RWL1b. The Z address signal / Z0 is given to one input terminal of the AND circuit G43,
The X address signal / X0 is applied to the other one input terminal, and the redundant word line activation signal RA1 is applied to the remaining one input terminal. Z address signal / Z0 is applied to one input terminal of AND circuit G44, X address signal X0 is applied to the other one input terminal, and redundant word line activation signal RA1 is applied to the other one input terminal. Is given.

The block selection signal BS1 is applied to one input terminal of the AND circuit G39, and the decoder activation signal DA1 is applied to the other input terminal. AND circuit G
Reference numeral 39 constitutes a word line activation signal generation circuit WLA.
The X address signal / X0 is applied to one input terminal of the AND circuit G40. The X address signal X0 is applied to one input terminal of the AND circuit G41. AND circuit G
The output signal of the AND circuit G39 is applied to the other input terminal of the AND circuit 40 and the other input terminal of the AND circuit G41. The AND circuits G40 and G41 form a Z decoder ZD.

A is applied to one input terminal of the AND circuit G42.
The output signal of the ND circuit G40 is given, and the output signal DS of the main decoder 700 is given to the other input terminal. The output signal of AND circuit G42 is applied to word line WL. The AND circuit G42 constitutes a local decoder LD.

FIG. 6 shows only one local decoder LD and one word line WL. The main decoder 700 receives the X address signal XA excluding the least significant bit.
Is given.

When the redundant word line RWL1a is used, the output of the redundancy selection circuit 31 is set to "H". In the replacement address program circuit 41, the X and Z addresses of the word line to be replaced by the redundant word line RWL1a are programmed in advance as replacement addresses. In the example of FIG. 6, the least significant bit of the X address is unprogrammed.

Externally applied X address signal XA
When the address designated by (except for the least significant bit) and the Z address signal ZA matches the replacement address programmed in replacement address program circuit 41, the output of replacement address program circuit 41 becomes "H".
As a result, the redundant word line activation signal RA1 becomes "H" and the decoder deactivation signal DA also becomes "H". Therefore, the output of the inverter G35 becomes "L".

When memory cell array block 101 is selected, Z address signals / Z0 to / Z5 are at "H".
As a result, the output of the AND circuit G38 becomes "H",
The block selection signal BS1 becomes "H" (selected state).
Therefore, the sense amplifier / write driver 401 (see FIG. 5) is activated.

At this time, since the decoder activation signal DA1 becomes "L", the output of the AND circuit G39 becomes "L" and the outputs of the AND circuits G40 and G41 also become "L" (non-selected state). Therefore, the output of the AND circuit G42 also becomes "L", and the word line WL remains in the non-selected state.

On the other hand, since the redundant word line activation signal RA1 is "H", if the X address signal / X0 and the Z address signal / Z0 are "H", the output of the AND circuit G43 becomes "H". .. Therefore, the redundant word line RWL
1a is selected.

Redundant word line groups RWG1 and RWG2 (see FIG. 5)
If none of the word lines in the reference word line) is selected, or if the address designated by the externally applied X address signal XA and Z address signal ZA does not match the replacement address, redundant word line activation signal RA
1 becomes "L".

In this case, AND in the redundancy decoder 501
The outputs of the circuits G43 and G44 are both "L", and the redundant word lines RWL1a and RWL1b are both in the non-selected state. The output of the AND circuit G38 becomes "L", and the decoder activation signal DA1 becomes "H".

All other redundant word line activation signals RA
When 2-RA32 (see FIG. 5) are "L", the decoder deactivating signal DA becomes "L". When the memory cell array block 101 is selected, the Z address signal / Z0
~ / Z5 becomes "H". Thereby, the inverter G3
The output of 5 becomes "H". Therefore, the block selection signal BS1 becomes "H".

As a result, the sense amplifier / write driver 401 (see FIG. 5) is activated. Further, the output of the AND circuit G39 becomes "H". X address signal / X0
Is "H", the output of the AND circuit G40 is "H".
Becomes Signal DS output from main decoder 700
Is "H", the output of the AND circuit G42 is "H", and the word line WL is in the selected state.

Redundant word line activation signals RA2-RA32
If any one of them (see FIG. 5) is "H", the decoder deactivating signal DA also becomes "H". In this case, the output of the inverter G35 becomes "L", and the block selection signal B
S1 becomes "L".

Therefore, the sense amplifier / write driver 401 is inactivated. Also, the AND circuit G39
Output becomes "L". Therefore, the AND circuit G4
The outputs of 0 and G41 also become "L", and the output of the AND circuit G42 also becomes "L". Therefore, the word line WL is in a non-selected state.

In the above embodiment, the present invention is applied to the redundant word line, but by replacing the redundant word line with the redundant bit line pair and replacing the X decoder with the Y decoder,
The present invention can be similarly applied to the redundant bit line pair.

The present invention can be applied not only to the static random access memory but also to the dynamic random access memory and other various semiconductor memory devices.

[0131]

As described above, according to the first and second aspects of the present invention, a defective bit in a certain memory cell array block can be replaced by an arbitrary redundant select line regardless of the memory cell array block. Therefore, it is possible to effectively replace a multi-bit defect that spreads in a plane with the miniaturization of the pattern with an arbitrary plurality of redundant selection lines.

Further, it is not necessary to provide the redundancy circuit means and the redundancy selection lines in the same number as the number of memory cell array blocks. Therefore, even in a semiconductor memory device having a large number of memory cell array blocks, the circuit scale and the chip area can be reduced by reducing the number of redundancy circuit means and redundancy selection means.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device including a redundancy circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a sense amplifier activation circuit.

FIG. 3 is a diagram showing a partial configuration of a sense amplifier unit.

FIG. 4 is a block diagram showing a configuration of a semiconductor memory device having a redundancy circuit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a semiconductor memory device having a redundancy circuit according to still another embodiment of the present invention.

6 is a circuit diagram showing a detailed configuration of a part of the semiconductor memory device of FIG.

FIG. 7 is a diagram showing a configuration of a main part of a semiconductor memory device including a conventional redundancy circuit.

FIG. 8 is a circuit diagram showing a detailed configuration of a redundancy selection circuit.

FIG. 9 is a circuit diagram showing a detailed configuration of a replacement address program circuit.

[Explanation of symbols]

1a, 1b, 101-164 Memory cell array block 2a, 2b Decoder 3a, 3b Redundancy selection circuit 4a, 4b Replacement address program circuit 5a, 5b NAND circuit 6a, 6b Inverter 7 NAND circuit 8 Inverter 9, 601-664 Block selector 10a , 10b, R1 to R32 replacement circuit 11 normal memory cell non-selection circuit 13a, 13b sense amplifier section BKa, BKb, BK1 to BK64 memory block 201 to 264 X decoder 301 to 364 Y decoder 401 to 464 sense amplifier / write driver 501 to 564 redundant decoder 700 main decoder WL word lines RWLa, RWLb, RWL1 to RWL32 redundant word lines RWG1 to RWG64 redundant word line group MC memory cells RA1 to RA32 redundant Lead wires activation signal DA decoder inactivation signal DA1~DA64 decoder activation signal In the drawings, the same reference numerals denote the same or corresponding parts.

Claims (3)

[Claims] 1. A plurality of memory cell array blocks each including a plurality of selection lines and a plurality of memory cells connected to the plurality of selection lines, and a plurality of memory cell array blocks provided corresponding to the plurality of memory cell array blocks, each corresponding to each other. A plurality of first selection means for selecting one of a plurality of selection lines in the memory cell array block, a plurality of redundant selection lines provided corresponding to a plurality of predetermined memory cell array blocks, and the plurality of selection lines. A plurality of redundant memory cells connected to the redundant select line; and a plurality of redundant circuit means each corresponding to one or a plurality of redundant select lines, each of the plurality of redundant circuit means corresponding to one Alternatively, setting means for presetting whether or not a plurality of redundant selection lines should be used, and an address of a selection line to be replaced by a corresponding one or a plurality of redundant selection lines Output of the plurality of redundancy circuit means, including programmable programming means and second selecting means for selecting corresponding one or more redundant selection lines in response to outputs of the setting means and the programming means. In response to any one of the plurality of redundancy circuit means to select one or a plurality of redundancy selection lines, the deactivation means further deactivates the plurality of first selection means. Semiconductor memory device 2. In each of the second selecting means, an address in which a redundant selecting line is set in the setting means and an address designated by an address signal given from the outside is programmed in the programming means. And a redundant selection line activation signal for selecting one or more corresponding redundant selection lines, the inactivating means generating the redundant selection line from any one of the plurality of redundancy circuit means. 2. A logic gate means for generating an inactivating signal for deactivating the plurality of first selecting means when the select line activating signal is generated.
The semiconductor storage device described. 3. A plurality of memory cell array blocks each including a plurality of selection lines and a plurality of memory cells connected to the plurality of selection lines, and a plurality of memory cell array blocks provided corresponding to the plurality of memory cell array blocks. A plurality of first selecting means for selecting one of a plurality of selection lines in the memory cell array block, a plurality of redundant selection lines provided corresponding to the plurality of memory cell array blocks, and a plurality of redundant selection lines. A plurality of redundant memory cells connected to each other and a plurality of redundant circuit means respectively corresponding to a plurality of redundant select lines, wherein the number of the plurality of redundant circuit means is greater than the number of the plurality of memory cell array blocks. Each of the plurality of redundancy circuit means corresponds to a setting means for presetting whether or not a plurality of corresponding redundancy selection lines should be used. Programming means capable of programming the address of a select line to be replaced with a plurality of redundant select lines;
Second selecting means for selecting a plurality of corresponding redundant selecting lines in response to the outputs of the setting means and the programming means, and the plurality of redundancy circuits in response to the outputs of the plurality of redundancy circuit means. A plurality of redundant selection lines are selected by any of the plurality of redundant circuit means, a plurality of deactivating means for deactivating the plurality of first selecting means, and a plurality of selecting means by each of the second selecting means. And a third selecting means for selecting any one of the redundant selection lines.