JPH05198185A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent power waste of many sense-amplifiers by driving the rest of sense-amplifiers after driving one sense-amplifier and having its output confirmed. CONSTITUTION:When an address buffer 1 fetches a new address and outputs it, an ATD signal generating circuit 2 generates ATD signals. Then, a memory cell circuit 3 receives these ATD signals and reads data from the plural memory cells corresponding to the addresses and transmits them to plural pair bit lines B0 to Bn. Moreover, a first sense-amplifier 40 also starts its operations simultaneously and amplifies the data read on the bit line B0. An output confirmation detecting circuit 6 receives the ATD signals and monitors the output of the amplifier 40. When the amplifier confirms the output data slightly later, the circuit 6 detects this, sends the ATD signals to the rest of sense-amplifiers 41 to 4n, the amplifiers 41 to 4n initiate their operations, confirm H level or L level and output them. Thus, unnecessary power consumption is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a plurality of sense amplifiers are driven when reading data.

[0002]

2. Description of the Related Art A semiconductor memory device employs an internal synchronization system for speeding up and power consumption reduction. The internal synchronization method is a method in which a change in an input from the outside is detected to generate a pulse-shaped synchronization signal called an ATD signal, and the ATD signal causes an internal circuit to operate in synchronization.

FIG. 2 shows a conventional read circuit in a semiconductor memory device having a multi-bit structure by the internal synchronization method.

This read circuit is composed of the address buffer 1
Takes in a new address, the ATD signal generation circuit 2
Generate an ATD signal. Then, the memory cell circuit 3 receives this ATD signal, decodes the address sent from the address buffer 1, and reads the data from the selected memory cells to a plurality of pairs of bit lines B and B. And a plurality of sense amplifiers 4
_{The 0} to 4 _n also start driving at the same time upon receiving this ATD signal, amplify the data read on the bit lines B and B bar of each pair, determine the H level or the L level, and output the output circuit 5.
Respectively output to ₀ to 5 _n.

[0005] Thus, the plurality of sense amplifiers 4 ₀ ~4 _n
Is an APD that starts driving after this ATD signal is issued and delays this ATD signal after a certain period of time.
When a signal is sent, it will stop driving, so
The power was supplied only during this period, and the wasteful power was not consumed as much as possible.

[0006]

[SUMMARY OF THE INVENTION However, data stored in each memory cell in the memory cell circuit 3 is a small signal, the bit line B, since B bar not immediately charged, the sense amplifiers 4 ₀ - It takes some time for 4 _n to detect the potential difference between the bit lines B and B and to be able to perform amplification.

[0007] Therefore, the bit line B from ATD signal is issued, until the potential difference between B bar is large enough, the sense amplifier 4 ₀ to 4 _n is driven by consuming power wastefully to become, in the conventional semiconductor memory device having a plurality of sense amplifiers 4 ₀ to 4 _n by a multi-bit configuration, a waste of the power consumption has occurred a problem that particularly large.

[0008] It should be noted that the above-mentioned problem, the sense amplifier 4 ₀ ~4 _n
Can be eliminated by delaying the driving of the above for a predetermined time after the ATD signal is issued. However, the optimum delay time for delaying the driving timing as described above varies depending on the device, and it is not easy to set this delay time precisely. Therefore, _if the driving of the sense amplifiers 4 ₀ to 4 _n is uniformly delayed, the effect of preventing waste of power consumption cannot be expected if the delay time is too short, and if the delay time is too long, the access time is too long. There is a new problem that is slow.

In view of the above situation, the present invention wastes a large number of sense amplifiers by first driving one sense amplifier and then driving the remaining sense amplifiers after the output is confirmed. An object of the present invention is to provide a semiconductor memory device that can prevent power consumption.

[0010]

SUMMARY OF THE INVENTION A semiconductor memory device of the present invention is a semiconductor memory device in which a plurality of sense amplifiers are driven at the time of reading data to read data of a plurality of memory cells at the same time. The first sense amplifier driving means for driving the sense amplifier, the output confirmation detecting means for detecting that the output of the one sense amplifier is confirmed, and the output confirmation detecting means for detecting the confirmation of the output, Second sense amplifier driving means for driving all the remaining sense amplifiers are provided, thereby achieving the above object.

[0011]

With the above structure, when reading data, only one sense amplifier is driven by the first sense amplifier driving means. However, since the bit line from which data is read from the memory cell does not have a sufficient potential difference immediately, it takes a while before the sense amplifier amplifies and determines it.

Then, when the potential difference of the bit lines becomes sufficient a little later and the output of this sense amplifier is confirmed, the output confirmation detecting means detects this, and all the remaining sense amplifiers are detected by the second sense amplifier driving means. Driven.

As a result, all the sense amplifiers except one are not driven until the bit lines have a potential difference enough to determine the output, so that power is wasted in the meantime. There is nothing to do. In addition, since one sense amplifier is driven and it is confirmed that the bit lines actually have a sufficient potential difference, the remaining sense amplifiers are driven, so the drive of the sense amplifiers is uniformly delayed for a predetermined time. There is no fear that the access time will be delayed as in the case of making it possible.

[0014]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows an embodiment of the present invention and is a block diagram of a read circuit of a semiconductor memory device. The components having the same functions as those of the conventional example shown in FIG. 2 are designated by the same reference numerals.

An address signal designating read data is taken into the address buffer 1. The address buffer 1 is a buffer that fetches an address signal according to a change in an external signal and temporarily stores the address signal. Address buffer 1
The address signal output by is sent to the ATD signal generation circuit 2 and the memory cell circuit 3.

The ATD signal generation circuit 2 is a circuit which detects a change in the address signal output from the address buffer 1 and outputs an ATD signal which is a pulse-shaped synchronizing signal. The ATD signal output by the ATD signal generation circuit 2 is
It is sent to the memory cell circuit 3, the first sense amplifier 40, and the output confirmation detection circuit 6.

The memory cell circuit 3 comprises a memory cell array and an address decoder. When the ATD signal from the ATD signal generation circuit 2 is input, the memory cell circuit 3 decodes the address sent from the address buffer 1 and selects it. It is a circuit for simultaneously reading data from a plurality of memory cells to a plurality of pairs of bit lines B and B bar. In each pair of two bit lines B and B in the memory cell circuit 3, the potential connected to the selected memory cell slightly changes according to the stored data, and the other outputs the reference potential. Then, the bit line B of these pairs, B bar is connected to the input of each sense amplifier 4 ₀ to 4 _n for each pair.

The sense amplifier 4 ₀ to 4 _n is driven by the input of the ATD signal, then amplifies the data read from the memory cell by the bit line B, the potential difference between B bar of each pair H
It is a circuit that determines and outputs the level or the L level. The data determined and output by the sense amplifiers 4 ₀ to 4 _n are sent to the output circuits 5 _{0 to} 5 _n , respectively. Also, the first
The output of the sense amplifier 4 _0, the output establishment detection circuit 6
Also sent to.

The output establishment detection circuit 6 is driven by ATD signal from the ATD signal generating circuit 2 monitors the output of the first sense amplifier 4 _0, the data is determined to H level or L level is inputted Is a circuit for outputting the ATD signal. The ATD signal output from the output confirmation detection circuit 6 is sent to the remaining sense amplifiers 4 ₁ to 4 _n .

The operation of the read circuit having the above configuration will be described.

When the address buffer 1 fetches a new address and outputs it, the ATD signal generation circuit 2 outputs A
Generate a TD signal. Then, the memory cell circuit 3 is
In response to the TD signal, the data is read from the plurality of memory cells corresponding to the address sent from the address buffer 1 to the plurality of pairs of bit lines B and B, respectively.

[0023] In addition, the first sense amplifier 4 ₀ also, the A
Upon receiving the TD signal, driving is started at the same time, and the bit lines B ₀ ,
Amplify the data read on the B ₀ bar. However,
Since the data stored in each memory cell of the memory cell circuit 3 is a minute signal, and the bit lines B ₀ and B ₀ are not immediately charged, the sense amplifier 4 ₀ causes the bit line B ₀ ,
It takes a certain amount of time to detect the potential difference between B ₀ bars and enable amplification. Thus, the sense amplifier 4 ₀ to ATD signal generating circuit 2 is a memory cell circuit 3 is slightly delayed after performing the read operation of data emits an ATD signal, determining to output the H-level or L-level of the data become.

The output establishment detection circuit 6 receives the ATD signal from the ATD signal generating circuit 2 monitors the output of the sense amplifier 4 _0. When the sense amplifier 4 ₀ is determined the output data bit late, output establishment detection circuit 6 detects this, the remaining sense amplifiers 4 ₁ to the ATD signal
Send to 4 _n . Then, these sense amplifiers 4 ₁ to 4 _n is the start of the drive, already bit lines B having a sufficient potential difference, immediately amplifies the data on the B bar, H-level or L
Confirm the level and output.

As described above, each of the sense amplifiers 4 ₀ to 4 _n
The data determined and output in step 5 is sent to the output circuits 5 _{0 to} 5 _n , and is further output from here.

As a result, the semiconductor memory device of this embodiment is
Bit line B by driving the first sense amplifier 4 _0, the potential difference between B bar will detect when large enough, the remaining number of sense amplifiers 4 ₁ to 4 _n on the basis of this
It means to drive the bit line B, between B bar a potential difference is insufficient, together with these sense amplifiers 4 ₁ to 4 _n is prevented from consuming power wastefully, unnecessarily sense amplifier 4 There is no fear that the drive time of ₀ to 4 _n will be delayed and the access time will be delayed.

[0027]

As is apparent from the above description, according to the semiconductor memory device of the present invention, the sense amplifier consumes power wastefully until the bit line has a sufficient potential difference to determine the output. It is possible to prevent this, and since the sense amplifier is driven immediately when the potential difference between the bit lines becomes sufficient, there is no fear that the access time will be delayed.

[Brief description of drawings]

FIG. 1 is a block diagram of a read circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a read circuit in a conventional semiconductor memory device.

[Explanation of symbols]

 2 ATD signal generation circuit 3 Memory cell circuit 4 Sense amplifier 6 Output confirmation detection circuit

Claims (1)

[Claims] 1. A semiconductor memory device in which a plurality of sense amplifiers are driven at the time of reading data to read data of a plurality of memory cells simultaneously, and a first sense amplifier driving means for driving one sense amplifier at the time of reading data. An output confirmation detecting means for detecting that the output of the one sense amplifier is confirmed, and a second sense amplifier for driving all remaining sense amplifiers when the output confirmation detecting means detects the confirmation of the output. A semiconductor memory device comprising a driving means.