JP4704691B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device that requires a refresh operation.

  Each memory cell constituting the dynamic RAM of the semiconductor memory device includes a capacitor that holds information depending on the presence or absence of electric charge, and an address selection MOSFET connected to the capacitor. In such a memory cell, for example, information is held by setting a state in which the capacitor is charged as data “1” and conversely setting the discharged state as data “0”.

  However, in the capacitor, the charged electric charge decreases with leakage current or the like with the elapsed time after charging. For this reason, the conventional semiconductor memory device performs a so-called refresh operation in which information stored in a memory cell is read and amplified at a predetermined cycle, and is written and updated again in the same memory cell.

  FIG. 4 is a block diagram showing a configuration of a portion related to a refresh operation of a conventional semiconductor memory device.

  As shown in FIG. 4, the semiconductor memory device includes a memory array 1 in which a plurality of memory cells are arranged. The semiconductor memory device also includes a sense amplifier 5 that amplifies data read from each memory cell of the memory array 1, a column decoder 6 that outputs a selection signal for the column address of the memory array 1 to the sense amplifier 5, and an external device. And a column address buffer 7 for buffering the column address signal and outputting it to the column decoder 6.

  The semiconductor memory device also includes a row decoder 2 that outputs a row address selection signal to the memory array 1 and a row address buffer 4 that buffers a row address signal from the outside and outputs the row address signal to the row decoder 2. Between the row decoder 2 and the row address buffer 4, the row address signal from the row address buffer 4 and the address signal for self-refresh operation generated by the refresh address generation circuit 10 are selected and output to the row decoder 2. The multiplexer 3 is provided. The refresh address generation circuit 10 includes a refresh controller 11 that controls refresh timing, a refresh timer 12 that generates a clock signal at a predetermined period in response to a control signal from the refresh controller 11, and an address signal for self-refresh operation by counting the clock signal. And an address counter 13 that outputs to the multiplexer 3.

  Such a conventional semiconductor memory device usually includes an external refresh method by external address input and a self-refresh method performed by a built-in circuit at a predetermined cycle.

  In the self-refresh method, the refresh timer 12 generates a clock signal at a cycle set by the refresh controller 11, the address counter 13 counts this clock signal, and the address signal (self-refresh operation) of the memory cell that performs self-refresh. Address signal). The address signal for self-refresh operation is input to the row decoder 2 through the multiplexer 3, and the row decoder 2 selects to select a column including the corresponding memory cell of the memory array 1 based on the input address signal for self-refresh operation. Generate a signal. Data of each memory cell in the selected column is read and output to the sense amplifier 5. The sense amplifier 5 detects and amplifies data of the corresponding memory cell in accordance with a selection signal from the column decoder 6 and writes it again into the memory cell.

  In the conventional self-refresh method of the semiconductor memory device, the refresh operation is performed at the same cycle for all the memory cells in the memory array. In this case, in order to reliably store data in all the memory cells, the period corresponding to the memory cell with the shortest information storage holding time is set by assuming a worst case due to a process failure or the like. For this reason, in memory cells having no problem, the number of data refresh operations is increased more than necessary, and the power consumption increases. In particular, when reading / writing is not performed on the memory (non-operating state), most of the power consumption is due to this refresh operation, and this effect cannot be ignored when power saving is performed.

As a semiconductor memory device that solves such a problem, a device that measures information storage holding time of each memory cell in advance, identifies a memory cell having a short information storage holding time, and shortens a refresh time only for this memory cell. Has been proposed (see, for example, Patent Document 1).
JP-A-61-217988

  However, in the semiconductor memory device disclosed in Patent Document 1, only when a memory cell having a short information storage holding time is specified and a refresh operation is performed on the specified memory cell, other memory cells (normal memory cells) ) Must be generated, and the cycle of the clock signal for performing self-refresh must be changed. This complicates the control of the refresh operation.

  The information storage retention time is measured in a standby state (non-operation state) and an operation state until information is written to and read from the memory cell. Generally, the information storage retention time in the operation state is more in the non-operation state. It is shorter than the information storage retention time. This is because in the operating state, the influence of mutual interference between the word lines, bit lines, and memory cells of the memory array is strong, so that the leakage current flowing through the memory cells increases and the charge charged in the capacitors decreases quickly. It is. Therefore, in the conventional semiconductor memory device shown in FIG. 4 and the semiconductor memory device shown in Patent Document 1, the refresh operation cycle is determined according to the memory cell having the shortest information storage holding time in the operating state. In the operating state, the refresh operation is performed more than necessary, and the power consumption increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a simple structure in which information of a memory cell is reliably stored in both an operating state and a non-operating state, and power saving is achieved.

In a semiconductor memory device that performs a self-refresh operation of cells constituting a memory array in response to a refresh timing signal, refresh signal generating means for generating a refresh signal having a predetermined cycle and reading having a cycle shorter than the refresh signal for the memory array An operation detection means for detecting a write control signal having a cycle shorter than that of the control signal or the refresh signal, an output signal of the operation detection means based on the cycle of the read control signal and the write control signal, and the refresh signal, and a predetermined cycle of the refresh signal Timing signal generation means for outputting a refresh timing signal by synthesizing so as to have the following cycle, and a memory for performing a self-refresh operation in accordance with the refresh timing signal output from the timing signal generation means Comprising an address counter for generating address data of the ray cells, the timing signal generating means is characterized by a logical sum circuit.

  In this configuration, when each cell of the memory array is not operating, the refresh operation of each cell of the memory array is performed based on the cycle of the refresh signal generated by the refresh signal generating means, and each cell of the memory array is In the operating state, the refresh operation of each cell of the memory array is performed based on the cycle of the refresh timing signal which is a combined signal of the refresh signal and the output signal of the operation detecting means. At this time, in the semiconductor memory device, normally, the refresh timing and the read or write timing are controlled so as not to be synchronized, so the cycle of the refresh timing signal is shorter than the cycle of the refresh signal.

  In the semiconductor memory device of the present invention, the refresh signal generating means is shorter than the minimum information storage holding time in the non-operating state of all the cells constituting the memory array, and the cycle of the read control signal or the write control signal A refresh signal with a longer period is generated.

  In this configuration, when each cell of the memory array is in a non-operating state, that is, in a standby state, the refresh operation is performed in the longest cycle in which all cells can continue to store information in this state. On the other hand, when each memory cell is in an operating state, the refresh operation is performed in the cycle of the refresh timing signal obtained from the signal for controlling the refresh operation in the non-operating state, the read control signal, and the write control signal. Is called. At this time, the cycle of the read control signal and the write control signal is shorter than the cycle of the refresh signal, and in order to synthesize them, the refresh timing signal is shorter than the cycle of the refresh signal. That is, in the operating state, the refresh operation is performed with a shorter repetition timing than in the non-operating state.

  In this configuration, since the timing signal generation means is an OR circuit, if the refresh signal from the refresh signal generation means and the output signal from the operation detection means are simply input, the refresh timing signal that is a composite signal of these signals is input. Is output.

  In the semiconductor memory device of the present invention, the operation detecting means includes a first AND circuit that outputs a detection signal when a read control signal and a selection signal for selecting a read target cell of the memory array are input, and a write A second AND circuit that outputs a detection signal when a control signal and a selection signal for selecting a write target cell of the memory array are input; and a detection signal from the first and second AND circuits , And a logical sum circuit that outputs these combined signals.

  In this configuration, when the read control signal, the write control signal, and the selection signal are simply input, the timing signal generating means (logical sum circuit) has a circuit configuration including only two logical product circuits and one logical sum circuit. The signal given to is output.

  According to the present invention, when the memory cell is not operating, the refresh operation is performed according to the non-operating cycle which is longer than the operating time, and when the memory cell is operating, the non-operating cycle is used as a reference. Further, the refresh operation is performed in a cycle shorter than that in the non-operation according to the read / write cycle of the information in the memory cell. As a result, the refresh operation is not performed at a cycle shorter than necessary when the memory cell is not operating, and the refresh operation is performed at a cycle where the stored information can be reliably updated when the memory cell is operating. As a result, a refresh operation is not performed more than necessary, and a power-saving semiconductor memory device can be configured.

  Further, according to the present invention, since the cycle of the read control signal and the write control signal is shorter than the cycle of the refresh signal that gives the refresh timing when the memory cell is not operating, the read timing and the write timing are set when the memory cell is operating. Since the refresh operation is frequently performed based on the information, the information of the memory cell can be surely updated.

  In addition, according to the present invention, the circuit for generating the refresh timing signal is composed of only an OR circuit, so that complicated control is not required and the refresh operation according to the operation state of the memory cell can be easily and simply performed. It can be realized with a configuration.

  In addition, according to the present invention, since the operation of the memory array is detected by only two logical product circuits and one logical sum circuit, further complicated control is not required, and refresh according to the operation state of the memory cell is performed. The operation can be realized easily and with a simple configuration.

A semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing a configuration of a portion related to the refresh operation of the semiconductor memory device according to the present embodiment.
In the semiconductor memory device of this embodiment, a plurality of memory cells each including a capacitor that holds information in a charge state and a semiconductor element such as a MOSFET that is connected to the capacitor and operates according to an address selection signal are arranged. A memory array 1 is provided. These memory cells are arranged at the intersections of a plurality of word lines wired in the row direction of the memory array 1 and a plurality of bit lines wired in the column direction. The semiconductor memory device detects a corresponding memory cell in the memory array 1 and amplifies read data, a column decoder 6 that outputs a selection signal of a column address of the memory array 1 to the sense amplifier 5, And a column address buffer 7 for buffering a column address signal from the outside and outputting it to the column decoder 6.

  The semiconductor memory device also includes a row decoder 2 that outputs a row address selection signal to the memory array 1 and a row address buffer 4 that buffers a row address signal from the outside and outputs the row address signal to the row decoder 2. A row address signal from the row address buffer 4 and a self-refresh operation address signal generated by the refresh address generation circuit 10 are selected between the row decoder 2 and the row address buffer 4 to select the row decoder 4. Is provided.

  The refresh address generation circuit 10 includes a refresh controller 11 that controls self-refresh timing, and a refresh timer 12 that generates a clock signal at a predetermined period by a control signal from the refresh controller 11. The refresh address generation circuit 10 detects whether or not the memory array 1 is being accessed based on the read control signal (OE), the chip select signal (CS), and the write control signal (WE). An operation detection circuit 18 that generates an operation detection signal is provided. Then, the refresh address generation circuit 10 receives the clock signal output from the refresh timer 12 and the operation detection signal output from the operation detection circuit 18, and outputs these combined signals as a refresh timing signal. 14 and an address counter 13 that generates a self-refresh operation address signal that gives a row address of a cell that performs a refresh operation based on the refresh timing signal from the OR circuit 14. The operation detection circuit 18 outputs a read operation detection signal based on the read control signal (OE) and the chip select signal (CS), a write control signal (WE), and a chip select signal (CS). And an AND circuit 15 that outputs the operation detection signal by combining the output signals of the AND circuits 16 and 17. Here, the refresh controller 11 and the refresh timer 12 correspond to “refresh signal generation means” of the present invention, and the OR circuit 14 corresponds to “timing signal generation means” of the present invention. The AND circuit 16 corresponds to the “first AND circuit” of the present invention, and the AND circuit 17 corresponds to the “second AND circuit” of the present invention. The AND circuit 15 corresponds to the “OR circuit of the operation signal detection means” of the present invention.

  The semiconductor memory device also includes a read controller 21 that generates a read control signal for controlling a read operation of each part of the semiconductor memory device based on a read control signal (OE) and a chip select signal (CS), and a write control signal (WE). ) And a chip select signal (CS) and a write controller 22 for generating a write control signal for controlling the write operation of each part of the semiconductor memory device.

In such a semiconductor memory device, data is written as follows.
When a data write control signal (WE) is output from a microprocessor (not shown), the write controller 22 generates a write control signal based on the chip select signal (CS), and each unit involved in the write operation in the apparatus. Output to. At the same time, a row address signal and a column address signal are input from the microprocessor to the row address buffer 4 and the column address buffer 7 via the data bus. The row address buffer 4 buffers the input row address signal and outputs it to the row decoder 2 via the multiplexer 3. The row decoder 2 outputs a word line selection signal for selecting a corresponding word line to the memory array 1 based on the input row address signal. On the other hand, the column address buffer 7 buffers the input column address signal and outputs it to the column decoder 6. The column decoder 6 outputs a bit line selection signal for selecting a corresponding bit line to the sense amplifier 5 based on the input column address signal. The sense amplifier 5 detects a memory cell disposed at the intersection of the selected word line and the bit line based on the input bit line selection signal and the word line selection signal applied to the memory array 1. The sense amplifier 5 writes the data input from the data input / output unit 8 in the detected memory cell in accordance with the write control signal output from the write controller.

On the other hand, data is read as follows.
When a data read control signal (OE) is output from a microprocessor (not shown), the read controller 21 generates a read control signal based on the chip select signal (CS), and each part involved in the write operation in the apparatus. Output to. At the same time, a row address signal and a column address signal are input from the microprocessor to the row address buffer 4 and the column address buffer 7 via the data bus. The row address buffer 4 buffers the input row address signal and outputs it to the row decoder 2 via the multiplexer 3. The row decoder 2 outputs a word line selection signal for selecting a corresponding word line to the memory array 1 based on the input row address signal. On the other hand, the column address buffer 7 buffers the input column address signal and outputs it to the column decoder 6. The column decoder 6 outputs a bit line selection signal for selecting a corresponding bit line to the sense amplifier 5 based on the input column address signal. The sense amplifier 5 detects a memory cell disposed at the intersection of the selected word line and the bit line based on the input bit line selection signal and the word line selection signal applied to the memory array 1. The sense amplifier 5 reads and amplifies the data written in the corresponding memory cell in accordance with the read control signal output from the read controller 21, and outputs the amplified data to the data input / output unit 8.

  In such a semiconductor memory device, a refresh operation is performed in order to hold data that volatilizes with time in each memory cell as described above. As described above, the refresh operation includes a refresh operation by an external input and a self-refresh operation that generates timing in an internal circuit. In the refresh operation by an external input, when the control of the refresh operation is input from the outside, the read operation is performed according to the input refresh address, the data read by the sense amplifier 5 is amplified, and the corresponding memory cell This is realized by rewriting to.

Next, the self-refresh operation of the semiconductor memory device of this embodiment will be described with reference to FIGS.
FIG. 2 is a timing chart showing a signal of a self-refresh operation when the semiconductor memory device is operating, and FIG. 3 is a timing chart showing a signal of a self-refresh operation when the semiconductor memory device is not operating.
(1) When the semiconductor memory device is in an operating state (corresponding to FIG. 2)
When the self-refresh operation is set, the refresh controller 11 outputs a control signal for generating a clock signal at a preset cycle T _s to the refresh timer 12. In response to this control signal, the refresh timer 12 outputs a clock signal (a signal shown in FIG. 2A) whose pulses are repeated at a cycle T _s . The period T _{s of the} clock signal is obtained by measuring the information storage holding time in the non-operating state for all the memory cells constituting the memory array at the final stage of manufacturing the semiconductor memory device. It is set by subtracting a predetermined margin time. This clock signal corresponds to the “refresh signal” of the present invention.

On the other hand, when the semiconductor memory device is operating, a chip select signal (CS) and a read control signal (OE) or a write control signal (WE) are output from the microprocessor, and the AND circuit 16 of the operation detection circuit 18 When the read control signal (OE) and the chip select signal (CS) are detected, a read operation detection signal is output. When the AND circuit 17 detects the write control signal (WE) and the chip select signal (CS), the write operation is detected. Output a signal. These read control signal and write control signal are input to an OR circuit 15, and the OR circuit 15 performs an OR operation on these signals, and an operation detection signal (signal shown in FIG. 2B) that is a composite signal. Is output. Here, the operation detection signal is controlled so that each pulse does not coincide with the pulse of the clock signal. As this control, a process of delaying each detection signal based on the read control signal, the write control signal, and the chip select signal for a predetermined time is used. The cycle T _MR of the read control signal is significantly shorter than the cycle T _{s of} the clock signal. For example, the cycle T _{s of the} clock signal is 2 μsec. The read control signal period T _MR is 60 nsec. ~ 200 nsec. Is set to about. On the other hand, the cycle T _MW of the write control signal is shorter than the cycle T _{s of} the clock signal. For example, the cycle T _{s of the} clock signal is 2 μsec. The period T _MW of the write control signal is 200 nsec. -1.0 μsec. Is set to about. The period of these control signals is not limited to these examples.

  The logical sum circuit 14 performs a logical sum operation on the clock signal input from the refresh timer 12 and the operation detection signal input from the operation detection circuit 18 to generate a refresh timing signal (signal shown in FIG. 2C) as a composite signal. ) Is output.

  The address counter 13 performs a counting process based on the input refresh timing signal, generates a self-refresh operation address signal (signal shown in FIG. 2D), and outputs it to the multiplexer 3. In FIG. 2D, the address signal for self-refresh operation is represented by a pulse having a predetermined width, but actually, a data signal for each bit is transmitted in parallel via the data bus line.

  When the multiplexer 3 detects that a self-refresh operation is being performed, such as when a control signal from the refresh controller 11 is input, the multiplexer 3 outputs the input address signal for self-refresh operation to the row decoder 2. The row decoder 2 outputs to the memory array 1 a word line selection signal for selecting a word line in which the corresponding memory cell is arranged based on the input address signal for self-refresh operation. The sense amplifier 5 sequentially detects each memory cell disposed on the selected word line in accordance with the refresh timing signal, amplifies the read information, and writes it again to the corresponding memory cell. At this time, the semiconductor memory device is controlled by delaying one of the operations so that the timing of reading and writing information of the normal memory cell does not coincide with the timing of the self-refresh operation. .

As described above, during the operation, the read control signal (OE) cycle T _MR and the write control signal (WE) cycle T _MW, and the self-refresh time shorter than the minimum information storage holding time of the memory cells of the memory array at the non-operation time. A self-refresh operation is performed in combination with the period T _s .

(2) When the semiconductor memory device is in a non-operating state (corresponding to FIG. 3)
Since the read control signal (OE) and the write control signal (WE) are not generated when the semiconductor memory device is in a non-operating state, the operation detection signal is not output from the operation detection circuit 18. For this reason, the OR circuit 14 outputs a refresh timing signal (signal shown in FIG. 3A) composed of a clock signal from the refresh timer 12. Then, the address counter 13 outputs a self-refresh operation address signal (signal shown in FIG. 3B) in response to the refresh timing signal of the cycle T _s . As described above, at the time of non-operation, the read control signal (OE) period T _MR and the write control signal (WE) period T _MW are longer than the minimum information storage holding time of the memory cells of the memory array at the non-operation time. the self-refresh operation is also carried out in a short period T _s.

With such a configuration, during the operation of the semiconductor memory device, the self-refresh operation is performed at intervals of the cycles T _s , T _MR , and T _MW , so that the time is shorter than the self-refresh cycle T _s during non-operation. A self-refresh operation is performed at intervals. In particular, in the above example, the read cycle T _MR is much less than 1/10 of the self-refresh period T _s of the time of non-operation, the degree less than half of the write period T _MW self refresh period T _s at the time of non-operation Therefore, during operation, the self-refresh operation can be performed at a repetition rate of 10 times or more compared with that during non-operation.

  As a result, the self-refresh operation interval becomes very short even during an operation in which the information storage retention time of the memory cell is shorter than that during the non-operation time, so that it is possible to configure a semiconductor memory device that reliably retains information. . When the memory cell is not in operation, the refresh operation is performed in a self-refresh cycle longer than that in the operation according to the time during which the memory cell can hold information when the memory cell is not in operation. Disappear.

  Normally, the information storage holding time during operation does not become about 10 times shorter than the information storage holding time during non-operation. However, if the information storage holding time during operation is refreshed repeatedly during operation. When the interval is shorter than the interval, the access cycle (data read cycle or data write cycle) to the memory array 1 may be set shorter than the information storage holding time.

  Further, with the above-described configuration, a circuit that generates a refresh signal during operation from a clock signal for refresh operation during non-operation and an operation detection signal can be formed using only a logical OR circuit. A semiconductor memory device that performs different refresh operations during operation and non-operation can be realized with a simple structure.

  In addition, with the above-described configuration, the circuit that generates the operation detection signal can be configured with two logical product circuits and one logical sum circuit, so that the semiconductor memory device having the above-described function can be further simplified. Can be realized with a structure.

1 is a block diagram showing a configuration of a portion related to a refresh operation of a semiconductor memory device according to an embodiment of the present invention. Timing chart showing signals of self-refresh operation when semiconductor memory device is operating Timing chart showing signals of self-refresh operation when semiconductor memory device is not operating A block diagram showing a configuration of a portion related to a refresh operation of a conventional semiconductor memory device

Explanation of symbols

1-memory array 2-row decoder 3-multiplexer 4-row address buffer 5-sense amplifier 6-column decoder 7-column address buffer 8-data input / output unit 10-refresh address generation circuit 11-refresh controller 12-refresh timer 13 -Address counters 14 and 15-OR circuits 16 and 17-AND circuit 18-Operation detection circuit 21-Read controller 22-Write controller

Claims (3)

In a semiconductor memory device that performs a self-refresh operation of cells constituting a memory array in response to a refresh timing signal,
Refresh signal generating means for generating a refresh signal of a predetermined period;
Operation detecting means for detecting a read control signal having a cycle shorter than the refresh signal or a write control signal having a cycle shorter than the refresh signal for the memory array;
The refresh timing signal is output by synthesizing the output signal of the operation detecting means based on the period of the read control signal and the write control signal and the refresh signal so as to be a period equal to or less than a predetermined period of the refresh signal. Timing signal generating means;
An address counter that generates address data of cells of the memory array that performs the self-refresh operation in response to the refresh timing signal output from the timing signal generation means ;
The semiconductor memory device according to claim 1, wherein the timing signal generating means is an OR circuit .   The refresh signal generating means refreshes with a cycle shorter than a minimum information storage holding time in a non-operating state of all cells constituting the memory array and longer than a cycle of the read control signal or the write control signal The semiconductor memory device according to claim 1, wherein the signal is generated. The motion detection means is
A first AND circuit that outputs a detection signal by receiving the read control signal and a selection signal for selecting a read target cell of the memory array;
A second AND circuit that outputs a detection signal by receiving the write control signal and a selection signal for selecting a write target cell of the memory array;
3. The semiconductor memory according to claim 1, comprising a logical sum circuit that inputs a detection signal from the first logical product circuit and a detection signal from the second logical product circuit and outputs a combined signal thereof. apparatus.

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