JPH05196697A - Test pattern making method - Google Patents

Abstract

PURPOSE:To make a test pattern capable of testing other places without ex changing a specified inferior IC/LSI. CONSTITUTION:An in-disassembly-circuit IC/LSI extracting means 1 extracts the integrated circuit contained in a divided circuit from the information of each divided circuit, and outputs the correspondence file wherein the divided circuit and an integrated circuit are made to correspond to each other. The divided circuit and a correspondence giving means 2 for pattern numbers give the correspondence for pattern number within each divided circuit and the circuit at large based on the test pattern of each divided circuit and the test pattern of the circuit at large made from it, and outputs the correspondence file wherein the divided circuit and the pattern number correspond to each other. And, the integrated circuit and the correspondence giving means 3 for pattern number extract which pattern of the test patterns of the circuit at large each integrated circuit is being tested by, based on these two correspondence file, and outputs the correspondence file for the integrated circuit and the pattern number of the circuit at large.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern creating method, and more particularly to a test pattern creating method using a circuit division method for a package circuit having an IC / LSI mounted thereon.

[0002]

2. Description of the Related Art Conventionally, in this type of test pattern creating method, when a test pattern of the entire circuit is created, the mounted IC
/ LSI and the pattern number of the test pattern of the entire circuit were not associated.

[0003]

In the conventional test pattern creating method described above, a test is performed using the pattern,
Even if an error is detected in a certain pattern and the specific IC / LSI can be identified as defective, when an error occurs in the remaining pattern, whether or not it is the influence of the already known failure is determined. Since it is not known, there is a drawback in that the remaining patterns cannot be tested for failure until the defective IC / LSI is replaced.

[0004]

According to the present invention, integrated circuits included in these divided circuits are extracted from the information of each divided circuit, and a first correspondence file in which the divided circuits and the integrated circuits are made to correspond to each other is created. Based on the IC / LSI extracting means in the divided circuit for outputting, the test pattern of each divided circuit and the test pattern of the whole circuit created from them, the pattern number in the test pattern of each divided circuit and the whole circuit is determined. Dividing circuit-pattern number associating means for performing associating and outputting a second corresponding file in which the dividing circuit and the pattern number are made to correspond, and the first corresponding file and the first Based on the two corresponding files, it is extracted which of the test patterns of the entire circuit each integrated path is tested for, and the pattern of the integrated circuit and the entire circuit is extracted. Integrated circuit outputs a correspondence list that associates a No. - the pattern number correlating means, and a.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flow chart showing a processing procedure for realizing an embodiment of the present invention. Referring to FIG. 1, the present invention comprises an IC / LSI extracting means 1 in a divided circuit, a dividing circuit and a pattern number associating means 2, and an IC / LSI and a pattern number associating means 3.

The IC / LSI extracting means 1 in the divided circuit inputs the divided circuit information 4 and the IC / LS included in the divided circuit.
I is extracted and the divided circuit and IC / LSI correspondence file 8
Output to.

Corresponding means 2 for associating the division circuit and the pattern number
Inputs the test pattern 5 of the divided circuit and the test pattern 6 of the whole circuit created from these, finds out which pattern number in the test pattern of the whole circuit the test pattern of the divided circuit corresponds to, and divides it. It is output as a correspondence file 7 of circuits and pattern numbers.

The means 3 for associating IC / LSI and pattern numbers inputs the divided circuit / IC / LSI correspondence file 8 and the divided circuit / pattern number correspondence file 7 and inputs each IC / IC
In the test pattern of the entire circuit, the pattern number of the LSI to be tested is identified and output as the correspondence list 9 of the IC / LSI and the pattern number.

FIG. 2 is a schematic diagram showing an example to which the test pattern creating method of the present invention is applied.

First, the IC / LSI included in each divided circuit is extracted from the information of each divided circuit, and the divided circuit and IC / LSI are extracted.
It is output as the corresponding file 11 of the LSI. In this embodiment, the divided circuit A includes an L1 mounted IC, and the divided circuit B includes an L1 mounted IC and an L2 mounted LSI.
The divided circuit C includes an L2 mounting LSI.

Next, the test pattern of the entire circuit created from the test pattern 12 of the divided circuit A, the test pattern 13 of the divided circuit B, and the test pattern 14 of the divided circuit C is set to 15. In the present embodiment, in the test patterns of the entire circuit, the pattern number 1 is created from the pattern A1 of the divided circuit A, and the pattern number 2 is created from the pattern A2.
Similarly, it is shown that the pattern of pattern number 7 is created from the pattern C3 of the division circuit C.

Subsequently, the test pattern 12 of the divided circuit A,
The test pattern 13 of the divided circuit B, the test pattern 14 of the divided circuit C, and the test pattern 15 of the entire circuit are input, and the correspondence file 16 of the divided circuit and the pattern number is output. In this embodiment, the divided circuit A corresponds to the pattern numbers 1 and 2 in the test pattern of the entire circuit, and the divided circuit B corresponds to the pattern numbers 5, 6 and 7.

Finally, the divided circuit / IC / LSI correspondence file 11 and the divided circuit / pattern number correspondence file 16
Is input, and the correspondence list 17 of the pattern numbers of the test patterns of the IC / LSI and the entire circuit is output. In this embodiment, the IC mounted on L1 is included in the divided circuits A and B. Therefore, in the test pattern of the entire circuit, pattern numbers 1, 2,
Tested with 3,4 patterns. In addition, L2 mounted LSI
Indicates that the pattern is included in the divided circuit B and the divided circuit C, and therefore the pattern numbers 3, 4, 5, 6, and 7 are tested.

The correspondence list 17 of IC / LSI and pattern numbers created in this way can be used as follows.

First, it is assumed that the circuit is tested by the test pattern 15 for the entire circuit and an error occurs. Then, if the result of the error analysis shows that the mounted IC of L1 is defective, the mounted IC of L1 is tested only in the patterns of pattern numbers 1, 2, 3 and 4, and the remaining pattern numbers 5 and 6 are tested. , 7
The pattern is not tested. Therefore, pattern number 5,
Patterns 6 and 7 can be used to test for other failures.

The reason for this is that if a subsequent test result error occurs, it can be specified that the cause is other than the failure detected first.

[0018]

As described above, according to the present invention, the IC / L
When a test pattern is created for a package circuit with SI mounted by using the circuit division method, the mounted IC / L
If a test is performed and an error is detected and a certain IC / LSI is found to be defective by outputting a correspondence list of SI and the pattern number under which it is tested, before replacement of the defective IC / LSI There is an effect that it is possible to test whether or not there is another failure by using a pattern that is not affected by the failure of the IC / LSI.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure for realizing an embodiment of the present invention.

FIG. 2 is a schematic view showing one row to which the test pattern creating method of the present invention is applied.

[Explanation of symbols]

 1 IC / LSI extraction means in divided circuit 2 Correlation means of divided circuit and pattern number 3 Correspondence means of IC / LSI and pattern number 4 Divided circuit information 5 Test pattern of divided circuit 6, 15 Test pattern of entire circuit 7, 16 division circuit and pattern number correspondence file 8,11 division circuit and IC / LSI correspondence file 9,17 IC / LSI and pattern number correspondence list 10 whole circuit 12 division circuit A test pattern 13 division circuit B test pattern 14 Test pattern of divided circuit C A, B, C Divided circuit L1 mounted IC L2 mounted LSI

Claims (1)

[Claims] 1. A test pattern creating method for creating a test pattern by dividing a package circuit on which an integrated circuit (IC / LSI) is mounted, and including the information of each divided circuit in the divided circuits. IC / L in a divided circuit for extracting an integrated circuit and outputting a first correspondence file in which the divided circuit and the integrated circuit are made to correspond to each other.
Based on the SI extracting means, the test pattern of each of the divided circuits and the test pattern of the whole circuit created from them, the pattern numbers in the test patterns of the divided circuits and the whole circuit are associated with each other, and the division is performed. Based on a divided circuit-pattern number associating unit that outputs a second corresponding file that associates a circuit with the pattern number, and the first corresponding file and the second corresponding file that each unit outputs. An integrated circuit-pattern that extracts which of the test patterns of the entire circuit is tested for each integrated path and outputs a correspondence list in which the integrated circuit and the pattern number of the entire circuit are associated with each other. A tester pattern creating method characterized by comprising a number associating means.