JPH05196680A - Wire breaking and malfunction preventive circuit - Google Patents

Abstract

PURPOSE:To prevent the use in dangerous condition of an electric unit by the wire breaking inside an IC by providing a wire break detecting circuit, which detects the wire breaking between logical circuits, and a malfunction preventive means, which operates by the output, inside the IC which has a plurality of logical circuits. CONSTITUTION:A wire break detecting circuit 4 recedes the output a of a prestage logical circuit 1 and the input of a poststage logical circuit 2, and detects the nonconformity between these two inputs. Moreover, the circuit 4 has a D latch 7 where the outputs of an exclusive logical circuit 6 and a circuit 6 are input to both a C terminal and a CK terminal. And in case that the inputs a and b are in conformity with each other, the output of the gate 6 comparing the inputs a and b is intact at L, so the output of the terminal Q of the latch 7 is intact at L in normal operation state. On the other hand, in case of the nonconformity of the inputs and b, the output of the gate 6 becomes H, and it is latched 7, and is outputted as a stop signal. Since this signal is made by the latch 7, by a through current preventive circuit 5, even if the voltage of a node b is fixed on the level of power source voltage, it continues to be outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disconnection malfunction prevention circuit for detecting a disconnection failure between logic circuits in a semiconductor integrated circuit to prevent malfunction.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit (hereinafter referred to as "IC")
Internal disconnection failure is described in, for example, Japanese Unexamined Patent Publication No. 1991/1991.
As disclosed in Japanese Patent Laid-Open No. 71, it was detected from the outside of the IC. Therefore, it takes time to detect a failure, and malfunctions and abnormal current consumption occur in the electrical unit controlled by this IC. This is because the penetration current due to internal disconnection of the IC is extremely weak,
This is because there is a case where the final output as is coincidentally with the normal output. That is, it may happen that the electrical equipment unit is used in a very dangerous state without detecting the internal disconnection of the IC.

In view of the above problems, it is an object of the present invention to provide a disconnection malfunction prevention circuit capable of avoiding use of an electrical component unit in a dangerous state due to internal disconnection of an IC.

[0004]

DISCLOSURE OF THE INVENTION A disconnection malfunction prevention circuit according to the present invention is operated by an disconnection detection circuit for detecting disconnection between logic circuits in an IC having a plurality of logic circuits, and an output of the disconnection detection circuit. It is characterized in that a malfunction prevention means is provided.

The disconnection detection circuit is configured to operate based on the detection of a mismatch between the output of the preceding logic circuit and the input of the succeeding logic circuit.

The malfunction preventing means has means for stopping the operation of the logic circuit in the IC.

Further, the malfunction preventing means is the IC
It has means for outputting a stop signal to the unit controlled by.

[0008]

According to the present invention, it is possible to avoid the use of the electric component in a dangerous state due to the internal disconnection of the IC. Further, by using the stop signal output from this circuit, it becomes easy to incorporate the fault tolerant system into the electrical unit.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, a P-MOS transistor T
The output terminal of the pre-stage logic circuit 1 which is a CMOS inverter constituted by r1 and the N-MOS transistor Tr2, and similarly the P-MOS transistor Tr3 and the N-MOS.
A signal line 3 is connected to an input end of a rear logic circuit 2 which is a CMOS inverter constituted by a transistor Tr4, and is connected in parallel to the signal line 3 in order to detect disconnection of the signal line 3. When the disconnection detection circuit that has been disconnected and the signal line 3 are disconnected, the P-MOS transistor Tr3 and the N-MOS transistor Tr4 of the subsequent logic circuit 2 are simultaneously turned on, and an abnormal through current flows. An abnormal through current prevention circuit 5 is provided to prevent this.

The disconnection detection circuit 4 is a circuit which receives the output a of the front-stage logic circuit 1 and the input b of the rear-stage logic circuit 2 which is an input disconnection monitored circuit as inputs and detects a mismatch between these two inputs. 2, the exclusive OR circuit 6 (hereinafter referred to as "EOR gate") and the E
The output of the OR gate 6 is composed of a D latch 7 input to both the D terminal and the CK terminal.

In FIG. 2, first, when the inputs a and b match each other, the output of the EOR gate 6 comparing a and b remains "L", so that the D latch 7 Q
Output of terminal (that is, stop signal "H" enable)
Remains in the “L” state and is in a normal operation state.

On the other hand, if the inputs a and b do not match, EO
The output of the R gate 6 becomes "H", which is latched by the D latch 7 and immediately continues to be output as a stop signal. Since this stop signal is formed by the D latch 7, once it is output, it continues to be output even if the voltage of the node b is fixed to the power supply voltage level by the shoot-through current prevention circuit 5 (of course, the output of the EOR gate 6). Returns to "L").

The stop signal also has a function of being led to the outside from one of the output terminals of the semiconductor integrated circuit to stop the operation of the electrical equipment unit controlled by the semiconductor integrated circuit.

FIG. 3 is a diagram showing an example of the structure of the through current prevention circuit 5. This circuit 5 uses the input b of the post-stage logic circuit 2 which is an input disconnection monitored circuit as its input, and changes the level of the input b when the potential level of the input b is at the intermediate level between the power supply voltage level and the ground level. A current mirror circuit that raises the voltage to the power supply voltage level, and includes P-MOS transistors Tr5 and Tr6 and an N-MOS transistor T.
It is composed of r7 and Tr8.

The operation of the abnormal shoot-through current prevention circuit 5 will now be described. First, when the signal line 3 is not disconnected, the output of the disconnection detection circuit 4 which is an enable signal of the abnormal shoot-through current prevention circuit 5 (that is, a stop signal). ) Is "L", the N-MOS transistors Tr7, T
r8 is in the "OFF" state. Therefore, the potential c of the gates of the P-MOS transistors Tr5 and Tr6 connected to each other causes the transistors Tr5 and Tr6 to be OF
It is stable at the F potential. That is, the abnormal shoot-through current prevention circuit 5 does not operate when the signal line 3 is not disconnected.

On the other hand, when the signal line 3 is broken, the above-mentioned stop signal becomes "H", the potential of the input b becomes an intermediate level between the power supply voltage level and the ground level, and the circuit 5 becomes the enable state. Become. That is, NM
Both OS transistors Tr7 and Tr8 are "ON"
Then, the level of the potential c decreases. Therefore,
P-MOS transistors Tr5 and Tr6 are "ON"
Then, the level of the input b is raised to the power supply voltage level through the transistor Tr6. Input b
Is fixed to the power supply voltage level, the second-stage logic circuit 2
The penetrating current flowing through disappears.

That is, according to the circuit of FIG.
When the input b of the latter-stage logic circuit 2 fluctuates between the power supply voltage and the ground level due to the disconnection, the level is fixed to the power supply voltage to prevent an abnormal through current from flowing to the latter-stage logic circuit 2. Therefore, it is possible to prevent malfunction of the circuits subsequent to the logic circuit 2 at the same time.

Although the abnormal shoot-through current prevention circuit 5 in this embodiment is configured to fix the input b of the subsequent logic circuit 2 to the power supply voltage when the signal line 3 is disconnected,
It goes without saying that the circuit 5 may be replaced with a circuit having the function of fixing the input b to the ground level.

[Brief description of drawings]

FIG. 1 is a block diagram of a disconnection malfunction prevention circuit according to the present invention.

FIG. 2 is a circuit diagram of a disconnection detection circuit.

FIG. 3 is a circuit diagram of an abnormal shoot-through current prevention circuit.

[Explanation of symbols]

 1 front stage logic circuit 2 rear stage logic circuit 3 signal line 4 disconnection detection circuit 5 abnormal through current prevention circuit 6 EOR gate 7 D latch

Claims (4)

[Claims] 1. A semiconductor integrated circuit having a plurality of logic circuits is provided with a disconnection detection circuit for detecting a disconnection between the logic circuits, and a malfunction prevention unit operated by an output of the disconnection detection circuit. A disconnection malfunction prevention circuit characterized by the following. 2. The disconnection malfunction prevention circuit according to claim 1, wherein the disconnection detection circuit is configured to operate based on detection of a mismatch between an output of the preceding logic circuit and an input of the succeeding logic circuit. . 3. The disconnection malfunction prevention circuit according to claim 1, wherein the malfunction prevention means includes means for stopping the operation of the logic circuit in the semiconductor integrated circuit. 4. The disconnection malfunction prevention circuit according to claim 1, wherein the malfunction prevention means includes means for outputting a stop signal to a unit controlled by the semiconductor integrated circuit.