JPH0519221B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a rotation control device for a motor used in a compact disc player or the like.

Conventional configuration and its problems Normally, during playback on a compact disc player, a PLL (phase control loop) is used to demodulate the EFM (8-14 conversion) signal detected by pickup from a disc on which information is recorded in a spiral shape. Since the synchronous pull-in range is limited to approximately ±6%, it is necessary to bring the rotational speed of the spindle motor that drives the disk within that range by other means.
Normally, the longest cycle signal included in the EFM signal is fed back to the spindle motor as speed information, and the rotation is controlled to the above-mentioned pull range, and then, at the same time as the PLL starts operating, the extracted clock signal detected by the PLL is converted into speed or A method is used in which the phase information is fed back to the spindle motor and subjected to phase control to perform constant linear velocity (CLV) control.
In this case, there is not much problem when playing normal music signals, but when playing a silent groove pattern, due to the unique characteristics of that pattern, the PLL deviates slightly from the frequency that should be synchronized (for example, about -3%). ) May result in pseudo synchronization. This is because the silent groove pattern repeats the same pattern in a relatively short cycle, which means that the phase comparator that constitutes this PLL has a point where it outputs a phase error of almost 0 in addition to the correct synchronization point. For example, in such a case, there is a problem that once the spindle motor deviates from the correct synchronization point and reaches the pseudo synchronization point, the spindle motor cannot escape from this state forever and becomes a deadlock state.

OBJECT OF THE INVENTION An object of the invention is to provide a motor rotation control device capable of escaping the PLL from its pseudo-synchronized state.

Structure of the Invention The present invention is characterized in that a pseudo-synchronization detection means for detecting a pseudo-synchronization state of the phase control loop is provided, and that the pseudo-synchronization detection means applies a speed fluctuation disturbance signal to the speed control loop. That is,
This disturbance signal causes the phase control loop to escape from the pseudo-synchronized state and reach the synchronized state of the phase control loop.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIGS. 1 to 6. That is, numeral 1 is a pickup for detecting information from a disk 3 driven by a motor 2, and a speed error detection circuit 4 detects a speed error output from the pickup.

At the same time, from the detection output of pickup 1,
The motor 2 is controlled by the PLL (phase control loop) circuit 5.
A rotation synchronized clock signal (hereinafter abbreviated as clock signal) is extracted, and the phase comparison circuit 7 detects the phase difference between the extracted clock signal and the external rotation reference frequency signal _fS . Reference numeral 8 denotes an adder circuit for adding the output of the speed error detection circuit 4 and the output of the disturbance signal generating circuit 12 that forcibly provides disturbance to the rotation of the motor 2. The output of the adder circuit 8 and the phase comparator circuit 7
The two outputs are selected by the changeover switch 9 and input to the motor drive circuit 10, where they are converted into electric power to be supplied to the motor 2. Furthermore, the PLL circuit 5 outputs an operating state determination signal S that switches the switch 9 depending on the state of the clock signal extraction operation.
When the PLL circuit 5 cannot extract a clock signal (that is, when it is not in a synchronous state), the switch 9 is connected to the contact A side, and the pickup 1, speed error detection circuit 4, adder circuit 8, motor drive circuit 10, and motor 2 A speed control loop is formed, and this speed control loop controls the rotational speed of the motor 2 to a rotational speed at which the PLL circuit 5 can extract a clock signal. When the PLL circuit 5 starts extracting a clock signal (that is, when it becomes synchronized), connect the switch 9 to the contact B side, pick up the pickup 1, PLL circuit 5, frequency divider circuit 6, and phase comparison. circuit 7,
The motor drive circuit 10 and the motor 2 constitute a phase control loop, and the motor 2 is rotationally controlled in synchronization with the reference frequency signal _fS . 11 is a pseudo synchronization detection circuit that detects a pseudo synchronization state when the PLL circuit 5 is pseudo synchronized at a point other than the correct synchronization point, and a reference oscillation circuit that outputs the same frequency as the output frequency when the PLL circuit 5 is correctly synchronized. Circuit (reference frequency generation means) 11a, PLL circuit 5 and reference oscillation circuit 1
A frequency subtraction circuit 11b that takes the difference between the two output frequencies of 1a, a frequency-voltage conversion circuit 11c that converts the output frequency of the frequency subtraction circuit 11b into a voltage, and a range of the output voltage of the frequency-voltage conversion circuit 11c is detected. Window comparator (comparison means) for
11d. Window comparator 11
The output of d, that is, the output of the pseudo synchronization detection circuit 11, is input to the disturbance signal generation circuit 12, and a disturbance is forcibly applied to the rotation of the motor 2.

In FIG. 1, the case where the PLL circuit 5 is normally synchronized will be described first. When the PLL circuit 5 is not in synchronization and cannot extract the clock signal, such as when the motor 2 starts rotating,
The switch 9 is controlled by the state determination signal S and connected to the contact A side, and as a result, the speed control loop is formed, and the motor 2 is roughly controlled to try to bring the rotational speed close to the normal rotational speed. This speed control operation causes the motor 2 to approach the rotational speed that is possible in the pulling range of the PLL circuit 5, and as a result, the PLL circuit 5
When the clock extraction operation starts, the switch 9 is switched to the contact B side by the state discrimination signal S, and the control loop is switched to the phase control loop, and as a result, the motor 2 is controlled to rotate in synchronization with the external reference frequency _S. be done.

Next, a case where the PLL circuit 5 is pseudo-synchronized will be described. The motor 2 is roughly controlled by the speed control loop and tries to enter the pull-in range of the PLL circuit 5, but at that time, the detection signal of the pickup 1 has a phase error even though it is not a synchronous frequency like a silent groove pattern. When detecting a signal such that 0 is almost 0, the output frequency of the PLL circuit 5 may become pseudo-synchronized even though it is not at the synchronization point. Therefore, the switch 9 cannot be switched from the contact A side to the contact B side by the state determination signal S of the PLL circuit 5, and therefore the speed control loop is fixed and it is impossible to escape from this state forever. . Therefore, the pseudo synchronization detection circuit 1
1 detects the state, triggers the disturbance signal generation circuit 12 to generate an AC signal having one cycle or more, and inputs it to the addition circuit 8 to be used as part of the speed control loop. give a disturbance,
The rotational speed of the motor 2 is varied in both positive and negative directions. As a result, the input signal of the PLL circuit 5 is frequency-modulated in both positive and negative directions around the current pseudo-synchronization state, and when it approaches the original synchronization point, it is pulled into the true synchronization point, and the PLL circuit 5 extracts the clock signal. At the same time, the switch 9 is connected from the contact A side to the contact B side to establish a phase control loop, and the motor 2 shifts to a normal synchronous state.

2 and 3 show the frequency subtraction circuit 1
1b is a graph illustrating the D flip-flop circuit and its operation; FIG. This means that the level state of the D input signal f _D of the D flip-flop circuit is
It performs calculations by taking advantage of the property that the CK (clock) input signal f _C is read into the D flip-flop circuit only at the rising (falling) point.
By connecting to the output terminals of circuit 5 and reference oscillation circuit 11a, frequency subtraction is performed. FIG. 4 shows a specific configuration example of the frequency-voltage conversion circuit 11c, in which the output pulse train of the one-shot multivibrator 13, which is triggered by the edge of the input signal and outputs a constant-width pulse, is converted into a low-pass circuit composed of a resistor 14 and a capacitor 15. By integrating with a filter, it is possible to obtain a voltage that corresponds to the frequency of edges of the input signal, that is, that is proportional to the input frequency.

FIG. 4 shows an example of the configuration of the window comparator 11d, in which the input voltage is compared by a voltage comparison circuit 17 with a reference power supply 16 and a voltage comparison circuit 19 with a reference power supply 18, and the two voltage comparison circuits 17, 1
The outputs of 9 are combined by a gate circuit 20.
In order to specifically explain the operation of the pseudo synchronization detection circuit 11, which is composed of the reference oscillation circuit 11a, the frequency subtraction circuit 11b, the frequency-voltage conversion circuit 11c, and the window comparator 11d, as an example, the PLL circuit 5 The synchronous output frequency is 4.3218M
Hz, and the case where the pseudo synchronization frequency is 4.1921MHz, which is about 3% lower. At this time, if the conversion gain of the frequency-voltage conversion circuit 11c is 50 mV/KHz and the reference power supplies 16 and 18 are set to voltages 4.32V and 8.64V corresponding to 2% and 4% of the synchronous frequency 4.3218MHz, the PLL circuit 5 Pseudo sync frequency 4.1921M
When pseudo-synchronized with Hz, the frequency subtraction circuit 11b outputs a difference frequency of 129.7KHz, and the frequency-voltage conversion circuit 11c outputs 6.48V. This voltage is divided into two reference levels by the window comparator 11d.
4.32V and 8.64V are compared, it is detected that the voltage is within that range, and it is determined that the PLL circuit 5 is pseudo-synchronized. FIG. 5 shows an example of the configuration of the disturbance signal generation circuit 12, in which the output of the oscillation circuit 23 is controlled by an analog switch 22 controlled by a one-shot multivibrator 21 that generates constant width pulses in response to an input trigger. Ru. That is, the disturbance signal generation circuit 12 operates to generate an oscillation output for a certain period of time from the time when the input signal is received.

Effects of the Invention As described above, when extracting a clock from a special pattern such as the silent groove pattern of a compact disc, the present invention immediately searches for the correct synchronization point and returns to the synchronization state even after the clock has reached a pseudo synchronization state. It has the excellent effect of being able to draw people in.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a D flip-flop constituting the frequency subtraction circuit, Fig. 3 is a graph explaining its operation, and Fig. 4 is a frequency subtraction circuit. Voltage conversion circuit diagram, Figure 5 is the window comparator circuit diagram,
FIG. 6 is a block diagram of the disturbance signal generation circuit. 1...Pickup (Pickup means), 2
... Motor, 3 ... Disk, 4 ... Speed error detection circuit (part of speed control loop), 5 ... PLL circuit (phase control loop), 6 ... Frequency divider circuit, 7 ...
Phase comparison circuit, 8...addition circuit, 9...switch (changeover switch means), 10...motor drive circuit,
11...Pseudo synchronization detection circuit (part of pseudo synchronization detection means), 11a...Reference oscillation circuit (reference frequency generation means), 11b...Frequency subtraction circuit, 11c...
...Frequency-voltage conversion circuit, 11d...Window comparator (comparison means), 12...Disturbance signal generation circuit, _fS ...Phase reference signal.

Claims (1)

[Scope of Claims] 1. A motor that drives a disk, a pickup means that detects information on the disk, and a speed control loop that detects rotational speed information of the disk from the pickup means and controls the speed of the motor. a phase control loop that controls the phase of the motor by comparing rotational phase information of the disk detected from the pickup means with a phase reference signal; and a speed control loop or A motor comprising a changeover switch for selecting one of the phase control loops, and pseudo-synchronization detection means for detecting a pseudo-synchronization state of the phase control loop and applying a speed fluctuation disturbance signal to the speed control loop. rotation control device. 2. The pseudo synchronization detection means includes a reference frequency generation means that generates a frequency signal that is the same as a frequency signal output when the phase control loop is correctly synchronized, and an output frequency of the reference frequency generation means and an output of the phase control loop. A frequency subtraction means for detecting a frequency difference, a frequency-voltage conversion means for converting an output frequency of the frequency subtraction means into a voltage, and a comparison means for comparing an output signal of the frequency-voltage conversion means with a reference voltage. 2. The motor rotation control device according to claim 1, comprising: a disturbance signal generation circuit driven by the comparison means; and an addition means for adding the output of the disturbance signal generation circuit to the speed control loop.