JPH05191735A - Ccd solid-state image pickup element - Google Patents

Abstract

PURPOSE:To increase an output voltage by changing a conductance of a load MOSFET complementarily with respect to an amplifier MOSFET of a source follower circuit to increase the amplitude. CONSTITUTION:When a voltage signal generated from a detection capacitor CS is high, the conductance of amplifier MOSFETs Q2, Q4, Q6 is increased, a large current flows to a resistor RS thereby increasing a source potential. Thus, the conductance of load MOSFETs Q3, Q5, Q7 in a feedback amplifier AMP is decreased, the source potential of the Q2, Q4, Q6 is increased to increase the output voltage. When a voltage signal is low, the output voltage is lowered by a similar action. Then the output voltage is increased by applying positive feedback to a source output voltage of each amplifier MOSFET by the load MOSFET controlled by the self bias resistor RS and a feedbacks signal of the AMP.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD type solid-state image pickup device, for example, a technique effective when used in a device provided with a floating diffusion amplifier (hereinafter, simply referred to as FDA).

[0002]

2. Description of the Related Art FDA is used for a charge-voltage conversion circuit and a voltage amplification circuit of a CCD type solid-state image pickup device. For such FDA, see, eg, US Pat. No. 4,646,1.
There is number 19.

[0003]

When the above FDA is used, in order to increase the voltage gain, the capacitance value of the detection capacitor that receives the signal charge and converts it into the voltage signal may be reduced. However, there is a limit in the manufacturing process to reduce the capacitance value of this capacitor. Therefore, it is conceivable to increase the gain in the source follower circuit that power-amplifies the voltage signal. However, since the source follower circuit basically performs power amplification, the signal amplitude itself of the voltage signal cannot be increased, and strictly speaking, the signal amplitude is attenuated according to the conductance ratio between the amplification MOSFET and the load MOSFET. Will end up.

It is an object of the present invention to use a source follower circuit and to substantially increase the output voltage of a CC.
It is to provide a D-type solid-state imaging device. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, an amplification MOSFET that receives the voltage signal of the detection capacitor that converts the signal charge transferred from the CCD transfer path into a voltage signal, and this amplification MOSF.
A source-follower circuit including a load MOSFET provided on the source side of the ET and at least one source-follower circuit for receiving and amplifying an output signal of the source-follower circuit of the first stage are provided, and the source of the load MOSFET of the source-follower circuit is A resistance means for self-bias is provided to negatively feed back the common source voltage to the gate of the load MOSFET via the feedback amplifier.

[0006]

According to the above means, the conductance of the load MOSFET is changed complementarily to the amplification MOSFET of the source follower circuit, so that the signal amplitude can be increased.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a schematic circuit diagram of an embodiment of a CCD type solid-state image pickup device to which the present invention is applied. In the figure, photodiodes D1 to D4 each consisting of a total of four in two rows and two columns are exemplarily shown as a representative in order to facilitate understanding of the CCD type solid-state imaging device itself. In an actual CCD type solid-state imaging device, photodiodes are arranged in a matrix in a plurality of rows and a plurality of columns, and as is well known, a large number of photodiodes of about 200,000 to about 400,000 are provided.

The anode side of the photodiode D1 is connected to the ground potential point of the circuit, and the cathode side is provided with a photogate (hereinafter simply referred to as PG gate) so that the photoelectrically converted signal charges are vertical CCD (hereinafter abbreviated as VCCD). V1
Transferred to the gate. Another photodiode D2 in the same row
Are transferred to the V3 gate of the VCCD via the PG gate. The photodiodes D3 and D4 in the other columns are also connected to the corresponding V1 and V of the VCCD via the PG gate similarly to the above.
Transferred to 3 gates.

The signal charge at the final stage of the VCCD is a horizontal CC.
D (hereinafter abbreviated as HCCD). HCCD
Is a high-speed charge transfer operation within 1H period in synchronization with the transfer pulses H1 and H2 until the next signal charge is transferred from the VCCD to the detection capacitor CS which converts the signal charge into a voltage signal. Tell. The OG provided at the output part of the HCCD is an output gate, and acts so that the signal charge of the HCCD is smoothly transferred to the detection capacitor CS. The timing pulse VG is supplied to the output gate OG.

Signal charges are converted into voltage signals by the capacitance CS. This voltage signal is FDA (Floating Diffu
The signal is amplified by a preamplifier PA called a sion amplifier) and transmitted from the output terminal OUT. When the signal charge transferred to the detection capacitor CS is output as a voltage signal through the preamplifier PA as described above, the reset gate RG and the reset drain shown in the form of a MOSFET (insulated gate field effect transistor) Q1. By RD, it is reset every one pixel, in other words, it is swept out. The reset gate RG
The reset drain has substantially the same structure as the MOSFET. A reset timing pulse is supplied to the reset gate RG, and a constant voltage such as an operating voltage is supplied to the reset drain RD.

An outline of the signal charge reading operation of the CCD type solid-state image pickup device will be described below. When the timing pulse supplied to the PG gate is set to the high level, the V1 gate and the V3 gate of the VCCD connected to the PG gate are set to the high level. As a result, the photodiode D
The photoelectric conversion charges of 1, D2 (D3, D4) are V of VCCD
1, read to V3 gate.

For example, in the odd field, the V2 gate is set to the high level. As a result, the signal charges under the V1 and V3 gates are mixed and temporarily collected under the V2 gate. Thereafter, the V3 gate is set to the high level at the next timing, and the V4 gate is set to the high level at the next timing, so that the signal charges are transferred downward. Below, V1
Each gate is set to a high level in the order of .about.V4, and the photoelectric conversion charges converted by the photodiode arranged above the gate are transferred in the same manner as above.

In the even field, V4 is set to the high level in place of the above V2 gate. As a result, the signal charges under the V3 and V1 gates are mixed with a shift of one row, and V4 is mixed.
Collected once under the gate. Hereinafter, the V1 gate becomes high level at the next timing, and V1 at the next timing.
The two gates are set to the high level and the signal charges are transferred downward. In this way, interlaced readout is equivalently performed by shifting the combination of signal charges in the odd field and the even field by one row.

The signal charges thus read out by the VCDD are transferred in parallel to the HCCD by the transfer operation, and the charge transfer operation is performed at high speed in the HCCD within a 1H period until the next signal charge is transferred. , Preamplifier P
A voltage signal is output through A.

FIG. 1 shows a circuit diagram of an embodiment of the FDA according to the present invention. The FDA of this embodiment is composed of the following circuits. The signal charge transferred via the output gate OG provided in the output part of the HCCD is transmitted to the detection capacitor CS. The voltage signal converted by the detection capacitor CS is supplied to the amplification MOSFET Q.
2 and current is amplified by the source follower circuit of the first stage consisting of the load MOSFET Q3 provided on the source side. The output signal of the first stage source follower circuit is an amplification MOSFET.
Q4, load MOSFET Q5, and amplification MOSFET Q6
And the load MOSFET Q7, and is sent from the external terminal OUT via a two-stage source follower circuit.

The load MOSFETs Q3, Q5 and Q7
Is composed of a depletion type MOSFET, and its source is provided with a resistor RS for self-bias between the source and the ground potential of the circuit. Although not particularly limited, depletion type MOSFETs are used as the amplification MOSFETs Q4 and Q6 in the second stage and the output stage. As described above, when the depletion type MOSFET is used, since there is no DC level loss due to the threshold voltage between the gate and the source, the operating voltage VDD can be lowered accordingly.
Alternatively, the output dynamic range with respect to the operating voltage VDD can be increased.

The detection capacitor CS has a MOSF.
A reset circuit composed of ETQ1 is provided. That is, when the timing pulse supplied to the reset gate RG is set to the high level, the MOSFET Q1 is turned on, and the potential of the reset drain RD is transmitted to the detection capacitor CS to sweep out the signal. That is, the diffusion layer forming the capacitor CS has a deep potential with respect to the output gate OG for the signal charge to be transferred next. In this way, the signal charges are transferred from the CCD transfer path side.

In this embodiment, in order to increase the voltage gain in the above three-stage source follower amplifier, in other words, in order to reduce the signal attenuation in the source follower circuit and substantially increase the gain, The source potential VS of the load MOSFET formed by the self-biasing resistor RS is inverted and amplified by the feedback amplifier AMP and is negatively fed back to the gates of the load MOSFETs Q3, Q5 and Q7 in common.

In this configuration, when the voltage signal formed by the detecting capacitor CS is high, the source output voltage is correspondingly increased and the amplification MOSFET Q2,
The conductance of Q4 and Q6 is also increased. Therefore, a larger current flows through the resistor RS and the source potential V
It acts to increase S. The feedback amplifier AMP receives the rise of the source potential VS and receives the load MOSFETQ.
3, it acts to lower the gate potential of Q5 and Q7. As a result, the conductances of the load MOSFETs Q3, Q5 and Q7 are reduced, and the amplification MOSFETs Q2 and Q7 are
4 and Q6 act to increase the source potential and increase the output voltage.

When the voltage signal formed by the detecting capacitor CS is low, the source output voltage is correspondingly lowered and the conductances of the amplification MOSFETs Q2, Q4 and Q6 are also reduced. Therefore, only a small current flows through the resistor RS, which acts to lower the source potential VS. The feedback amplifier AMP receives the drop of the source potential VS and receives the load MOSFETs Q3, Q5 and Q.
7 acts to raise the gate potential. As a result, the conductance of the load MOSFETs Q3, Q5, and Q7 becomes large, which acts to lower the source potential of the amplification MOSFETs Q2, Q4, and Q6, and lowers the output voltage.

As described above, the load MO controlled by the feedback signal of the self-bias resistor RS and the feedback amplifier AMP.
Since the SFETs Q3, Q5 and Q7 are positively fed back to the source output voltage of each amplification MOSFET, the output voltage can be increased. In such a feedback operation, if the feedback amount is set to a limit point where oscillation does not occur, a gain increase of about 3 dB can be expected compared to the conventional source follower circuit.

FIG. 2 shows a circuit diagram of an embodiment of the feedback amplifier AMP. In this embodiment, a differential amplifier circuit is used. That is, the differential amplification MOSFET Q
A constant current MOSFET Q14 that receives a constant voltage VC is provided at the common source of 10 and Q11. These differential MOS
Depletion type MOSFETs Q12 and Q13 are provided as loads on the drains of the FETs Q10 and Q11. These load MOSFETs Q12 and Q13 act as a constant current load by sharing their gates and sources.

The drain voltage of the differential amplification MOSFET Q13 is supplied to the gate of the source follower output MOSFET Q15. The source of the amplification MOSFET Q15 is the output terminal OUT, and the constant voltage VC
A constant current MOSFET Q16 that receives the voltage is provided as a load. In this configuration, the gate of the differential amplification MOSFET Q10 is a non-inverting input (+), and the differential amplification MOSFET
The gate of TQ11 is an inverting input (-). Therefore, when used as a negative feedback amplifier, the source voltage VS is supplied to the gate of the differential amplification MOSFET Q11 as the inverting input (-), and a feedback circuit for gain setting is provided between the gate and the output terminal OUT. .. A bias circuit is provided at the gate of the differential amplification MOSFET Q10 as the non-inverting input (+).

When the CCD type solid-state image pickup device is composed of a CMOS circuit, the load circuit of the differential amplifier circuit is P
The channel type MOSFET may be configured in the form of a current mirror. Or N channel type M
The gate and drain of the OSFET may be connected and used as a load. The feedback amplifier AMP is
In addition to the differential amplifier circuit as described above, an amplifier MOSFET having a gate input and a source grounded, and a load MOS on its drain
It is also possible to use an inverting amplifier circuit composed of a load circuit composed of an FET or the like.

The operational effects obtained from the above embodiment are as follows. That is, (1) A first-stage source follower including an amplification MOSFET that receives the voltage signal of the detection capacitor that converts the signal charge transferred from the CCD transfer path into a voltage signal, and a load MOSFET that is provided on the source side of the amplification MOSFET. In a preamplifier including a circuit and at least one source follower circuit that receives and amplifies an output signal of the first-stage source follower circuit, a self-biasing resistor means is provided at the source of the load MOSFET of the source follower circuit, and this commonization is performed. By negatively feeding back the generated source voltage to the gate of the load MOSFET via the feedback amplifier, the conductance of the load MOSFET is changed complementarily to the amplification MOSFET of the source follower circuit, and positive feedback is applied. It is possible to increase the signal amplitude The effect is obtained that that.

(2) By using a depletion type MOSFET as the second and subsequent amplification MOSFETs,
The effect that a large output dynamic range can be taken is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, it may be configured by a two-stage source follower circuit including a first stage source follower circuit and an output stage source follower circuit. CC
The D transfer path may be a one-dimensional one other than the two-dimensional CCD. In other words, the photodiodes may be arranged in a line, and the signal charges thereof may be transferred to the HCCD in parallel and serially output. The present invention can be widely used as a CCD type solid-state imaging device.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an amplification MOSFET that receives the voltage signal of the detection capacitor that converts the signal charge transferred from the CCD transfer path into a voltage signal, and this amplification MOSF.
In a preamplifier equipped with a first-stage source follower circuit composed of a load MOSFET provided on the source side of ET and at least one source follower circuit for amplifying by receiving an output signal of the first-stage source follower circuit, a load of the source follower circuit is provided. Amplifying MOS of the source follower circuit is provided by providing self-biasing resistance means at the source of the MOSFET and negatively feeding back the common source voltage to the gate of the load MOSFET via the feedback amplifier.
The conductance of the load MOSFET is complementarily changed with respect to that of the FET, and positive feedback is applied to increase the signal amplitude.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an FDA according to the present invention.

2 is a circuit diagram showing an embodiment of a feedback amplifier used in the FDA of FIG.

FIG. 3 is a schematic circuit configuration diagram showing an embodiment of a CCD type solid-state image pickup device to which the present invention is applied.

[Description of Reference Signs] Q1 to Q16 ... MOSFET, CS ... Detection capacitor, RS ... Self-biasing resistor, AMP ... Feedback amplifier,
VCCD ... Vertical CCD, HCCD ... Horizontal CCD, PG ...
Photogate, OG ... Output gate, RG ... Reset gate, RD ... Reset drain, PA ... Preamplifier (FD)
A), D1 to D4 ... Photodiodes.

Claims (3)

[Claims] 1. A first stage including a detection capacitor for converting a signal charge transferred from a CCD transfer path into a voltage signal, an amplification MOSFET for receiving the voltage signal, and a load MOSFET provided on the source side of the amplification MOSFET. A source follower circuit, at least one source follower circuit that receives and amplifies an output signal of the first-stage source follower circuit, and a load MOSFE of the source follower circuit.
And a feedback amplifier for receiving a common source voltage of the load MOSFET and commonly performing negative feedback to the gate of the load MOSFET. CCD solid-state image sensor. 2. A load MOS of each of the source follower circuits
FET and source follower amplification MOSFET in the second and subsequent stages
Is a depletion type MOSFET, and the CCD type solid-state image pickup device according to claim 1. 3. The CCD transfer path comprises a plurality of vertical CCDs, which receive the signal charges of a plurality of vertically arranged photodiodes of the photodiodes arranged two-dimensionally, and transfer from the plurality of vertical CCDs. Horizontal C that receives the signal charges to be transferred in parallel and transfers them serially
The CCD type solid-state image pickup device according to claim 1 or 2, which comprises a CD.