JPH0519159B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a screen superimposition device that superimposes a plurality of screen signals stored in a plurality of screen memories by setting priorities.

Prior Art and its Problems Conventionally, in order to display superimposed screens on a display device such as a CRT display device, a screen superimposition device has been used in the previous stage.

Figure 1 is a conceptual diagram for explaining the principle of superimposing screens. Screen A consists of a red (R) circle drawn in a transparent (T) background, and When overlapping screen B, which consists of a rectangle of blue (B), if you simply overlap them, the overlapping portion of R and B will become magenta (M) due to additive color mixing, as shown in Figure C'. becomes. However, in cases where screen A is a portrait of a person and screen B is a distant view that should serve as the background, it may be desirable to give priority to screen A and superimpose the images, as shown in FIG.

FIG. 2 is a block diagram of a conventional device for performing the above-mentioned preferential superimposition, illustrating a case where three screens are superimposed. 1 to 3 are screen memories that store each of the three screens to be superimposed; 11 to 13 are bus drivers; 14 to 16
1 is a data bus, 17 is a bus selector, 18 is a priority determination circuit, and 20 is a data bus connected to a video signal generation circuit. Screen signals outputted from the screen memories 1 to 3 to the corresponding data buses 14 to 16 via the corresponding bus drivers 11 to 13 are coupled to a bus selector 17 and a priority determination circuit 18. The priority determination circuit 18 selects a data bus to be connected to the data bus 20 according to the priority of the screen signal on each data bus and whether or not the screen signal is transparent.
The bus selection signal is sent to the bus selector 1 via the signal line 19.
Output to 7. Assuming that screen signals are prioritized in the order of screen memories 1, 2, and 3,
The priority determination circuit 18 selects the data buses 14 to 16 according to the following rules. When the output of the screen memory 1 is not transparent, the data bus 14 is unconditionally selected. When the output of screen memory 1 is transparent and the output of screen memory 2 is not transparent, data bus 15 is selected. Data bus 16 is selected only if the outputs of screen memories 1 and 2 are transparent.

In the conventional example described above, a data bus corresponding to the number of screen memories is required, resulting in a problem that the data bus portion becomes complicated and expensive. This causes problems in that the number of screens that can be superimposed and the number of display colors (the number of signal lines per data bus) are limited.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a screen superimposition device in which the data bus portion is simplified and the cost is reduced.

Summary of the Invention The present invention, which achieves the above object, includes an output prohibition circuit and an output control circuit provided in each screen memory, and a common data bus through which read data from each screen memory is outputted via the output prohibition circuit. , and a plurality of prohibition signal lines for prohibiting output of read data to the common data bus,
Each output control circuit has a priority setting register that sets the priority, and if the read data from the screen memory is not transparent, outputs a prohibition signal based on the setting value of the priority setting register to the prohibition signal line. a first gate means that inputs the setting value of the own priority setting register and the prohibition signal of the prohibition signal line, and outputs a prohibition signal to the prohibition signal line according to the setting value of the own priority setting register; a second gate that instructs the output prohibition circuit to output the read data to the common data bus if the read data from the screen memory is higher than the priority setting register setting value of the image memory; and means.

Hereinafter, the present invention will be explained in further detail with reference to Examples.

Embodiment of the Invention FIG. 3 is a block diagram of an embodiment of the invention. In the figure, only two screen memories are shown, and a third system of screen memory as shown in FIG. 2 is not shown here. In this figure, the same reference numerals as in FIG. 2 denote the same components as already explained in connection with FIG.

100 and 200 are output control circuits added to each screen memory 1 and 2, 109 and 209 are output inhibit circuits, 21 is a common data bus, and 22 and 23 are inhibit signal lines. The red (R), green (G), blue (B), and black (BL) signals of each screen memory are transferred to the corresponding signal lines R, G, B of the common bus 21 via the corresponding output prohibition circuit and bus driver. Combined with BL.

Furthermore, the output control circuits 100 and 200 associated with the screen memories 1 and 2 have the same negative logic configuration. The output control circuits 100 and 200 are 3-input AND gates 101, 106, 201, 206, inverters 102, 202, and 2-input NAND gates 10.
3,104,203,204, Noah Gate 10
5,205, 2-input AND gate 107,20
7. Consists of priority setting registers 108 and 208. In this embodiment, the priority setting register 10 is set so that the screen memory 1 has the highest priority and the screen memory 2 has the second priority.
8,208 is α ₁ = “0”, β ₁ = “1”, α ₂ = “1”
”,
β ₂ =“0”. When setting the priority of screen memory 2 to the lowest, α ₂
= “0” and β ₂ = “0”. By setting the priority setting registers 108 and 208, the priority of overlapping each screen memory can be dynamically changed.

In the output control circuit 100 attached to the screen memory 1 having the highest priority, since α ₁ is "0", the output of the two-input NAND gate 103 is always "1" regardless of the output of the inverter 102. If the read data of the own screen memory 1 is not transparent, that is, if any of R, G, and B is not "0", the output of the inverter 102 becomes "1" because β ₁ is "1". In response to this, the output of the two-input NAND gate 104 becomes "0", and a prohibition signal is output to the prohibition signal line 22. Also, 2
Input NAND gate 107, 3 input AND gate 1
Since β ₁ is "1", the output of 06 becomes "0" regardless of other inputs. Therefore, if any of R, G, and B is not "0", the output of NOR gate 1
The output of 05 becomes “1” and the output prohibition circuit 109
The output of the screen memory 1 is transferred to the common data bus 21.
is combined with

On the other hand, in the output control circuit 200 attached to the screen memory 2 having the second highest priority,
Since β ₂ is "0", the output of the two-input NAND gate 204 is always "1" regardless of the output of the inverter 202, but any one of R, G, and B in its own screen memory 2 is "0". If not, then
Since α ₂ is “1”, the output of the inverter 202 becomes “1”, and the output of the two-input NAND gate 203 becomes “0”, and the inhibition signal line 23
A prohibition signal is output. Furthermore, since α ₂ is “1”, the output of the 3-input AND gate 206 is “0” regardless of other inputs, but since β ₂ is “0”, the output of the 2-input AND gate 206 is “0”.
The output of 7 becomes "0" only when the prohibition signal "0" is not output to the prohibition signal line 22. Therefore, if any of R, G, and B in the own screen memory 2 is not "0" and the prohibition signal "0" is not output to the prohibition signal line 22, the output of the NOR gate 205 is "1". ” output prohibition circuit 20
9, the output of screen memory 2 is connected to common data bus 2.
1. However, in this embodiment, if any of R, G, and B of the screen memory 1 having the highest priority is not "0", the output control circuit 100 attached to the screen memory 1
2, the output of the screen memory 22 is not coupled to the common data bus 21. This realizes overlapping of the outputs of screen memories 1 and 2.

Note that when the screen memory 3 (not shown) is set to the lowest priority, the output of the screen memory 3 will be the inhibition signal when all of R, G, and B of the screen memories 1 and 2 are "0". The lines 22 and 23 are coupled to the common data bus 21 only when the inhibition signal "0" is not output.

In the above embodiment, three screen memories are overlapped, but the number of overlaps is not limited to three; if the prohibition signal line and priority setting register are made larger in advance, Of course, the number of overlapping can be increased accordingly.

The screen memory, output control circuit, output inhibition circuit, and bus driver can usually be mounted on one card, and connectors corresponding to the maximum number of screen memories can be connected to the common data bus 21 and inhibition signal lines 22 and 23. If provided in advance, the screen memory can be easily expanded by inserting a card into the connector and changing the setting of the priority setting register of the output control circuit associated with the existing screen memory.

Effects of the Invention As explained above, in the present invention, each screen memory determines whether or not its own output is transparent and whether or not it receives a prohibition signal from another screen memory with a higher priority than itself. The output control circuit that controls output to the common data bus has a common configuration for each screen memory, and the priority can be changed arbitrarily using the priority setting register, making it easy to expand the screen memory. It has the advantage of being able to

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram illustrating preferential overlapping of screens, FIG. 2 is a block diagram of a conventional device, and FIG. 3 is a block diagram of an embodiment of the present invention. 1 to 3... Screen memory, 100, 200...
Output control circuit, 109, 209...Output prohibition circuit, 11 to 13...Bus driver, 21...Common data bus, 22, 23...Prohibition signal line.

Claims (1)

[Claims] 1. In a screen superimposition device that superimposes a plurality of screen signals stored in a plurality of screen memories with priority, an output prohibition circuit and an output control circuit provided in each screen memory, respectively. , a common data bus through which read data from each screen memory is output via the output inhibit circuit, and a plurality of inhibit signal lines for inhibiting output of read data to the common data bus, Each output control circuit includes a priority setting register for setting the priority, and outputs a prohibition signal based on the setting value of the priority setting register to the prohibition signal line if the read data from the screen memory is not transparent. First thing to do
a gate means; a screen memory which inputs the setting value of the own priority setting register and the prohibition signal of the prohibition signal line, and outputs the prohibition signal to the prohibition signal line according to the setting value of the own priority setting register; a second gate means for instructing the output prohibition circuit to output the read data to the common data bus if the read data from the screen memory is higher than the setting value of the priority setting register of the second gate; A screen overlapping device characterized by comprising: