GB2176677A

GB2176677A - Combining image signals

Info

Publication number: GB2176677A
Application number: GB08612867A
Authority: GB
Inventors: Kazuo Yoshioka
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1985-05-27
Filing date: 1986-05-27
Publication date: 1986-12-31
Also published as: JPS61270786A; JPH0443589B2; GB8612867D0; GB2176677B; CA1257024A

Abstract

Image signals are combined to produce a composite image in which images of higher priority overlay images of lower priority, the order of priority of the images being controllable. Image signals relating to images A, B, C together with associated stencil signals which indicate the area in which the image is to be displayed - see A, B, C in figures 3a and 3b are stored in image memories 11a, b, c. The signals are read via priority setting circuit 12 which passes the image signals to data selecting circuit 14 and arranges them in a predetermined order of priority, as a result of which they are displayed as in figure 3a. The stencil signals pass to priority rearranging circuit 13 where the order of priority may be changed. A control signal on line 23b may cause image B to be suppressed as in figure 3b. <IMAGE>

Description

SPECIFICATION Image signal transmitting system BACI(GROUND OF THE INVENTION Fieldofthe Invention The present invention relates to an image signal transmitting system for giving information, such as letters and graphic patterns produced by a CPU, to a display such as a CRT and, more specifically, to an imagesignaltransmittingsystem capable of giving imagesignalstoadisplaysothat images are displayed in a plurality of separate display divisions in the display screen of a display.

Description ofthe PriorArt An image signal transmitting system which provides image signals to be displayed in a plurality of separate display divisions in the display screen of a display is disclosed, for example, in Unexamined Patent Publication (Kokai) No. 58-35592. Fig. 4 is a block diagram of such an image signal transmitting system. Referring to Fig. 4, there are shown image memories 1a, 1 and 1c, a vertical division assigning register 2, a horizontal division assigning register 3, a vertical scanning position counter 4, a horizontal scanning position counter 5, a vertical position detecting circuit 6, a horizontal position detecting circuit 7 and a selecting circuit 8.

In this image signal transmitting system, the vertical position detecting circuit 6 compares the output signal of the vertical scanning position counter 4 and the output signal ofthe vertical division assigning register 2to detectthevertical position of a display division in the display screen, while the horizontal position detecting circuit7 compares the output signal of the horizontalscanningcounter5andtheoutputsignal of the horizontal division assigning register3to detect the horizontal position of the display division on the display screen. Then, the selecting circuit 8 selects one ofthe image memories 1a, 1 b and 1c according to the detection signals of the vertical and horizontal position detecting circuits 6 and 7, and then providesthe image signal of the selected image memory.

The conventional image signal transmitting system divides the display screen in the above-mentioned manner by means ofthe division assigning registers 2 and 3, the scanning position counters 4and 5, and the position detecting circuits 6 and 7. When a display screen dividing pattern is required to be changed, the contents of the division assigning registers 2 and 3 must be rewritten. Accordingly, it has been impossible to change an existing divisional pattern shown on the display screen for a new one without manipulating the data of the existing divisional pattern displayed on the screen.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image signal transmitting system capable of easily changing an existing divisional pattern for a new one without manipulating the data of the images of the existing divisional pattern.

According to the principle of the present invention, each one ofthe image data read from a plurality of image memories is given to a display according to a priority given to a data effectiveness signal corresponding to the image data. Although each image memory has a preset priority, the preset priorities are rearranged by a priority rearranging circuit according to external instructions.

An image signal transmitting system, in a preferred embodiment, according to the present invention for feeding image data of images to be displayed to a display to display a plurality of images including letters and/or graphic patterns on the display comprises: a plurality of image memories storing different image data and the corresponding data effectiveness signals, respectively; a priority setting circuit for assigning predetermined priorities to an image data read from the corresponding image memory and to the corresponding data effectiveness signal, respectively; a priority rearranging circuit which receives the data effectiveness signals from the priority setting circuit and rearranges the priorities of the data effectiveness signals according to external gate signals; and a data selecting circuit which selects one of the image data and gives the selected image data to the display according to the data effectiveness signal indicating the priority rearranged by the priority rearranging circuit.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an image signal transmitting system according to the present invention; Figure 2 is a logical circuit diagram showing the details of a priority rearranging circuit and a data selecting circuit employed in the image signal transmitting system of Fig.1; Figures 3a and 3b are diagrammatic illustrations of exemplary patterns formed by the image signal transmitting system ofthe present invention on a display screen; and Figure 4 is a block diagram of a conventional image signal transmitting system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Fig. 1, an image signal transmitting system according to the present invention comprises, to simplify the description,three image memories 1 la, 1 1 b and 1 Ic. However, the number of the image memories may be an optional number not less than two.

A priority setting circuit 12 is connected to the image memories 11 a, 11 band 1 icto receive image data 21a, 21 band 21 c, and data effectiveness signals 22a, 22b and 22e from the image memories 1 1 a, 1 1 b a nd lic, respectively. The priority setting circuit 12 assigns predetermined priorities to the image data and the corresponding data effectiveness signals, respectively. The priority setting circuit 12 gives image data 51 a, 51b and 51coo a data selecting circuit 14, and gives data effectiveness signals 52a, 52b and 52c each having a priority to a priority rearranging circuit 13.

The priority rearranging circuit 13 has three gates which are conrolled by external gate signals 23a, 23b and 23c. One ofthe three data effectiveness signals 52a, 52b and 52c given to the priority rearranging circuit 13 allowed to pass the gate is fed to a data selecting circuit 14 to specifythe data among the three image data 51 a, 51 b and 51 c to be selected by the data selecting circuit 14.

Fig. 2 illustrates the details ofthe priority rearranging circuit 13 and the data selecting circuit 14. The priority rearranging circuit 13 includes three AND gates 41,42 and 43 which are controlled by gate signals 23a, 23b and 23c, respectively. The data effectiveness signals 52a, 52b and 52c are given to the AND gates 41,42 and 43, respectively. The data selecting circuit l4comprisesAND gates 31,32 and 33,an OR gate 34,AND gates 35 and 36 and inverters 37and38.

Thefirst, second and third priorities are assigned to the image data 51a, 51b and 51c, orthe image data 51 a, 51 and 51 c havethefirst, second and third priorities, respectively, and the first, second and third priorities are assigned to the data effectiveness signals 52a, 52b and 52c.At this stage, the image data 51 a, Sib and Sic and the data effectiveness signals 52a, 52b and 52c are not regarded as those stored in the image memories 1 la, 11 and 11 c, respectively, and hence the image data 51 a, 51 band Sic and the data effectiveness signals 52a, 52b and 52c are treated on a conception that the image data 51 a, Sib and 51 c and the data effectiveness signals are data having the first, second and third priorities and the corresponding data effectiveness signals, respectively.

Figs. 3a and 3b show an exemplary pattern including divisional imagesdisplayedonadisplayscreen by the image signal transmitting systemofthe present invention.

In Fig. 3a, it is assumed that images A, B and C correspond to image memories 11 a, 11 and 11 C, respectively. The truth-value ofthe data effectiveness signal 22a ofthe image memory 1 lea is "1" onlywithin the region ofthe image A, the truth-value ofthe data effectiveness signal 22b ofthe image memory 11 b is "1" only within the region ofthe image B including a portion overlapping the region of the image A, and the truth-value ofthe data effectiveness signal 22c of the image memory 1 is "1 " within the region ofthe image C, namely, the entire region.

The priorities ofthe data effectiveness signals 22a, 22b and 22c of the image memories 1 la, 1 1 band lic are decided by the priority setting circuit 12 under the control of a CPU, nowshown, orthe like. In the case shown in Fig. 3a, the imageA > the image B > the image C in priority. Therefore, the highest priority, the secondary priority and the lowest priority are given to the data effectiveness signals 22a of the image memory 1 la, 22b of the image memory 11 band 22c of the image memory 11 c, respectively. In this state, when the divisional images are displayed in a pattern 3A as shown in Fig. 3a, the values of the gate signals 23a, 23b and 23c are "1".When the pattern 3A is required to be changed for a pattern 3B shown in Fig.

3b, the gate signals 23a, 23b and 23c corresponding to the images A, B and Care set at "1", "0" and "1", respectively. This gate signal setting operation willie described more specifically with reference to Fig. 2.

With particular reference to lines land m shown in Figs. 3a and 3b, in the pattern 3A, onlythe data effectiveness signal 52c of the lowest priority is "1 " in sections [a, b ] and [ e,f ] ,whilethe data effectiveness signals 52a and 52b of the hig hest and the secondary priorities are "0", and all the gate signals 23a, 23b and 23c are "1 ". Therefore, the outputs ofthe AND gates 41 and 42 are "0", while the output of the AND gate 43 is "1 ". Accordingly, the outputs ofthe inverters 37 and 38 are"1",the outputoftheAND gate 35 is "0", and the output ofthe AND gate 36 is "1".Consequently, only the AND gate 33 among the AND gates 31, 32 and 33 is open, and hence the image data Sic of the lowest priority that passed the AND gate 33, namely, the image data 21 c of the image memory 11 c, appears at the output ofthe OR gate 34.

In a section [b, c ] , the data effectiveness signal 52b of the secondary priority and the data effective signal 52c ofthe lowest priority are "1 ", while the data effective signal 52a ofthe highest priority is "0". Since all the gate signals 23a,23band 23c are "1".theAND gate 41 is "0" and the AND gates 42 and 43 are "1 ".

Accordingly, the output of the inverter 37 is "1", the output ofthe inverter 38 is "0", the output of the AND gate 35 is "1" and the output of the AND gate 36 is "0".

Consequently, only the AND gate 32 among the AND gates 31,32 and 33 is open, and hence the image data Sib of the secondary prioritythat passed the AND gate 32, namely, the image data 21 b ofthe image memory 11 b, appears at the output ofthe OR gate 34.

In a section [c, d ] , all the data effectiveness signals 52a, 52b and 52c are "1" and all the gate signals 23a, 23b and 23calso are "1 ".Therefore,allthe outputs of theAND gates 41,42 and 43 are "1". Accordingly, the outputs of both the inverters 37 and 38 are"0".

Consequently, only the AND gate 31 among the AND gates 31,32 and 33 is open, and hence the image data 51a of the highest priority that passed the AND gate 31, namely, the image data 21 a of the image memory 11 a, appears at the output of the OR gate 34.

in a section [d, e ] , the data effectiveness signal 52a ofthe highest priority and the data effectiveness signal 52c of the lowest priority are "1", while the data effectiveness signal 52b ofthe secondary priority is "0". Since all the gate signals 23a, 23b and 23c are "1 ", the outputs ofthe AND gates 41 and 43 are "1 " and the AND gate 42 is "0". Accordingly, the output ofthe inverter 37 is "0", the output ofthe inverter 38 is "1" and the outputs of the AND gates 35 and 36 are "0".

Consequently, only the AND gate 31 among the AND gates 31,32 and 33 is open,the hence the image data 51 a ofthe highest priority that passed the AND gate 31, namely, the image data 21a ofthe image memory 11 a, appears atthe output of the OR gate 34.

Thus, the image data of the image memory 11 c, the image memory lib and the image memory 1 la are displayed in the sections [a, bland [ e, fi, in the section [ b, c ] and in the section [c, e ] , respectively. Conse quently,the divisional pattern 3A is displayed on the display screen.

The pattern shown in Fig. 3b will be described hereinafter.

In sections [g, h ] and [k, p], only the data effective ness signal 52c of the lowest priority is "1" and the rest are 0". Sincethe gate signals 23a and 23care "1" and the gate signal 23b is "0", the AND gates 41 and 42 are "0" and the AND gate 43 is "1 ".Accordingly, the outputs of the inverters 37 and 38 are "1 ", the output oftheAND gate 35 is "0" and the outputoftheAND gate 36 is "1". Consequently, onlytheAND gate 33 among the AND gates 31,32 and 33 is open, and hence the image data 51 c of the lowest priority that passed theANDgate33,namely,theimagedata 21 c ofthe image memory 1 1 c, appears atthe output of the OR gate 34.

In a section [h, i ] , the data effectiveness signal 52b of the secondary priority and the data effectiveness signal 52c ofthe lowest priority are "1" and the data effectiveness signal 52a ofthe highest priority is "0".

Furthermore, since the gate signals 23a and 23c are "1" " and the gate signal 23b is "0", the AND gates 41 and42are"0"andtheANDgate43is"i".

Accordingly, the outputs of the inverters 37 and 38 are "1 ",the outputoftheANDgate 35 is "0" and the output of the AN D gate 36 is "1". Consequently, only theAND gate 33 among the AND gates 31,32 and 33 is open, and hence the image data 51 c of the lowest priority that passed the AND gate 33, namely, the image data 21 cof the image memory 1 it, appears at the output of the OR gate 34.

In a section [i, j ] , all the data effectiveness signals 52a, 52b and 52c are "1", the gate signals 23a and 23c are "1 " and the gate signal 23b is "0", hencethe AND gates 41 and 43 are "1 " and the AND gate 42 is "0".

Accordingly, the output of the inverter 37 is "0", the output ofthe inverter 38 is "1" and the outputs of both the AND gates 35 and 36 are "0". Consequently, only the AND gate 31 among the AND gates 31,32 and 33 is open, and hence the image date 51 a ofthe highest priority that passed the AND gate 31, namely, the image data 21 a of the image memory 11 a appears at the output of the OR gate 34.

In a section [ j, k ] , the data effectiveness signal 52a of the highest priority and the data effectiveness signal 52c of the lowest priority are "1 " and the date effectiveness signal 52b of the secondary priority is "0". Since the gate signals 23a and 23c are "1" and the gatesignal23bis"0",theANDgates4l and 43 are "1" and the AND gate 42 is "0". Accordingly, the output of the inverter37 is "0", the outputofthe inverter38 is "1", and the outputs of the AND gates 35 and 36 are "0".Consequently, only the AND gate 32 among the AND gates 31,32 and 33 is open, and hence the image data 51 a ofthe highest priority that passed the AND gate 31, namely, the image date 21a of the image memory ii a, appears at the output ofthe OR gate 34.

Thus, in the sections [ g, i ] and [k, p ] and in the section [i, k ] ,the image data 21 c of the image memory 1 1c and the image data 21a ofthe image memory 11a are displayed. Consequently, the divisional pattern 3B shown in Fig. 3B is displayed on the display screen.

As has been described hereinbefore, the divisional pattern 3A can be changed for the divisional pattern 3B only by setting thetruth-valueofthe gate signal 23b at "0" without requiring the chance of priority.

Accordingly, the display pattern can be changed from the divisional pattern 3B to the divisional pattern 3A simply by setting the truth-value of the gate signal 23b at"1".

The embodiment as provided with three image memories has been described hereinbefore, however, the number of the image memories need not necessarily be limited to three. Furthermore, the circuit constitution shown in Fig. 2 is for example only and is not limited thereto. The image data itself may be used as the data effectiveness signal. When the image data is used as the data effectiveness signal, an image consisting of a plurality of images superimposed over another is displayed on the display screen.

The superimposition of images may be easily understood when considered with reference to the display of letters over a background picture. As is apparent from the foregoing description, in the embodiment, the data effectiveness signal is explained as representing a rectangular shape. In this case, the actual display is a window shape as shown in Fig. 3.When the data effectiveness signal represents the same shape as that represented by the image data, for example, when the image data is a letter data and the data effectiveness signal represents the same shape as that represented by the letter data, the shape represented by the data effectiveness signal is can be most efficiently displayed by using the image data as the data effectiveness signal, and thereby the output data is changed according to the shape of the letter, a portion of the background picture corresponding to the letter is erased to display the lettertherein,which is called generally as superimposition.

As apparent from the foregoing description, according to the present invention, data effectiveness signals are provided by image memories, respectively, and priorities are given to the data effectiveness signals to use the data effectiveness signals as data selecting signals; and the transmission of the data effectiveness signals is controlled by gate signals independent of priority setting. Accordingly, the divisional pattern displayed on a display screen can be easily changed without manipulating the priority setting.

Claims

1. An image signal transmitting system for feeding image data corresponding to a plurality of images including lettersand/orgraphicpatternstodisplaya divisional pattern on a display, which comprises: a plurality of image memories storing different image data and the corresponding data effectiveness signals, respectively.

a priority setting ci rcu it for assigning predetermined priorities to an image data read from the corresponding image memory and to the corresponding data effectiveness signal, respectively; a priority rearranging circuit which receives the data effectiveness signals from the priority setting circuit and rearranges the priorities of the data effectiveness signals according to external gate signals; and a data selecting circuit which selects one ofthe image data and gives the selected image data to the display according to the data effective signal indicating the priority rearranged by the priority rearranging circuit.

2. An image signal transmitting system according to Claim 1, wherein said priority rearranging circuit comprises AND gates, the data effectiveness signal provided by said priority setting circuit and said gate signal are applied to the first and second input terminals of each one oftheAND gates, respectively.

3. An image signal transmitting system according to Claim 2, wherein said data selecting circuit comprisesfirst gate means for gating the image data; and second gate meansforcontrolling thefirst gate means according to the data effectiveness signals indicating the rearranged priorities so thatthefirst gate means allow the image data of the highest priority to pass therethrough.