JPH05191234A - Timing control circuit - Google Patents

Abstract

PURPOSE:To provide a function to adjust a delay of a signal delay circuit implementing timing control with respect to the timing control circuit used for a phase locked loop(PLL). CONSTITUTION:Plural delay circuit elements 10 connected in series able to control a delay are used for a signal delay circuit 30, and delay control signals 20 of each delay circuit element 10 are added in common to revise the delay of all the delay circuit elements 10 simultaneously. Then a delay control signal 20 is controlled by the combination of a selection circuit 40, a bidirectinal shift register circuit 50, a phase detection circuit 120, shift control circuit 124 and a delay control circuit 60 to select a desired delay thereby realizing a broad band timing control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device having a timing control circuit for delaying an input digital signal under a certain control for a predetermined time and outputting the same, and more particularly to a phase locked loop (PLL) and The present invention also relates to a timing control circuit used when dynamically controlling the delay of a signal.

[0002]

2. Description of the Related Art In a microprocessor having an operating frequency exceeding 40 MHz and its peripheral systems, a clock synchronous wide band bus interface is required to obtain high performance. Especially, the bus clock is 2
When it becomes 5 ns or less, even if each functional device (especially integrated circuit) operates in synchronization with the bus clock, the existence of skew between the internal clock of the functional device and the bus clock is ignored with respect to the bus clock. This makes it difficult to speed up access to the memory subsystem (in particular, to secure setup time and hold time).

An example of the influence of the existence of the skew between the internal clock of the functional device and the bus clock on the setup time and the hold time will be described below with reference to the drawings.

FIG. 11 shows the relationship between the read data from the memory subsystem synchronized with the bus clock and the internal clock of the functional device. Here, it is assumed that all the timings are specified with respect to the rising edge of the bus clock. Further, the setup time of read data with respect to the rise of the bus clock is d1, and the hold time is d2. Furthermore, the read data is
It shall be sampled at the rising edge of the internal clock.

As shown in FIG. 11A, when the internal clock is delayed by the time d with respect to the bus clock, the hold time with respect to the rise of the internal clock becomes d2-d, and if this value deviates from the standard of the functional device, The read data cannot be sampled correctly in the functional device. Such a situation occurs in a functional device that operates by generating an internal clock from a bus clock. In general, the minimum hold time is often defined as 0 ns, and depending on the load of the internal clock, if d = 3-5 ns, the hold time for the bus clock is at least 3-5 ns. You need some degree.

As shown in FIG. 11B, when the bus clock is delayed by the time d with respect to the internal clock, the setup time for the rising edge of the internal clock is d1.
-D, and if this value deviates from the standard of the functional device, the read data cannot be correctly sampled in the functional device. Such a situation occurs in the functional device that generates and supplies the bus clock from the internal clock. Generally, it is said that the maximum setup time is preferably about 3 ns, and if d = 5 to 10 ns, the setup time for the bus clock is at least 5 to 1 depending on the size of the load on the bus.
About 0 ns is required.

Therefore, it is necessary to give a margin to the setup time d1 and the hold time d2 of the read data with respect to the rise of the bus clock in consideration of the time difference d of the internal clock with respect to the bus clock.
This makes it difficult to speed up access to the memory subsystem.

Therefore, in order to make these clock skews as small as possible to obtain high performance, the timing control circuit is used to control the phase for the purpose of minimizing the skew between the internal clock of the functional device and the bus clock. Phase locked loop (PLL)
Is used.

A phase locked loop (PL) for controlling a phase using a timing control circuit will be described below with reference to the drawings.
A conventional example of L) will be described.

FIG. 12 shows a conventional example of a phase locked loop (PLL) which controls a phase using a timing control circuit. In FIG. 12, the signal delay circuit 30 is composed of a plurality of delay circuit elements connected in series. The clock signal 32 is used as an input signal, and a signal obtained by delaying the clock signal 32 is delayed from the output of each delay circuit element. The signal 34 is output. These delayed clock signals 34
Is selected by the selection circuit 40 and supplied to the internal clock generation circuit 110. The bus control circuit 112 generates the internal bus clock 114 by the internal clock 48 generated by the internal clock generation circuit 110. The bus clock 116 is a clock having a cycle twice that of the clock signal 32, is input to the phase detection circuit 120 together with the internal bus clock 114, and generates the phase control signal 122 according to the phase difference. Phase control signal 122
Are input to the shift control circuit 124, the shift control circuit 124 controls the shift operation of the bidirectional shift register circuit 50, and the bidirectional shift register circuit 50 causes the selection circuit 4 to operate.
Control 0.

The signal delay circuit 30, the selection circuit 40, the bidirectional shift register circuit 50, and the bus control circuit 112.
, Internal clock generation circuit 110, and phase detection circuit 12
0 and the shift control circuit 124 have a phase locked loop (PL
L). The phase detection circuit 120 generates a phase control signal 122 according to the phase difference between the internal bus clock 114 and the bus clock 116. The shift control circuit 124 shifts the set bit of the bidirectional shift register circuit 50 using the phase control signal 122. The set bits are
It resides in only one register in the bidirectional shift register circuit 50, all others are reset bits. The set bit and the reset bit serve as control signals for the selection circuit 40,
The delayed clock signal 34 of the signal delay circuit 30 corresponding to the set bit is selected. The delayed clock signal 34 of the signal delay circuit 30 corresponding to the reset bit is not selected.
In this way, the delay amount of the clock signal 32 is selected so that the phase difference of the internal bus clock 114 with respect to the bus clock 116 is minimized. For example, bus clock 11
When the internal bus clock 114 is delayed with respect to 6, the delay clock signal 34 having a small delay amount is selected by using the selection circuit 40 and the bidirectional shift register circuit 50 to advance the internal bus clock 114. On the other hand, the bus clock 11
When the internal bus clock 114 is ahead of 6, the delayed clock signal 34 having a large delay amount is selected using the selection circuit 40 and the bidirectional shift register circuit 50 to delay the internal bus clock 114.

As described above, the internal bus clock 114 is controlled to be in phase with the bus clock 116 to minimize the skew between the clocks. One implementation example of such a phase locked loop (PLL) is "The 68040 32-b MonolithicProcessor (IEEE Journ
al of Solid-State Circuits, Vol.25, No.5, Oct.1990, p1178-11
80) ”.

[0013]

However, the above-mentioned structure has the following problems.

(1) Since the delay amount of each delay circuit element that constitutes the signal delay circuit 30 is constant, it is difficult to change the range and accuracy of phase control. In order to solve this problem, it is easily inferred that the delay amount of the delay circuit elements forming the signal delay circuit 30 can be varied and the phase range and accuracy thereof can be changed depending on the situation of phase control. However, the range and accuracy of phase control cannot be easily changed unless a means for accurately grasping the state of phase control is realized.

(2) There is no means for knowing whether the delay amount required for phase synchronization is within the delay amount range controllable by the signal delay circuit 30.

(3) Two types of clock signals (bus clock and clock having twice the frequency thereof) are used to facilitate phase synchronization, but when only the bus clock can be used (bus clock itself If the frequency of is sufficiently high and it is difficult to use a clock having twice that frequency, it is necessary to delay the phase of the bus clock by 360 ° (180 ° when the logic is inverted by the logic inversion circuit). In order to cope with a wide frequency range, the signal delay circuit 30 alone cannot provide control because the amount of delay is insufficient.

In view of the above problems, the present invention forms a delay control signal, a warning signal, and a delay line selection control signal by detecting the position of a set bit in a bidirectional shift register to form a signal delay circuit. (EN) A timing control circuit that enables flexible delay control by adjusting the delay amount of each delay circuit element or delaying a signal in advance for a predetermined time before the signal delay circuit.

[0018]

In order to solve the above-mentioned problems, the invention of claim 1 provides a delay circuit element having a plurality of delay values for delaying a given signal for a predetermined time and outputting the delayed signal.
(N ≧ 2, n is an integer) serially connected delay circuits, a selection circuit for selecting and outputting one of the outputs of each of the delay circuit elements, and a signal given to the delay circuit. A phase control circuit that determines the output of the delay circuit element to be selected so that the output signals of the selection circuit have the same phase; and a delay control circuit that controls the delay value of the delay circuit element itself. When the control circuit determines that the delay amount in the entire delay circuit is insufficient for phase synchronization, the delay control circuit changes the delay value of the delay circuit element to set the delay control range in the delay circuit. It is characterized by changing.

According to a second aspect of the present invention, in the timing control circuit according to the first aspect, as the selection circuit, an n-input / single-output selection circuit which receives the output of each delay circuit element is used.
As a phase control circuit, a phase detection circuit that compares the phase of the signal supplied to the delay circuit and the output signal of the selection circuit, and a shift that outputs a shift clock and a shift direction control signal based on the phase difference information from this phase detection circuit A control circuit and an n-bit bidirectional shift register circuit that bidirectionally shifts only one set bit according to the shift clock and the shift direction control signal are used, and the most significant bit of the bidirectional shift register circuit is used as a delay control circuit. An RS latch whose output is a set signal is used. The output value of the RS latch is used to change the delay value of the delay circuit element to change the delay value of the entire delay circuit, and the set bit in the bidirectional shift register circuit is used. Delay to minimize the phase difference between the signal given to the delay circuit and the signal output from the n-input 1-output selection circuit. It is characterized in that for selecting either the output of road elements.

According to a third aspect of the present invention, in the timing control circuit according to the first aspect, as the delay circuit, a plurality of delay lines that delay a given signal by different fixed periods having a common input, and a plurality of these delay lines are provided. A delay line selection circuit that selects one output from the outputs of the delay line and a circuit in which n delay circuit elements having a constant delay value that receive the output signal of this delay line selection circuit are connected in series is used. As the selection circuit, an output signal of the delay line selection circuit and an n + 1-input 1-output selection circuit having the outputs of the delay circuit elements as inputs are used, and as the phase control circuit, a signal given to the delay circuit and an output signal of the selection circuit Detection circuit for comparing the phases of the shift clock, the shift control circuit for outputting the shift clock and the shift direction control signal based on the phase difference information from the phase detection circuit, and the shift clock An n-bit bidirectional shift register circuit that bidirectionally shifts only one set bit according to the shift direction control signal is used, and the set bit in the bidirectional shift register circuit remains at the most significant bit for a certain period as a delay control circuit. The delay value of the entire delay circuit is detected by using the overflow detection circuit that detects this and the delay line selection control circuit that switches the output of the delay line selected by the delay line selection circuit in the delay circuit by the output signal of this overflow detection circuit. It is changed to obtain a delay amount necessary for phase synchronization, and a signal given to the delay circuit by the set bit in the bidirectional shift register circuit and n + 1 input 1
It is characterized in that any one of the outputs of the delay circuit elements is selected so that the phase difference between the signals output by the output selection circuit is minimized.

According to a fourth aspect of the present invention, in the timing control circuit according to the first aspect, as the delay circuit, a first delay circuit element for delaying a given signal for a predetermined time and outputting the delayed signal is connected in series. And the second delay circuit are connected in series and the m-th (1 ≦ m ≦ n, m) of the first delay circuit is connected.
An integer) delay circuit element output or an output of the m-th delay circuit element of the second delay circuit is selected, and a selection circuit using n 2-input 1-output selection circuit elements is used. , A phase detection circuit for comparing the phase of the signal given to the delay circuit with the phase of the output signal of the selection circuit, using an n-input 1-output selection circuit having the output of each of the selection circuit elements as an input, and this phase A shift control circuit that outputs a shift clock and a shift direction control signal based on phase difference information from the detection circuit, and an n-bit bidirectional shift register that bidirectionally shifts only one set bit according to the shift clock and the shift direction control signal. Circuit, and an RS latch using the output of the most significant bit in the bidirectional shift register circuit as a set signal is used as a delay control circuit. The output signal of the switching circuit switches the delay circuit selected by the selection circuit element in the delay circuit, and the position of the signal provided to the delay circuit by the set bit in the bidirectional shift register circuit and the signal output by the n-input 1-output selection circuit. The output of any one of the selection circuit elements in the delay circuit is selected so that the phase difference is minimized.

According to a fifth aspect of the present invention, a delay formed by connecting n delay circuit elements (n ≧ 2, n is an integer) in series having a plurality of delay values for delaying a given signal by a certain time and outputting the delayed signal is output. A circuit, an n-bit delay control register for selecting a specific delay value for each delay circuit element, an n-input 1-output selection circuit for receiving the output of each delay circuit element, and a bidirectional set bit It is characterized in that it comprises an n-bit bidirectional shift register circuit for shifting to n, and the selection operation of the n input 1 output selection circuit is controlled by a set bit in the bidirectional shift register circuit.

[0023]

According to the first aspect of the present invention, each of the delay control circuit and the phase control circuit has a plurality of delay circuit elements connected in series and capable of controlling the delay amount based on the phase difference information of the phase control circuit. And one of the outputs of each of the delay circuit elements is controlled to control the selection circuit for outputting the delay value of the delay circuit element or the combination thereof for obtaining the delay amount that minimizes the phase difference between the signals. By making changes, timing control can be realized over a wide frequency range.

According to the second aspect of the invention, as the signal delay circuit, a plurality of delay circuit elements capable of controlling the delay amount are connected in series, and the delay control signals of the respective delay circuit elements are commonly connected to all the delay circuits. By allowing the delay values of circuit elements to be changed at the same time and controlling the delay amount of the entire delay circuit by controlling the delay control signal with the combination of the selection circuit, the bidirectional shift register circuit, and the delay control circuit, Timing control can be realized over.

According to the third aspect of the invention, prior to inputting the clock signal to the signal delay circuit whose delay amount can be controlled,
The clock signal is delayed by a plurality of delay lines having different delay amounts in advance, the delayed clock signal is further delayed by the signal delay circuit, and the position information of the set bit in the bidirectional shift register circuit at that time is fed back. Timing control can be realized over a wide frequency range by selecting one of the plurality of delay lines so that the signal delay circuit has a timing controllable range.

According to the fourth aspect of the invention, as the signal delay circuit, two sets of delay circuit elements each having a plurality of delay circuit elements connected in series are connected in series, and the output of the delay circuit elements in the two sets of delay circuits is connected. A mechanism for selecting either of them is provided, and the delay control signal is controlled by the combination of the selection circuit, the bidirectional shift register circuit, and the delay control circuit to switch the two sets of delay circuits, thereby obtaining a desired delay amount and wide range. Timing control can be achieved over the frequency range.

According to the invention of claim 5, a plurality of delay circuit elements capable of controlling the delay amount are connected in series as the signal delay circuit, and each of the signal delay circuits is constituted by the data held in the delay control register. The timing control can be realized over a wide frequency range by independently controlling the delay circuit elements of and the desired delay amount is selected by the combination of the selection circuit and the bidirectional shift register circuit.

[0028]

(Embodiment 1) A timing control circuit according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the timing control circuit according to the first embodiment of the present invention.
Consider the case where eight signal delay circuits 10 (n = 8) are used as 0. Here, in order to simplify the description, it is assumed that the delay circuit element 10 has two kinds of delay values.
It goes without saying that the delay circuit element 10 may have a plurality of (two or more) delay values.

The delay circuit element 10 connects an inverter 12 and an inverter 14 in series, connects the drain of the first N-channel MOS transistor 16 to the output of the inverter 12, and delays the gate of the first N-channel MOS transistor 16 with a delay. Control signal 20 is connected to the first N channel MO
The source of the S transistor 16 is the second N-channel MOS
The second N-channel MOS transistor 18 is connected to the gate of the transistor 18, and the drain and source of the second N-channel MOS transistor 18 are both connected to the ground potential. The signal delay circuit 30 connects eight delay circuit elements 10 in series, supplies a clock signal 32 to the input of the inverter 12 in the first stage delay circuit element 10, and outputs the clock signal 32 to the inverter 14 in each delay circuit element 10. The outputs are first to eighth delayed clock signals 34a to
34h, the delay control signal 20 applied to each delay circuit element 10 is commonly connected. Selection circuit 40
Is composed of an 8-input 1-output select circuit controlled by eight selection control signals 42a to 42h and a buffer circuit 46. The bidirectional shift register circuit 50 includes a reset signal 52, a shift direction control signal 54, and a shift clock 5.
6 is composed of a shift register using eight registers (flip-flops) 58a to 58h controlled by 6 and outputs the values held by the registers 58a to 58h as selection control signals 42a to 42h. Delay control circuit 60
Is an RS that has a set input (S) and a reset input (R)
It is a latch. The phase detection circuit 120 uses the clock signal 3
2 is a circuit having a function of detecting the phase difference between the internal clock 48 and the phase difference signal 1 synchronized with the internal clock 48.
22 is generated. The shift control circuit 124 is a circuit having a function of generating the shift direction control signal 54 and the shift clock 56 based on the phase difference signal 122, and controls the shift operation of the bidirectional shift register circuit 50.

The timing control circuit according to the present embodiment has the signal delay circuit 30, the selection circuit 40, the bidirectional shift register circuit 50, the delay control circuit 60, the phase detection circuit 120, and the shift control circuit 124 configured as described above. Of the delayed clock signals 34a to 34h in the selection circuit 40.
Selection control signals 42a to 42h which are input to the input 1 output select circuit and output from the bidirectional shift register circuit 50.
Is input to the selection circuit 40, the clock signal 32 and the internal clock signal 48 are input to the phase detection circuit 120, the phase difference signal 122 is input to the shift control circuit 124, and the shift direction control signal 54 and the shift clock 56 are bidirectional. Input to shift register 50, reset signal 52 and selection control signal 4
2h is used as the reset input and the set input of the delay control circuit 60, and the output of the delay control circuit 60 is used as the delay control signal 20.

The operation of the timing control circuit of the present embodiment having the above configuration will be described below.

In the delay circuit element 10, the first N-channel MOS transistor 16 serves as a switch circuit which is turned on / off by a signal given to the delay control signal 20, and the second N-channel MOS transistor 18 serves as a capacitive load. .. When the delay control signal 20 becomes the “L” level, the first N-channel MOS transistor 16 is turned off, the capacitive load including the second N-channel MOS transistor 18 is disconnected, and the delay in the delay circuit element 10 is τ0. (= Delay when the first N-channel MOS transistor 16 is off). On the contrary, when the delay selection signal 20 becomes the “H” level, the first N-channel MOS transistor 16 is turned on, the capacitive load including the second N-channel MOS transistor 18 is connected, and the delay circuit element 10 The delay is τ1 (= the delay when the first N-channel MOS transistor 16 is on) (here, τ0 <τ1 is clear). Therefore, the delay control signal 2
By controlling 0 to “L” or “H”, the m-th signal delay circuit 30 (1 ≦ m ≦ n = 8, m is an integer)
Of the output (= any of the delayed clock signals 34a to 34h) can be controlled to two values of m × τ0 or m × τ1.

The selection circuit 40 has a selection control signal 42a-42.
1 from among the delayed clock signals 34a to 34h using h
Select the book signal. In the present embodiment, an eight-input one-output select circuit is configured by using eight N-channel MOS transistors 44, and a select circuit having a configuration of outputting an internal clock 48 after waveform shaping using the buffer circuit 46 is used. ing.

The bidirectional shift register circuit 50 shifts the set bit using the shift direction control signal 54 and the shift clock 56. The shift direction control signal 54 and the shift clock 56 are given by the shift control circuit 124 controlled by the phase detection circuit 120, and when the phase detection circuit 120 detects a phase difference between the clock signal 32 and the internal clock signal 48. Change its state to. That is, the shift direction control signal 54 is
The delay is converted into shift direction information, and the shift clock 56 is a pulse synchronized with the internal clock 48 generated only when a phase difference occurs. The set bit is a register 58a in the bidirectional shift register circuit 50.
Only one of ~ 58h is present, all others are reset bits. Further, the set bit always exists in one of the registers 58a to 58h in the bidirectional shift register circuit 50, and is controlled so that it is not further shifted when it is shifted to the end of the shift register. The reset signal 52 is input to all the registers 58a to 58h and used to give initial values to all the registers. Register 5
Only the initial value of 8a is "H", and the others are "L".
That is, the set bit is set only in the lowest register 58a. The set bit and the reset bit become the selection control signals 42a to 42h of the 8-input 1-output select circuit in the selection circuit 40, and select one of the delay signals 34a to 34h in the signal delay circuit 30 corresponding to the set bit. Then, it is controlled to output as the internal clock 48. The one corresponding to the reset bit is not selected. In this way, the signal delayed by the desired delay amount is extracted from the signal delay circuit 30 and output as the internal clock 48.

The delay control circuit 60 uses the reset signal 52 and the selection control signal 42h to generate the delay control signal 20. When the reset signal 52 is "H", the delay control signal 2
0 becomes "L". This state represents the case where the entire circuit is initialized by the reset signal 52, and the delay circuit element 10 is set by setting the delay control signal 20 to “L”.
The delay due to is controlled to be small. On the other hand, when the selection control signal 42h is "H", the delay control signal 20 is "H". In this state, since the delay due to the delay circuit element 10 is small, the delay clock signal 34 having a large delay amount
This shows the case where h is selected, and the delay control signal 20 is set to "H" to control the delay circuit element 10 to increase the delay.

The above operation is shown in the timing chart of FIG. In FIG. 2, the clock signal 32
Is 30 ns, the signal delay in the selection circuit 40 is 5 ns (including the delay of the buffer circuit 46 due to the load of the internal clock 48), and τ0 = 1n.
It is assumed that s and τ1 = 2 ns. In the next cycle after the reset signal 52 is set to "L", the delayed clock signal 34
Although a is selected, the phase of the internal clock 48 is 9 ns (= 15 ns) with respect to the phase of the clock signal 32 at this point.
-5ns-1ns). Phase detection circuit 120
Detects the advance of this phase and shift control circuit 124
The bidirectional shift register 50 is instructed to shift the set bit via the. By this instruction, the delayed clock signal 34b is selected in the next cycle (second cycle). Thereafter, this operation is repeated until the delayed clock signal 34h is selected in the 7th cycle. When the delayed clock signal 34h is selected, that is, when the selection control signal 42h is activated, the RS latch of the delay control circuit 60 is set by the activated selection control signal 42h and the delay selection signal 20 is set to " H ". As a result, the delay value of each delay circuit element is τ1 (= 2ns).
Therefore, the delay amount of the entire signal delay circuit 30 is 16 ns (=
τ1 × 8). Therefore, in the eighth cycle, the phase of the internal clock 48 is 6 ns with respect to the phase of the clock signal 32.
(= 16ns + 5ns-15ns) delay. On the other hand, the phase detection circuit 120 detects this phase delay and instructs the bidirectional shift register 50 via the shift control circuit 124 to shift the set bit in the opposite direction. By this instruction, the phase delay becomes 4 ns in the 9th cycle (since τ1 = 2 ns, it changes by 2 ns). This operation is repeated thereafter, and the phases match in the 11th cycle.

This state is illustrated in FIG.
The delay immediately after the reset is 6 ns including the signal delay in the selection circuit 40. The trajectory for selecting the delay amount until phase synchronization is the trajectory shown by the dotted line in FIG. In this example,
When the delay selection signal 20 = “L”, the delay amount is 6 ns to 1
3 ns, which can correspond to a specific frequency in the range of 83.3 to 38.5 MHz in frequency conversion, and the delay selection signal 20 =
When it is "H", the delay amount is 7 ns to 21 ns, and it can correspond to a specific frequency in the range of 71.4 to 23.8 MHz in frequency conversion.

As described above, according to this embodiment, the signal delay circuit 30 has a switch circuit and a capacitive load connected thereto, and the delay amount can be controlled by controlling the on / off of the switch circuit. Delay value control and selection circuit 4 using circuit element 10 and delay control signal 20
0, bidirectional shift register circuit 50, and delay control circuit 6
In combination with 0, the phase control information in the signal delay circuit 30 can be controlled by dynamically feeding back the phase control information to the signal delay circuit 30 and selecting a desired delay amount. In this embodiment, the delay amount control range of the signal delay circuit 30 when the delay control signal 20 = “L” is 1 to 8 ns, and the signal delay circuit 30 when the delay control signal 20 = “H”. The delay amount control range is 2 to 16 ns. Further, the timing control circuit in the present embodiment dynamically controls the delay amount per delay circuit element 10 by using the delay control circuit 60, so that the timing control circuit is stable with respect to the frequency fluctuation of the input clock signal 32. Can work. In order to perform smooth phase control, the delay of the entire signal delay circuit 30 when the delay control signal 20 = “L” is equal to the delay control signal 20 =
It is desirable to set the delay value larger than the delay value per delay circuit element 10 in the case of "H", and the signal delay circuit 30
It is desirable that the total delay is set with overlap between the case where the delay control signal 20 = "L" and the case where the delay control signal 20 = "H".

As can be seen from this result, since two delays can be controlled by one signal delay circuit 30, the control range can be widened or narrowed even though the number of delay circuit elements is the same. You can In particular, the delay amount can be dynamically controlled by using the delay control circuit 60 to feed back the signal delay information at a certain time point in order to set the next delay value. In this way, the delay circuit element 1 capable of controlling a plurality of types of delays
Using the signal delay circuit 30 configured by using 0, the information of the bidirectional shift register 50 that controls the selection of the delay value is fed back to the signal delay circuit 30 via the delay control circuit 60. It becomes the point of the circuit.

The delay circuit element 10 may have the output of the inverter 14 connected to the drain of the first N-channel MOS transistor 16 instead of the output of the inverter 12. Further, the first and second MOS transistors 16 and 18 used for the delay circuit element 10 and the N-channel MOS transistor 44 used for the selection circuit 40.
Need not be limited to N-channel MOS transistors, but may be P-channel MOS transistors or N-channel MOS transistors.
The combination of a transistor and a P-channel MOS transistor can be appropriately selected according to the design. In particular, the second MOS transistor 18 does not have to be a transistor, but may be anything as long as it is a capacitive load.
For example, the capacitance between the wiring and the substrate or the capacitance between the diffusion layer and the base plate may be used. Further, as the delay circuit element 10, FIG.
As shown in, a delay circuit element composed of an inverter whose drive capability can be adjusted by a control signal and a normal inverter connected in series may be used. Further, any circuit may be used as long as the delay value can be changed by the control signal. Further, in the present embodiment, a circuit including an N-channel MOS transistor is used as the selection circuit 40, but any implementation method may be used as long as it performs the same operation. Further, instead of the buffer circuit 46, a clock generating circuit having various functions such as generating a multi-phase clock from a single-phase clock may be used.

(Second Embodiment) A timing control circuit according to a second embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows the configuration of a timing control circuit according to the second embodiment of the present invention. Three delay lines are used as delay lines for delaying a clock signal by a fixed period, and a signal delay circuit 10 is used as a signal delay circuit 30. Consider the case of using eight (n = 8).

In the delay circuit element 10, an inverter 12 and an inverter 14 are connected in series, and the output of the inverter 12 is N
It is configured such that it is connected to the gate of the channel MOS transistor 18 and the drain and source of the N-channel MOS transistor 18 are both connected to the ground potential. The signal delay circuit 30 has eight delay circuit elements 10 connected in series, and the outputs of the inverters 14 in each delay circuit element 10 are configured as first to eighth delayed clock signals 34a to 34h. The selection circuit 40 includes nine selection control signals 42, 4
It is composed of a 9-input 1-output select circuit controlled by 2a to 42h and a buffer circuit 46. The bidirectional shift register circuit 50 includes nine registers (flip-flops) 58, 58a to 58h controlled by a reset signal 52, a shift direction control signal 54, and a shift clock 56.
Each of the registers 58,
58a to 58h hold the values held by the selection control signals 42, 42.
a to 42h. Overflow detection circuit 7
0 uses four registers (flip-flops) 72a to 72d controlled by the selection control signal 42h held by the uppermost register 58h of the bidirectional shift register circuit 50, the shift clock 56, and the reset signal 52.
Bit shift register and 4 of registers 72a to 72d
It is composed of a logical product circuit 74 having two outputs as inputs, and an overflow signal 76 is output from the logical product circuit 74.
The three signal delay lines 80, 82, 84 are delay lines each having a different delay amount, which is configured by an inverter chain or the like, and the delay amount is 80 <82 <84. The delay line selection circuit 90 is a 3-input 1-output selection circuit and outputs a fixed delay clock signal 94. The delay line selection control circuit 92 is composed of a shift register controlled by the reset signal 52 and the overflow signal 76, and outputs a delay line selection control signal 96. The phase detection circuit 120 is a circuit having a function of detecting the phase difference between the clock signal 32 and the internal clock 48, and generates the phase difference signal 122 synchronized with the internal clock 48. Shift control circuit 124
Is a circuit having a function of generating the shift direction control signal 54 and the shift clock 56 based on the phase difference signal 122, and controls the shift operation of the bidirectional shift register circuit 50. The timing control circuit according to the present embodiment has the signal delay circuit 30, the selection circuit 40, the bidirectional shift register circuit 50, and the overflow detection circuit 70 configured as described above.
And the signal delay lines 80, 82, 84, the delay selection circuit 90, the delay selection control circuit 92, the phase detection circuit 120, and the shift control circuit 124.
0, 82, 84 are commonly input to the signal delay lines 80, 8
The output of each of 2, 84 is input to the delay line selection circuit 90, the fixed delay clock signal 94 is input to the delay circuit element 10 of the first stage in the signal delay circuit 30, and the fixed delay clock signal 94 and the signal delay circuit are input. 30 eight delayed clock signals 34
a to 34h are input to the 9-input 1-output select circuit in the selection circuit 40, and the 9 selection control signals 58, 58a to 58h output from the bidirectional shift register circuit are input to the selection circuit 4.
0, clock signal 32 and internal clock signal 48
To the phase detection circuit 120, the phase difference signal 122 to the shift control circuit 124, and the shift direction control signal 54
And the shift clock 56 are input to the bidirectional shift register 50, the reset signal 52 and the selection control signal 42h are input to the overflow detection circuit 70, and the reset signal 52 and the overflow signal 76 are input to the delay line selection control circuit 92. It is configured by inputting the line selection control signal 96 to the delay line selection circuit 90.

The operation of the timing control circuit of this embodiment having the above configuration will be described below.

In the delay circuit element 10, the N channel M
The OS transistor 18 serves as a capacitive load, and forms a delay element in combination with the inverters 12 and 14. Assuming that the delay in the delay circuit element 10 is τ2, the signal delay circuit 3 configured by connecting eight delay circuit elements 10 in series.
0th t-th (0 ≦ t ≦ n = 8, t is an integer) output (=
The delay amount of any of the delayed clock signals 34a to 34h is t × τ2, and nine types of delay amounts can be obtained.

The selection circuit 40 has nine selection control signals 42,
42a-42h using fixed delay clock signals 94 and 8
One signal is selected from the delayed clock signals 34a to 34h. In this embodiment, a selection circuit having nine inputs and one output is configured by using nine N-channel MOS transistors 44, a waveform is shaped by using a buffer circuit 46, and then a selection circuit having a configuration for outputting as an internal clock 48 is used. ing.

The bidirectional shift register circuit 50 shifts the set bit using the shift direction control signal 54 and the shift clock 56. The shift direction control signal 54 and the shift clock 56 are given by the shift control circuit 124 controlled by the phase detection circuit 120, and when the phase detection circuit 120 detects a phase difference between the clock signal 32 and the internal clock signal 48. Change its state to. That is, the shift direction control signal 54 is
The delay is converted into shift direction information, and the shift clock 56 is a pulse synchronized with the internal clock 48 generated only when a phase difference occurs. The set bit is a register 58 in the bidirectional shift register circuit 50,
Only one of 58a-58h is present, all others are reset bits. Further, the set bits are always registers 58, 58a to 58 in the bidirectional shift register circuit 50.
If it exists in any one of h and is shifted to the end of the shift register, it is controlled so that it is not further shifted.
The reset signal 52 is input to all the registers 58, 58a to 58h and used to give initial values to all the registers. Only the initial value of the register 58 is set to "H", and the rest are "L". That is, the set bit is set only in the lowest register 58. The set bit and the reset bit become the selection control signals 42, 42a to 42h of the 9-input 1-output select circuit in the selection circuit 40, and the fixed delay clock signal 94 corresponding to the set bit.
Also, one of the delay signals 34a to 34h in the signal delay circuit 30 is selected and controlled to be output as the internal clock 48. The one corresponding to the reset bit is not selected. In this way, the signal delayed by the desired delay amount is extracted from the signal delay circuit 30 and output as the internal clock 48.

The overflow detection circuit 70 takes in the data (= selection control signal 42h) held in the uppermost register 58h in the bidirectional shift register circuit 50 in synchronization with the shift clock 56 and shifts it. The outputs of all the registers 72a to 72d forming the shift register in the overflow detection circuit 70 are input to the logical product circuit 74, and the outputs of all the registers 72a to 72d are "H".
"H" is output as the overflow signal 76 only in the case where By this control, the signal delay circuit 3
At 0, it can be known that the delay amount of the signal has reached the maximum value of the delay control range. That is, in the case of this embodiment,
If the selection control signal 42h continues to be "H" while the shift clock 56 is generated four times (because the shift register is composed of the four registers 72a to 72d), the overflow signal 76 becomes "H". .. The condition that the selection signal 42h continues to be "H" while the shift clock 56 is generated four times is that the delay amount of the signal in the signal delay circuit 30 at the timing of a certain shift clock 56 is the maximum value of the delay control range. Even when
This is because as a result of the phase comparison in the phase detection circuit 120, the maximum value of the delay control range may not be reached at the subsequent timing of the shift clock 56. That is, it is determined that the maximum value of the delay control range is exceeded by keeping the maximum value of the delay control range for a certain predetermined period (here, the period in which the shift clock 56 is generated four times). The reset signal 52 is input to all the registers 72a to 72d,
It is used to give initial values to all registers. The initial values in this case are all "L". In this embodiment, the registers 72a to 72 that form the shift register are
Although it is assumed that d is 4, the number may be any number as long as it is 1 or more, and can be appropriately set according to the design.

The signal delay lines 80, 82, 84 are delay lines composed of inverter chains and the like and having different delay amounts, and the clock signal 32 is used as a common input.
The clock signal is delayed and output for a predetermined period. Here, it is assumed that the magnitude relationship of the delay amounts is 80 <82 <84. Although the number of signal delay lines is three in this embodiment, the number of signal delay lines may be any number of two or more, and can be set as appropriate according to the design.

The delay line selection circuit 90, as shown in FIG.
This is a 3-input 1-output select circuit, which selects one of the three inputs under the control of the delay line selection control signal 96 and outputs it as a fixed delay clock signal 94. In the present embodiment, the delay line selection circuit 90 is composed of a 3-input 1-output select circuit, but the number of inputs is not limited and can be appropriately set according to the number of signal delay lines used.

The delay line selection control circuit 92 generates a delay line selection control signal 96 by the overflow signal 76 and the reset signal 52, as shown in FIG.
Control the delay line selection operation in. That is, if the reset signal 52 is "H" or the overflow signal 76 never becomes "H", the output of the signal delay line 80 is selected, and when the overflow signal 76 becomes "H", the signal delay line 82 is selected. Select the output of. When the overflow signal 76 subsequently becomes “H”, the output of the signal delay line 84 is selected.

The above operation is shown in the timing chart of FIG. In FIG. 7, the cycle of the clock signal 32 is 30 ns, the signal delay in the selection circuit 40 is 3 ns (including the delay of the buffer circuit 46 due to the load of the internal clock 48), and the signal delay line 80.
2 ns, the delay amount of the signal delay line 82 is 8 ns,
When the delay amount of the signal delay line 84 is 14 ns, τ2 =
It is assumed to be 1 ns. In FIG. 7, for simplification of the drawing, the seventh and subsequent cycles after the reset signal 52 is set to “L” are shown. In the 7th cycle, the delayed clock signal 3
4f is selected, but at this time, the phase of the internal clock 48 is 4ns (= 15n) with respect to the phase of the clock signal 32.
s-3ns-2ns-6ns). The phase detection circuit 120 detects the advance of this phase and instructs the bidirectional shift register 50 via the shift control circuit 124 to shift the set bit. By this instruction,
In the next cycle (8th cycle), the delayed clock signal 3
4g is selected. Thereafter, this operation is repeated until the delayed clock signal 34h is selected in the 9th cycle.
In the same cycle, the set bit information is
It is taken into the register 72a in the overflow detection circuit 70. During the following three cycles, the set bit remains in the register 58h, during which the set bit information is stored in all the registers 72a to 72 in the overflow detection circuit 70.
It is taken into d and the overflow signal 76 is output in the 12th cycle. As a result, the delay line selection control circuit 92 gives an instruction to the delay line selection circuit 90, the signal delay line 82 is selected in the 13th cycle, and the phase of the internal clock 48 is 4 ns (= 8 ns) with respect to the phase of the clock signal 32.
+ 8ns + 3ns-15ns). On the other hand, the phase detection circuit 120 detects this phase delay and instructs the bidirectional shift register 50 via the shift control circuit 124 to shift the set bit in the opposite direction. By this instruction, the phase delay is 3n in the 14th cycle.
s. This operation is repeated thereafter, and the phases match in the 17th cycle.

As described above, according to the present embodiment, when the delay amount in the range which cannot be controlled by the delay control range of the signal delay circuit 30 is handled, it is different in advance before the clock signal is input to the signal delay circuit 30. The clock signal is delayed by one of the plurality of delay lines 80, 82, 84 having a delay amount, and thereafter, the delay amount is controlled by the signal delay circuit 30, the selection circuit 40 and the bidirectional shift register circuit 50, and the timing is Take control. The overflow detection circuit 70 uses the information of the selection control signal 42h of the bidirectional shift register circuit 50 to determine whether or not timing control is possible within the delay control range of the signal delay circuit 30, and if further delay is required. By issuing an instruction to the delay line selection control circuit 92 so that the delay line selection circuit 90 selects the output of the signal delay line having a larger delay, a wide range of timing control can be realized. ..

For example, each of the signal delay circuits 30 in the conventional example and the present embodiment comprises eight stages of delay circuit elements,
If the delay of one stage of the delay circuit element is 1 ns, the delay amount control range of only the signal delay circuit 30 is only 0 to 8 ns. In this embodiment, the signal delay lines 80, 82, 8
If the delay values of 4 are 2, 8 and 14 ns, respectively, the timing control circuit as a whole has 5 to 13 ns and 11 to 19 n.
It is possible to obtain a delay amount control range of s, 17 to 25 ns. 100 to 38.5 MH in terms of frequency
z, 45.5 to 26.3 MHz, 29.4 to 20 MHz
It will be possible to correspond to a specific frequency within the range. In order to perform smooth timing control, it is desirable that the delay amount of the entire timing control circuit when each of the signal delay lines 80, 82 and 84 is used has an overlap. In the above example, the overlap value is 2 ns.

As can be seen from this result, the amount of delay is controlled by using the signal delay lines 80, 82, 84 having a fixed delay and the signal delay circuit 30, and it is detected that the amount of delay exceeds the controllable range. The timing control range can be widened or narrowed by automatically switching the output from the signal delay line dynamically, as detected by the circuit 70. In particular, the point of the timing control circuit of the present embodiment is to automatically and dynamically control the output from the signal delay line by using the overflow detection circuit 70.

As the delay circuit element 10, a circuit in which the gate of the N-channel MOS transistor 18 is connected to the output of the inverter 14 instead of the output of the inverter 12 may be used. Further, the N-channel MOS transistor 44 used in the selection circuit 40 need not be limited to the N-channel MOS transistor, but may be a P-channel MOS transistor, an N-channel MOS transistor and a P-channel MO transistor.
It can be appropriately selected according to the design, such as combined use with the S transistor. Furthermore, the N-channel MOS transistor 18 does not have to be a transistor, and may be anything as long as it is a capacitive load. For example, a wiring-substrate capacitance or a diffusion layer-base plate capacitance may be used. Further, the inverters 12 and 14 may be simply connected in series without having a capacitive load. Further to the extreme argument, any circuit may be used as long as it can obtain a desired delay value. Further, in the present embodiment, a circuit including an N-channel MOS transistor is used as the selection circuit 40, but any implementation method may be used as long as it performs the same operation. Further, instead of the buffer circuit 46, a clock generating circuit having various functions such as generating a multi-phase clock from a single-phase clock may be used.

(Third Embodiment) A timing control circuit according to a third embodiment of the present invention will be described below with reference to the drawings. FIG. 8 shows the configuration of the timing control circuit according to the third embodiment of the present invention. As a delay circuit constituting the signal delay circuit 30, the delay circuit element 10 is 8
Consider a case where the first and second delay circuits, each of which is used (n = 8), are connected in series.

The delay circuit element 10 is the same as that used in the second embodiment, and the outputs 34a to 34h of the delay circuit elements 10 constituting the first delay circuit are respectively n P.
The drain of the channel MOS transistor is connected to the second
Output 35 of each delay circuit element 10 constituting the delay circuit of
a to 35h are connected to the drains of n (8 in this embodiment) N-channel MOS transistors, and the sources of n (8 in this embodiment) P-channel MOS transistors and n N-channel MOS transistors are connected. The respective sources of the channel MOS transistors are commonly connected to provide n delayed clock signals. The clock signal 32 is connected to the input of the first delay circuit, and the output 34f of the delay circuit element 10 forming the first delay circuit is used as the input of the second delay circuit. The other components and their connection relationships are described in the first embodiment.
Is the same as.

The operation of this embodiment will be described below. In this embodiment, only the configuration of the signal delay circuit 30 is different from that of the first embodiment, and therefore only the operation of the signal delay circuit 30 will be described here.

At reset, in the signal delay circuit 30, since the delay control signal 20 = “L”, the delayed clock signals 34a to 34h connected to the n P-channel MOS transistor sides are input to the selection circuit 40. It is ready to be used. When the delay amount of the signal required for the phase synchronization of the clock signal 32 and the internal clock signal 48 is obtained by any of the delayed clock signals 34a to 34g, the timing can be controlled only by the first delay circuit. is there. However, when the delay amount is insufficient with only the delay amount of the first delay circuit, the delay control circuit 60 is controlled by the phase detection circuit 120, the shift control circuit 124, and the bidirectional shift register circuit 50, and the delay control signal 20 is output.
= “H”, and the delayed clock signals 35a to 35h connected to the n N-channel MOS transistor sides are input to the selection circuit 40. by this,
Further, the delay amount can be increased.

When the sum of the signal delay in the P-channel MOS transistor or the N-channel MOS transistor and the signal delay in the selection circuit 40 is 6 ns (including the delay of the buffer circuit 46 due to the load of the internal clock 48), the delay circuit element If the delay at 10 is 1 ns, the entire timing control circuit can obtain a delay amount control range of 7 ns to 22 ns. When converted into frequency, it can correspond to a specific frequency in the range of 71.4 to 22.7 MHz.

In the present embodiment, the P-channel MOS transistor and the N-channel are respectively switched to switch between the output of each delay circuit element 10 in the first delay circuit and the output of each delay circuit element 10 in the second delay circuit. Although a MOS transistor is used, any one may be used as long as it can perform an equivalent operation.

(Embodiment 4) A timing control circuit according to a fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 9 shows the configuration of the timing control circuit according to the fourth embodiment of the present invention. Consider a case where eight signal delay circuits 10 (n = 8) are used as the signal delay circuit 30. Here, in order to simplify the description, it is assumed that the delay circuit element 10 has two kinds of delay values. It goes without saying that the delay circuit element 10 may have a plurality of (two or more) delay values.

The delay circuit element 10 has an inverter 12 and an inverter 14 connected in series, the output of the inverter 12 is connected to the drain of the first N-channel MOS transistor 16, and the gate of the first N-channel MOS transistor 16 is delayed. Control signal 20 is connected to the first N channel MO
The source of the S transistor 16 is the second N-channel MOS
The second N-channel MOS transistor 18 is connected to the gate of the transistor 18, and the drain and source of the second N-channel MOS transistor 18 are both connected to the ground potential. The signal delay circuit 30 connects eight delay circuit elements 10 in series, supplies a clock signal 32 to the input of the inverter 12 in the first stage delay circuit element 10, and outputs the clock signal 32 to the inverter 14 in each delay circuit element 10. The outputs are first to eighth delayed clock signals 34a to
34h. The selection circuit 40 includes an 8-input 1-output selection circuit controlled by eight selection control signals 42a to 42h and a buffer circuit 46. The bidirectional shift register circuit 50 includes eight registers (flip-flops) 58a to 5 controlled by a reset signal 52, a shift direction control signal 54, and a shift clock 56.
Each register consists of a shift register using 8h.
8a to 58h hold the values held by the selection control signals 42a to 42
Output as h. The delay control register 100 includes 8-bit registers 102a to 102h for writing / holding / reading delay control data under the control of the reset signal 52 and the delay control register write signal 104. The phase detection circuit 120 is a circuit having a function of detecting the phase difference between the clock signal 32 and the internal clock 48, and generates the phase difference signal 122 synchronized with the internal clock 48. The shift control circuit 124 is a circuit having a function of generating the shift direction control signal 54 and the shift clock 56 based on the phase difference signal 122, and controls the shift operation of the bidirectional shift register circuit 50.

The timing control circuit of this embodiment is composed of the signal delay circuit 30 and the selection circuit 40 configured as described above.
, The bidirectional shift register circuit 50, and the delay control register 100. The 8-bit register output of the delay control register 100 is used as the eight delay control signals 20a to 20h of the signal delay circuit 30, respectively. Thirty
The delayed clock signals 34a to 34h of the clock signal 3 are input to the 8-input 1-output select circuit in the selection circuit 40, and the clock signal 3
2 and the internal clock signal 48 are input to the phase detection circuit 120, the phase difference signal 122 is input to the shift control circuit 124, the shift direction control signal 54 and the shift clock 56 are input to the bidirectional shift register 50, and the bidirectional shift is performed. Eight selection control signals 42a-output from the register circuit 50
42h.

The operation of the timing control circuit of the present embodiment having the above configuration will be described below.

In the delay circuit element 10, the first N-channel MOS transistor 16 serves as a switch circuit which is turned on / off by a signal given to the delay selection signal 20, and the second N-channel MOS transistor 18 serves as a capacitive load. .. When the delay selection signal 20 becomes "L" level, the first N-channel MOS transistor 16 is turned off, the capacitive load formed of the second N-channel MOS transistor 18 is disconnected, and the delay in the delay circuit element 10 is τ0. (Delay when the first N-channel MOS transistor 16 is off). On the contrary, when the delay selection signal 20 becomes the “H” level, the first N-channel MOS transistor 16 is turned on, the capacitive load including the second N-channel MOS transistor 18 is connected, and the delay circuit element 10 The delay is τ1 (delay when the first N-channel MOS transistor 16 is on) (here, τ0 <τ1 is clear). In the signal delay circuit 30, the 1st to 8th delay control signals 20a to 20h are the mth (1 ≦ m ≦ n = 8, 1 ≦ m ≦ n = 8, 1) of the signal delay circuit 30 depending on the combination of the signal levels “L” or “H”. (m is an integer) The delay amount in the output (= any of the delayed clock signals 34a to 34h) is controlled to two values of τ0 and τ1. The first to eighth delay control signals 20a to 20h are given by the values set in the delay control register 100. Therefore, by controlling the value set in the delay control register 100, the delay amount of each delay circuit element 10 in the signal delay circuit 30 can be independently controlled.

Bidirectional shift register circuit 50 shifts the set bit using shift direction control signal 54 and shift clock 56. The shift direction control signal 54 and the shift clock 56 are provided by the shift control circuit 124 controlled by the phase detection circuit 120, and when the phase detection circuit 120 detects a phase difference between the clock signal 32 and the internal clock 48. Change that state. That is, the shift direction control signal 54 is obtained by converting the phase lead / lag into shift direction information, and the shift clock 56 is a pulse synchronized with the internal clock 48 generated only when a phase difference occurs. The set bits are
Registers 58a-5 in the bidirectional shift register circuit 50
Only one of 8h is present, all others are reset bits. Further, the set bit always exists in one of the registers 58a to 58h in the bidirectional shift register circuit 50, and is controlled so that it is not further shifted when it is shifted to the end of the shift register. Reset signal 52
Is input to all the registers 58a to 58h and is used to give initial values to all the registers. Register 58
Only the initial value of “a” is “H”, and the others are “L”. That is, the set bit is set only in the lowest register 58a. The set bit and the reset bit become the selection control signals 42a to 42h of the 8-input 1-output select circuit in the selection circuit 40, and select one of the delay signals 34a to 34h in the signal delay circuit 30 corresponding to the set bit. Then, it is controlled to output as the internal clock 48. The one corresponding to the reset bit is not selected. In this way, the signal delayed by the desired delay amount is extracted from the signal delay circuit 30 and output as the internal clock 48.

FIG. 10 is a timing chart showing the above operation. In FIG. 10, the clock signal 3
When the period of 2 is 30 ns and the signal delay in the selection circuit 40 is 5 ns (including the delay of the buffer circuit 46 due to the load of the internal clock 48), τ0 = 1n
It is assumed that s and τ1 = 3 ns. Further, in the delay control register 100, the registers 102a, 102b, 1
It is assumed that "H" is set in 02g and 102h and "L" is set in 102c to 102f. Reset signal 52
Is set to "L", the delay clock signal 3
4a is selected, but at this time, the phase of the internal clock 48 is 7 ns (= 15n) with respect to the phase of the clock signal 32.
s-5ns-3ns). Phase detection circuit 120
Detects the advance of this phase and shift control circuit 124
The bidirectional shift register 50 is instructed to shift the set bit via the. By this instruction, the delayed clock signal 34b is selected in the next cycle (second cycle). The delayed clock signals 34a and 34b are set by the delay control register 100 to have a large delay τ1, and the clock signal 32 is rapidly delayed in phase to near the phase synchronization point. After this operation is repeated, the delayed clock signal 34f is selected and the phases match in the sixth cycle. Delayed clock signals 34c to 34f
Are set so that the difference between them is τ0 (= 1 ns), so that the delay can be controlled in a fine time unit near the phase synchronization point.

As described above, according to the present embodiment, the signal delay circuit 30 has the switch circuit and the capacitive load connected thereto, and the delay amount can be controlled by controlling the on / off of the switch circuit. A delay control register 1 having a plurality of delay circuit elements 10 connected in series is used.
By independently controlling each delay circuit element 10 constituting the signal delay circuit 30 by the data held in 00, and selecting a desired delay amount by the combination of the selection circuit 40 and the bidirectional shift register circuit 50, It is possible to control a wide range of delay without increasing the number of delay circuit elements 10 in the signal delay circuit 30.

In the present embodiment, it is assumed that the signal delay circuit 30 comprises eight stages (n = 8) of delay circuit elements 10, the delays thereof are 1 ns (= τ0) and 3 ns (= τ1), and the phase locked loop ( When the delay amount required to lock the PLL is 8 to 10 ns, the delay amounts of the first, second, seventh, and eighth delay circuit elements 10 are set to τ1, and the third to sixth delay circuit elements are set. By setting the data for setting the delay amount of 10 to τ0 in the delay control register 100, the precision of the delay control near the lock point can be set to τ0, and fine control can be performed. Further, when the lock point is deviated, τ1 is used as the delay amount with coarse accuracy, so that the convergence to the lock point is performed at high speed.
As described above, the point of the timing control circuit of the present embodiment is that the delay control register 100 can be used to freely set the delay amount of each delay circuit element 10 in the signal delay circuit 30.

The delay circuit element 10 may have the output of the inverter 14 connected to the drain of the first N-channel MOS transistor 16 instead of the output of the inverter 12. Further, the first and second MOS transistors 16 and 18 used for the delay circuit element 10 and the N-channel MOS transistor 44 used for the selection circuit 40.
Need not be limited to N-channel MOS transistors, but may be P-channel MOS transistors or N-channel MOS transistors.
The combination of a transistor and a P-channel MOS transistor can be appropriately selected according to the design. In particular, the second MOS transistor 18 does not have to be a transistor, but may be anything as long as it is a capacitive load.
For example, the capacitance between the wiring and the substrate or the capacitance between the diffusion layer and the base plate may be used. Further, as the delay circuit element 10, FIG.
As shown in, a delay circuit element composed of an inverter whose drive capability can be adjusted by a control signal and a normal inverter connected in series may be used. Further, any circuit may be used as long as the delay value can be changed by the control signal. Further, in the present embodiment, a circuit including an N-channel MOS transistor is used as the selection circuit 40, but any implementation method may be used as long as it performs the same operation. Further, instead of the buffer circuit 46, a clock generating circuit having various functions such as generating a multi-phase clock from a single-phase clock may be used.

In this embodiment, the delay circuit element 10 is
I considered the case of having two types of delay values.
In case of having an extension value, n bits × j words (j is j ≧ l
og ₂use the control data of the smallest natural number that satisfies i)
This allows you to set a delay value of n bits x j words.
It

[0073]

As described above in detail, according to the invention of claim 1, the delay control circuit and the phase control circuit can control the delay amount based on the phase difference information of the phase control circuit. By controlling the signal delay circuit in which a plurality of elements are connected in series and the selection circuit that selects and outputs one of the outputs of each delay circuit element, the delay amount that minimizes the phase difference between the signals is obtained. Timing control can be realized over a wide frequency range by changing the delay value of the delay circuit element and the combination thereof.

According to the second aspect of the present invention, the signal delay circuit is formed by connecting a plurality of delay circuit elements capable of controlling the delay value in series, and both the delay value control using the delay control signal and the selection circuit are used. A combination of the directional shift register circuit and the delay control circuit dynamically controls the range of phase control in the signal delay circuit by dynamically feeding back the phase control information to the signal delay circuit and selecting a desired delay amount. It will be possible. In particular, the feature that the delay control can be performed in a wide range with a small circuit scale makes it optimal as a delay circuit of a phase locked loop (PLL).

According to the third aspect of the present invention, when a delay amount in a range that cannot be controlled by the delay control range of the signal delay circuit is handled, a different delay amount is provided in advance before the clock signal is input to the signal delay circuit. 1 of multiple delay lines
Delays the clock signal, and then controls the delay amount by the signal delay circuit, the selection circuit, and the bidirectional shift register circuit, and performs the timing control.The overflow detection circuit controls the highest selection control of the bidirectional shift register circuit. The signal information is used to determine whether timing control is possible within the delay control range of the signal delay circuit, and if further delay is required, an instruction is sent to the delay line selection control circuit to cause the delay line selection circuit to By controlling so as to select the output of the signal delay line having a larger delay, a wide range of timing control can be realized. In particular, before performing fine delay control, by delaying to a range that can be controlled by the signal delay circuit by using a means for selecting a delay line according to the required delay amount, wide range timing control is possible. It can be realized and is optimal as a delay circuit of a phase locked loop (PLL).

Further, according to the invention of claim 4, as the signal delay circuit, two sets of delay circuit elements each having a plurality of delay circuit elements connected in series are connected in series, and the delay circuit elements in the two sets of delay circuits are connected. A mechanism that can select either of the outputs is provided, and the delay control signal is controlled by the combination of the selection circuit, the bidirectional shift register circuit, and the delay control circuit to switch the two sets of delay circuits to obtain the desired delay amount. It is possible to realize timing control over a wide frequency range.

Further, according to the invention of claim 5, each of the delay circuits which comprises a plurality of delay circuit elements capable of controlling the delay amount connected in series and which constitutes the delay circuit by the data held in the delay control register is used. Control elements independently,
By selecting a desired delay amount with the combination of the selection circuit and the bidirectional shift register circuit, it becomes possible to control a wide range of delays without increasing the number of delay circuit elements in the signal delay circuit. In particular, the phase locked loop (PL
When used as a delay circuit of L), the delay amount of some delay circuit elements on the input side of the clock signal and some delay circuit elements on the termination side of the delay circuit element sequence is set to be large, and the delay amount of the delay circuit elements in between is set large. By setting data to set the delay to a small value in the delay control register and making the delay necessary for phase locking near the middle of the delay circuit element sequence, improve the accuracy of delay control near the lock point. be able to. Further, when the lock point is deviated, the delay amounts at both ends of the delay circuit element array are set to be large, so that the convergence to the lock point can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a timing control circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the timing control circuit in the embodiment.

FIG. 3 is an explanatory diagram showing a timing control range of the timing control circuit in the embodiment.

FIG. 4 is a circuit diagram showing another configuration example of the delay circuit element 10.

FIG. 5 is a block diagram showing a configuration of a timing control circuit according to a second embodiment of the present invention.

FIG. 6 shows a delay line selection circuit 90 and a delay line selection control circuit 9
2 is a circuit diagram showing a configuration example of FIG.

FIG. 7 is a timing chart showing the operation of the timing control circuit according to the second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a timing control circuit according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a timing control circuit according to a fourth embodiment of the present invention.

FIG. 10 is a timing chart showing the operation of the timing control circuit in the embodiment.

FIG. 11 is a timing diagram illustrating the necessity of phase synchronization control.

FIG. 12 is a block diagram showing a configuration of a conventional timing control circuit.

[Explanation of symbols]

 10 Delay Circuit Elements 12, 14 Inverter 16, 18, 44 N Channel MOS Transistor 20 Delay Selection Signal 30 Signal Delay Circuit 32 Clock Signal 34a-34h Delayed Clock Signal 40 Selection Circuit 42a-42h Selection Control Signal 46 Buffer Circuit 48 Internal Clock 50 Bidirectional shift register circuit 52 Reset signal 54 Shift direction control signal 56 Shift clock 58a to 58h Register 60 Delay control circuit

Claims (5)

[Claims] 1. A delay circuit element having a plurality of delay values for delaying a given signal for a predetermined time and outputting the delayed signal (n ≧ n).
2, n is an integer) a delay circuit connected in series, a selection circuit for selecting and outputting one of the outputs of the delay circuit elements, a signal given to the delay circuit and the selection circuit. The phase control circuit includes a phase control circuit that determines the output of the delay circuit element that should be selected so that the phases of the output signals match, and a delay control circuit that controls the delay value of the delay circuit element itself. When it is determined that the delay amount in the entire delay circuit is insufficient for synchronization, the delay control circuit changes the delay value of the delay circuit element to change the delay control range in the delay circuit. A characteristic timing control circuit. 2. The timing control circuit according to claim 1, wherein an n-input 1-output selection circuit which receives an output of each delay circuit element is used as a selection circuit, and a signal applied to the delay circuit is provided as a phase control circuit. A phase detection circuit that compares the phases of the output signals of the selection circuit, a shift control circuit that outputs a shift clock and a shift direction control signal based on the phase difference information from the phase detection circuit, and the shift clock and the shift direction control signal. According to the above, an n-bit bidirectional shift register circuit that bidirectionally shifts only one set bit is used, and an RS latch that uses the output of the most significant bit in the bidirectional shift register circuit as a set signal is used as a delay control circuit. The delay value of the delay circuit element is changed by the output signal of the RS latch to change the delay value of the entire delay circuit. One of the outputs of the delay circuit element is selected so that the phase difference between the signal given to the delay circuit by the set bit in the shift register circuit and the signal output from the n-input 1-output selection circuit is minimized. Timing control circuit. 3. The timing control circuit according to claim 1, wherein the delay circuit includes a plurality of delay lines that delay a given signal by different fixed periods having a common input and outputs of the plurality of delay lines. Using a delay line selection circuit that selects one output from among and a series of n delay circuit elements having a constant delay value that receives the output signal of this delay line selection circuit and connected in series, An n + 1 input 1 output selection circuit, which receives the output signal of the delay line selection circuit and the output of each delay circuit element as input, is used as a phase control circuit to compare the phase of the signal given to the delay circuit with the phase of the output signal of the selection circuit. A phase detection circuit, a shift control circuit that outputs a shift clock and a shift direction control signal based on the phase difference information from the phase detection circuit, the shift clock and the shift direction control circuit. An n-bit bidirectional shift register circuit that bidirectionally shifts only one set bit according to a signal is used, and as a delay control circuit, it is detected that the set bit in the bidirectional shift register circuit remains at the most significant bit for a certain period of time. By using the overflow detection circuit and the delay line selection control circuit that switches the output of the delay line selected by the delay line selection circuit in the delay circuit by the output signal of this overflow detection circuit, the delay value of the entire delay circuit is changed. The delay circuit obtains a delay amount necessary for phase synchronization and minimizes the phase difference between the signal given to the delay circuit by the set bit in the bidirectional shift register circuit and the signal output from the n + 1 input 1 output selection circuit. A timing control circuit characterized by selecting the output of any of the elements. 4. The timing control circuit according to claim 1, wherein as the delay circuit, first and second delay circuit elements are connected in series, each delay circuit element delays a given signal for a predetermined time and outputs the delayed signal. Either the output of the m-th delay circuit element of the first delay circuit (1 ≦ m ≦ n, m is an integer) or the output of the m-th delay circuit element of the second delay circuit, with the circuits connected in series. A two-input one-output selection circuit element that selects n is used, an n-input one-output selection circuit that receives the output of each of the selection circuit elements is used as the selection circuit, and a delay is used as the phase control circuit. A phase detection circuit that compares the phase of the signal given to the circuit and the output signal of the selection circuit, a shift control circuit that outputs a shift clock and a shift direction control signal based on the phase difference information from this phase detection circuit, and a shift clock. The only set bits using a bi-directional shift register circuit of n bits to be shifted bidirectionally accordance click and shift direction control signal, as the delay control circuit,
An RS latch that uses the output of the most significant bit in the bidirectional shift register circuit as a set signal is used, and the output signal of the RS latch switches the delay circuit selected by the selection circuit element in the delay circuit, and the bidirectional shift is performed. The output of one of the selection circuit elements in the delay circuit is selected so that the phase difference between the signal given to the delay circuit by the set bit in the register circuit and the signal output by the n-input 1-output selection circuit is minimized. A characteristic timing control circuit. 5. A delay circuit element having a plurality of delay values for delaying a given signal for a predetermined time and outputting the delayed signal (n ≧ n).
(2, n are integers), a delay circuit connected in series, an n-bit delay control register for selecting a specific delay value of each of the delay circuit elements, and an n input having an output of each of the delay circuit elements as an input. A 1-output selection circuit and an n-bit bidirectional shift register circuit for bidirectionally shifting only one set bit are provided, and the selection operation of the n-input 1-output selection circuit is performed by the set bit in the bidirectional shift register circuit. A timing control circuit characterized by controlling.