JPH05191232A - Delay circuit - Google Patents

Abstract

PURPOSE:To reduce the entire area by ensuring a required delay with a few number of transistors(TRs) by providing a transfer gate controlled by an output of an inverter circuit to the input side of the inverter circuit. CONSTITUTION:When a high level signal is inputted to an input terminal 101 as the initial state, an output terminal 103 goes to a low level, a PMOS transistor(TR) 109 of a transfer gate is turned on and an NMOS TR 111 is turned off. When a low level signal is inputted to the input terminal 101, an input terminal 113 of an inverter circuit goes to a low level via the transfer gate and the output terminal 103 goes to a high level. In this case, the transfer gate is not completely opened and till the TRs 109 and 111 are completely turned off or on, the low level signal is not completely delivered to the input terminal 113. The delay gives an effect onto the output terminal 103 to delay the output terminal 103 to reach completely a high level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for ensuring a predetermined delay time.

[0002]

2. Description of the Related Art Conventionally, there has been a delay circuit as shown in FIG. FIG. 2 is a diagram showing a conventional delay circuit. In order to secure a required delay time, PMOS transistors 201, 203, 205 and N corresponding thereto are provided.
It is composed of a three-stage inverter circuit composed of MOS transistors 207, 209, 211 and load capacitors 213, 215. Originally, the PMOS transistor 201
The load capacitance 213 is added to the output of the inverter circuit composed of the NMOS transistor 207 and the NMOS transistor 207 to reduce the transistor size of the inverter circuit to smooth the input waveform and secure a desired delay time. However, with this method, an LSI whose transistor layout and transistor size cannot be changed, such as a gate array LSI.
Can't deal with. Therefore, as shown in FIG.
A desired delay time was secured by connecting a plurality of inverter circuits.

[0003]

However, the above method has a problem in that the number of transistors used to secure a desired delay time increases, and as a result, the circuit area of the entire delay circuit increases. there were.

[0004]

In order to solve the above problems, the present invention provides a transfer gate, which is controlled by the output of the inverter circuit, on the input side of the inverter circuit.

[0005]

According to the present invention, the waveform of the signal input to the inverter circuit can be blunted by gradually changing the conduction states of the NMOS transistor and the PMOS transistor forming the transfer gate.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a circuit diagram of the present invention.
The present invention will be described using.

The present invention has an input terminal 101 and an output terminal 10.
3, an inverter circuit including a PMOS transistor 105 and an NMOS transistor 107, and a transfer gate including a PMOS transistor 109 and an NMOS transistor 111. The source (or drain) of the transfer gate PMOS transistor 109 and the source (or drain) of the NMOS transistor 111 are commonly connected to the input terminal 101.
It is connected to the.

In addition, the drain (or source) of the PMOS transistor 109 and the NMOS transistor 111
The drains (or sources) of are commonly connected to the input terminal 113 of the inverter circuit. Also, PMO
The gate of the S transistor 109 and the gate of the NMOS transistor 111 are commonly connected to the output terminal 103 and the output terminal 115 of the inverter circuit. The inverter circuit has a general CMOS configuration, and the gates of the PMOS transistor 105 and the NMOS transistor 107 are commonly connected to form an input terminal 113 of the inverter circuit. The source of the PMOS transistor 105 is connected to the power supply voltage (high level), and the drain is connected to the output terminal 103 and the drain of the NMOS transistor 107. The source of the NMOS transistor 107 is grounded (low level), and the drain is connected to the output terminal 103 and the drain of the PMOS transistor 105. The drain of the PMOS transistor 105 and the drain of the NMOS transistor 107 form an output terminal 115 of the inverter circuit.

Next, the operation of the circuit of the present invention will be described in detail with reference to the signal waveform diagram of FIG. In FIG. 3, the horizontal axis represents time and the vertical axis represents the signal level. Where the waveform 30
Reference numeral 1 denotes a signal input to the input terminal 101, which has a waveform 303
Is the signal appearing at the input terminal 113 of the inverter circuit, and the waveform 305 is the signal appearing at the output terminal 305. In addition,
For easy understanding, the horizontal axis is divided into high level t1, low level t2, and high level t3 when the signal input to the input terminal is high level again.

First, as an initial state, it is assumed that a high level signal is input to the input terminal 101 and a low level signal which is an inverted signal of this high level appears at the output terminal 103. This is designated as t1. At t1, since the output terminal 103 is at the low level, the PMOS transistor 111 is on and the NMOS transistor 109 is off. Looking at the transfer gate as a whole, PM
Since the OS transistor 111 is on, the high level signal input to the input terminal is transmitted to the input terminal 113 of the inverter circuit through the source and drain of the PMOS transistor 111. Next, when a low level signal is input to the input terminal 101, t2
As shown in, the input terminal 113 of the inverter circuit is lowered to the low level via the transfer gate.
Then, the inverter circuit receives the output of the transfer gate and raises the output terminal 103 to a high level. At the same time, as the output terminal 103 of the transfer gate rises to a high level, the PMOS transistor 109, which has been on until now, is turned off, and the NMOS transistor 1 that has been off until now.
Head in the direction of turning on 11. Then, as shown at the beginning of t2 in FIG. 3, the waveform 303 becomes stepwise at the almost intermediate level between the low level and the high level, and the waveform 303
It can be seen that, as shown by the waveform 301, the full swing does not occur at once, but shifts in the time axis direction. At this intermediate level, the waveform 303 becomes stepwise because the NMO
This is because the S transistor 111 changes from off to on and the PMOS transistor 109 changes from on to off. Therefore, the transfer gate is not completely opened, and the low-level signal input to the input terminal 101 is not input to the input terminal of the inverter circuit until the PMOS transistor 109 and the NMOS transistor 111 are completely turned off or on. 1
Not completely transmitted to 13. That is, the delay occurs only for the time when the states of the PMOS transistor 109 and the NMOS transistor 111 are determined. Such a delay naturally affects the output terminal 103, and the waveform 305
As shown in, the output terminal 103 is delayed from becoming a high level completely. After that, the level of the input terminal 113 and the level of the output terminal 103 of the inverter circuit become stable.

Then, when a high level signal is input to the input terminal 101, as shown at t3, the input terminal 113 of the inverter circuit is raised to a high level via the transfer gate. Then, the inverter circuit receives the output of the transfer gate and outputs the output terminal 103.
To a low level. At the same time, in the transfer gate, as the output terminal 103 drops to the low level, the PMOS transistor 109 that has been off until now is turned on, and the NMOS transistor 111 that was on until now is turned off. Head to. Then, as shown at the beginning of t3 in FIG. 3, the waveform 303 has a staircase shape at a substantially intermediate level between the low level and the high level, and the waveform 303 does not swing fully at once like the waveform 301, and the time axis direction You can see that it will shift to. At this intermediate level, the waveform 303 has a stepped shape for the same reason as described above. Therefore, the transfer gate is not completely opened, and the high-level signal input to the input terminal 101 is not input to the input terminal 113 of the inverter circuit until the PMOS transistor 109 and the NMOS transistor 111 are completely turned on and off. Not completely transmitted to. That is,
The delay occurs only for the time when the states of the PMOS transistor 109 and the NMOS transistor 111 are fixed. This delay also affects the output terminal 103 and causes the waveform 3
As indicated by 05, the output terminal 103 is delayed from becoming a low level completely. After that, the level of the input terminal 113 and the level of the output terminal 103 of the inverter circuit become stable.

As described above, the signal input to the input terminal 101 can be delayed by a desired time.

Next, FIG. 4 shows a comparison result of characteristics of the circuit of the present invention shown in FIG. 1 and the conventional circuit shown in FIG. In FIG. 4, the horizontal axis represents time and the vertical axis represents the signal level. Here, a waveform 401 is a signal input to the input terminal 101 (in the conventional circuit, a signal input to the first-stage inverter circuit), and a waveform 403 is a signal appearing at the output terminal 103 of the circuit of the present invention. Then, the waveform 405 is the output signal of the conventional circuit (the signal output from the third-stage inverter circuit). Further, as described above, the time axis is t
It will be divided into 1, t2 and t3.

The effect of the present invention can be understood by looking at the initial stage of t2 and t3 in FIG. Focusing only on the initial stage of t2, in the conventional circuit, when the input signal becomes low level, the output signal is completely stable at high level. On the other hand, in the circuit of the present invention, even if the input signal becomes low level, the output signal does not completely become high level for a while, and is stabilized at high level after being delayed for a predetermined time. Considering that the circuit of the present invention is composed of four MOS transistors, whereas the conventional circuit is composed of six MOS transistors, a large delay time can be secured with a small number of elements. You can understand the effect of the present invention.

If a larger delay time is desired, a plurality of circuits shown in FIG. 1 can be connected.

In order to obtain an inverted signal delayed from the input signal by using the conventional circuit, it is necessary to connect an even number of inverter circuits to the first stage inverter circuit without fail. In this case, six MOS transistors are required. On the other hand, the circuit of the present invention can be configured with a minimum of four MOS transistors.

[0017]

As described in detail above, according to the present invention, the required delay time can be secured with a small number of transistors. Therefore, the area of the entire delay circuit can be reduced.

Further, it is particularly effective in an LSI such as a gate array LSI in which the transistor size is defined.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit diagram of the present invention.

FIG. 2 is a diagram showing a conventional delay circuit.

FIG. 3 is a signal waveform diagram showing the operation of the circuit of the present invention.

FIG. 4 is a diagram showing a comparison result of characteristics of a circuit of the present invention and a conventional circuit.

[Description of Reference Signs] 101 input terminal 103 output terminal 105 PMOS transistor 107 NMOS transistor 109 PMOS transistor 111 NMOS transistor 113 input terminal of inverter circuit 115 output terminal of inverter circuit

Claims (1)

[Claims] 1. A transfer gate comprising an input terminal, an output terminal, an inverter circuit for outputting an inverted signal of an input signal, and an N-type MOS transistor and a P-type MOS transistor, each of the MO gates.
A first electrode of the S-transistor is commonly connected, a second electrode of each of the MOS transistors is commonly connected, and a gate electrode of each of the MOS transistors is commonly connected to a transfer gate. First of each of the connected MOS transistors
An electrode is connected to the input terminal, a gate electrode of each of the MOS transistors commonly connected is connected to the output terminal, and a second electrode of the MOS transistors commonly connected is connected to the output terminal. A delay circuit, wherein the inverter circuit is connected to.