JPH05190847A - MOS semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a MOS semiconductor device capable of increasing another current flowing between a source and a drain and driving another device by the current flowing between the source and the drain. A surface diffusion layer 7 as an N-type high-concentration impurity diffusion layer region is formed on a part of the source regions 2a, 2b on the substrate surface side.
Then, the source region 2b and the surface diffusion layer 7 form a PN junction. Then, the band bending is increased by the PN junction composed of the source region 2b and the surface diffusion layer 7,
Increase the probability of tunneling between bands. This allows
By increasing the current gain, another device can be driven by the current flowing between the source regions 2a and 2b and the drain region 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device to which a band-to-band tunneling phenomenon is applied.

[0002]

2. Description of the Related Art Conventionally, a MOS type semiconductor device, for example, MO
In the S-type field effect transistor, as the scale of the element is reduced, there is a problem that the reliability of the element characteristic is deteriorated due to the hot carrier effect, the short channel effect, etc. As a countermeasure against this problem, LDD The structure was devised. However, as long as the operation mechanism of the MOS field effect transistor, that is, the operation mechanism of controlling the carriers in the channel region under the gate by the voltage applied to the gate is used, the above-mentioned hot carrier effect, short channel effect, or the like causes the device characteristic There was a problem that a decrease in reliability was unavoidable. Further, as the gate length is reduced, it becomes difficult to form a complicated structure such as an LDD structure.

Therefore, as a means for solving these problems, A BAND by Eiji Takeda et al. Described in IEDM 88, pp402-405.
TO BAND TUNELING MOS DE
VICE (B ² T-MOSFET) has been devised.
Note that a similar semiconductor device is a European Pate
Also described in NT 0399261.

This MOS field effect transistor (MO
As shown in FIG. 10, the SFET) has a drain 2 formed of a high-concentration impurity diffusion layer of the same conductivity type (P-type) as the substrate 1 and a source 3 of a high-concentration conductivity type (N-type) different from that of the substrate 1. It was formed of an impurity diffusion layer, and the gate 4 was formed so as to partially overlap with each other with the gate oxide film 5 interposed therebetween.

The operating mechanism of this MOSFET is, for example, when a P type is used for the substrate 1, a positive voltage V is applied to the gate 4.
g, when a negative voltage Vd is applied to the drain 2, an electron-hole pair is generated by band-to-band tunneling in the drain region surface layer (shaded portion) 6 where the gate 4 and the drain 2 overlap, and the hole moves to the drain 2. Then, the electrons move to the source terminal 3 to which the positive voltage is applied. Since the current I _SD flowing between the source and the drain is caused by the electrons generated by the band-to-band tunneling, it can be controlled by the potential difference between the gate and the drain.

The advantage of the operating mechanism of the MOS field effect transistor is that there is almost no decrease in reliability due to the short channel effect or hot carrier effect. From this, it is considered that the mechanism applying the interband tunneling phenomenon is suitable for miniaturization.

[0007]

However, as shown in FIG.
The conventional MOS field effect transistor shown in FIG. 2 is configured as described above. When the gate width is 100 μm, the magnitude of the current I _SD flowing between the source and the drain is 1
There is a problem that it is difficult to drive other devices with this current I _{SD because} it is about 0 ⁻⁸ amps.

The present invention has been made to solve the above problems, and is a MOS that can increase the current flowing between the source and the drain and drive another device by the current flowing between the source and the drain. An object of the present invention is to provide a semiconductor device.

[0009]

The present invention has been made in view of the above circumstances, and a MOS semiconductor device according to the present invention is a semiconductor substrate of a first conductivity type and a high concentration of a second conductivity type. A drain region made of an impurity diffusion layer, a source region made of a high-concentration impurity diffusion layer of the first conductivity type, and a second-conduction type high-concentration impurity diffusion layer region formed in a part of the source region on the substrate surface side. And a gate partially overlapping with the high-concentration impurity diffusion layer region of the second conductivity type with a gate insulating film interposed therebetween.

[0010]

According to the above-described structure, the MOS semiconductor device according to the present invention has the second conductivity type high-concentration impurity diffusion in the region where the gate and the source region formed of the first conductivity-type high-concentration impurity diffusion layer overlap. By providing the layer region, the high-concentration impurity diffusion layer region and a part of the source region form PN.
A junction is formed, and the PN junction increases band bending, increases the probability of tunneling between bands, and increases the current flowing between the source and drain.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a MOS type semiconductor device, for example, a MOSFET according to an embodiment of the present invention.

The MOSFET has a P-type silicon substrate 1, on which source regions 2a and 2b are formed by diffusing P-type impurities, and also N-type impurities. Is diffused to form the drain region 3. Then, a surface diffusion layer 7 as an N-type high-concentration impurity diffusion layer region is formed on a part of the source regions 2a, 2b on the substrate surface side, and on the surface diffusion layer 7, as a gate insulating film. A gate 4 is formed with the gate oxide film 5 interposed therebetween so as to partially overlap each other. Furthermore, the source region 2
The surfaces of a and the drain region 3 are covered with a protective oxide film 8, and field insulating films 9 are formed on both end sides of the protective oxide film 8. The shaded area 6 is an area where the band-to-band tunneling phenomenon occurs.

Here, the formulation of the generation ratio of interband tunnel electrons will be described.

FIG. 2 is a schematic diagram of the case where the space charge density distribution (ρ (z)) in the vicinity of the substrate surface is used for the P-type substrate 1. The z axis is in the depth direction, and z =
0 is the surface, that is, the interface between the substrate and the gate oxide surface,
z = a is the position of the PN junction, the region of 0 <z <a is the N-type diffusion layer region (N-type impurity concentration Nn) on the surface, and the region of a <z is the P-type diffusion layer region (P-type impurity concentration). Np), and b
Is the depth of the depleted region due to the application of the voltage V _GS between the gate and the substrate. When the electric field potential is E (z), the electrostatic potential is V (z), the dielectric constant of silicon is ε _Si , and the silicon oxide film is ε _OX , the depth b of this depletion region is calculated by the following four equations. Can be obtained by self-consistently solving.

E (z) = (1 / ε _Si ) ∫ρ (z) dz (1) V (z) = − ∫E (z) dz (2) V _OX = (ε _Si / ε _OX ) T _OX E (0) (3) V (0) + V _OX = V _GS (4) However, the integration range is from b to z.

Further, from these equations, the impurity band concentration in each of the P-type and N-type regions, the oxide film thickness, and the bending of the energy band (-eV when the voltage V _GS between the gate and the substrate is given).
(Z); e is also an elementary quantity). However,
Here, E is used as a boundary condition so that generality is not lost.
(B) = V (b) = 0. Then, if the solutions of these equations are obtained, the generation ratio of tunnel electrons is calculated as follows.

The tunnel probability for the triangular potential barrier is given by the following equation according to the calculation based on the WKB approximation.

T (z) = AEa (z) ² exp (−8π (2m ^* E _G ³ ) ^1/2 / 3ehEa (z)) (5) where A is a proportional constant and m ^* is an effective electron. Mass, E _G is the silicon band gap, and h is the Planck constant.

As Ea (z), the average value of the electric field at the starting point (z) and the ending point (u) of the interband tunneling, that is, Ea (z) = (E (z) + E (u)) / 2 is used. However, the coordinate u of the end point with respect to the start point z is obtained by the following equation from the band bending, that is, the electrostatic potential.

V (u) −V (z) = E _G (6) As described above, the tunnel electron generation ratio J is calculated by the following equation.

J = −eN _V ∫T (z) dz (7) Note that the integration range is from c to b, N _V is the effective electron density of the valence band at the starting point, and c is tunneling. It represents the lower limit of the region and can be obtained as the solution of the following equation.

V (0) −V (c) = E _G (8) By using the above equation, the gate voltage determined by
It is possible to estimate the optimum conditions for maximizing the distribution of impurities within the controllable range, the PN junction depth, and the ratio of tunnel electron generation to the gate oxide film thickness.

FIG. 3 is a diagram showing an example of the calculation result, showing the dependence of the tunnel electron generation ratio J on the junction depth a. However, V _GS is 12V, Nn is 1.0E + 19 / cm ³ , and Np is 2.0E + 19 / cm.
³ , T _OX was set to 10 nm. Note that a = 0 corresponds to the case where no PN junction is provided. It can be seen that the optimum value of the junction depth a is about 6 nm, and the generation ratio of tunnel electrons at that time is about 20 times that in the case where the PN junction is not provided. From this, it can be seen that providing the PN junction in the band-to-band tunneling region is effective in increasing the tunnel current generation rate.

Next, the manufacturing process of the MOSFET of this embodiment will be described.

First, as shown in FIG. 4, a field insulating film 9 made of SiO ₂ is formed on the silicon substrate 1 in a portion other than the transistor element forming region by a selective oxidation method such as LOCOS. Sacrificial oxide film 10
To form.

Then, a photoresist 11 is applied in a predetermined pattern and, as shown in FIG. 5, a region which causes a band-to-band tunneling phenomenon is patterned, and the impurity concentration and the PN junction depth determined by using the above-mentioned formula are set. (For example, Nn = 1.0E + 18 / cm ³ , Np = 2.0
Impurity diffusion layer 7 having E + 19 / cm ³ , a = 6 nm)
And the source region 2b is formed by an ion implantation method, a vapor phase diffusion method or the like.

Further, as shown in FIG. 6, using the photoresist 12, a high-concentration impurity diffusion layer in the drain region 3 is formed by ion implantation and thermal diffusion.

Then, as shown in FIG. 7, the source region 2a is formed using the photoresist 13 by the ion implantation method and the thermal diffusion.

Then, as shown in FIG. 8, etching is performed using the photoresist 14 as a mask to form the gate 4
Pattern.

After that, as shown in FIG. 9, a protective oxide film 8 is formed.
Are formed by thermal oxidation and position, and contact holes corresponding to the source region 2a and the drain region 3 are formed in the protective oxide film 8 by etching, and then respective electrodes are formed to form a MOSFET.

In the above embodiments, the P-type substrate 1 is used as the first conductivity type semiconductor substrate, but the present invention is not limited to this, and some or all of the impurity types may be used. May be the opposite type.

[0033]

As described above, according to the present invention,
A PN junction is provided in the region where the gate and the source overlap, and the band bending is increased by this PN junction.
The probability of tunneling between bands can be increased,
It is possible to increase the current gain, which allows the source,
Other devices can be driven by the current flowing between the drains.

[Brief description of drawings]

FIG. 1 is a sectional view showing a MOS semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an impurity distribution in a depth direction of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a calculation result of an equation for a generation ratio of interband tunnel electrons according to an embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of a MOS semiconductor device according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a conventional MOS semiconductor device.

[Explanation of symbols]

 1 Silicon substrate 2a, 2b Source region 3 Drain region 4 Gate 5 Gate oxide film 7 Surface diffusion layer

Claims (1)

[Claims] 1. A MOS provided with a semiconductor substrate of a first conductivity type.
Type semiconductor device, a drain region formed of a second-conductivity-type high-concentration impurity diffusion layer, a source region formed of a first-conductivity-type high-concentration impurity diffusion layer, and a part of the source region on the substrate surface side are formed. A second conductivity type high-concentration impurity diffusion layer region, and a gate partially overlapping the second conductivity type high-concentration impurity diffusion layer region via a gate insulating film. apparatus.