JPH05190814A - Basic layout method of transistor - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Transistors can be spread over the entire surface,
Increase transistor integration density while achieving short lead times. A plurality of P-type or N-type diffusion regions are formed on a semiconductor substrate, and a gate electrode 11 is provided along the surface of the diffusion region, and is formed in a lowermost wiring layer including at least a first wiring layer. The fixed wirings 12 to 14 of the gate electrode 11
And the second fixed region between the gate electrode 11 and the first fixed wiring 12 between the gate electrode 11 and the first fixed wiring 12, and one region 10a of the diffused region 10 divided by the gate electrode 11 and the second fixed region. A contact hole 15 is formed between the wiring 13 and the third fixed wiring 14 between the other region 10b of the diffusion region 10 divided by the gate electrode 11 and the third fixed wiring 14, respectively. 12 to 14 are exposed to the final wiring layer by the via hole 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a basic transistor layout method suitable for shortening the LSI development period. In general, a typical semi-custom LSI is a gate array with a fixed transistor pattern. By applying an arbitrary wiring program to all wiring layers, various logic circuits can be freely created, and small amount of It is often used in the development of various types of LSI.

By the way, since it is necessary to modify all wiring layers in the gate array, it is not necessarily optimum for LSI development which requires extremely short delivery time.

[0003]

2. Description of the Related Art IEICE Technical Committee (1989.
6.23) CAS 89-31 "Ultra-fast delivery ASIC" QC
L series ", Yamashita et al." Discloses a short delivery LSI technology in which a transistor pattern is fixed and wiring layers other than the final layer are also fixed. According to this
The development period can be considerably shortened because only the final wiring layer needs to be programmed.

FIG. 14 is a layout diagram of essential parts of a conventional short delivery LSI. Internal area of the LSI chip 1 (Inner regi
On), a large number of basic transistors 2 including P-channel transistors and N-channel transistors are regularly arranged, and wiring regions (also referred to as wiring channels) 3 and 4 are provided between the basic transistors 2. Has been. A large number of via holes and a large number of fixed wirings (1st layer wiring) are formed in advance in the wiring channels 3 and 4, and when the final layer is the second layer, an arbitrary circuit is formed by the program wiring of the second layer. Realize the configuration.

[0005]

However, in such a conventional short delivery LSI, since the wiring channel is provided between the basic transistors, the transistor integration density is reduced by the wiring channel. There was a problem that became. Therefore, it is an object of the present invention to increase the integration density of transistors while allowing transistors to be spread over the entire surface and realizing a short delivery time.

[0006]

In order to achieve the above-mentioned object, the present invention connects the respective wiring parts of a transistor in a semiconductor substrate and the final wiring layer with an existing fixed wiring as shown in FIG. A basic layout method of a transistor, which enables free combination of the transistors by providing an arbitrary wiring on the final wiring layer, wherein a P-type or N-type diffusion region 10 is formed on a semiconductor substrate, and
The gate electrode 11 is arranged along the surface of the diffusion region, and a plurality of fixed wirings 12 to 14 formed in the lowermost wiring layer including at least the first wiring layer are arranged in parallel with the gate electrode 11 and the diffusion region 10 is formed. The gate electrode 11 and the first fixed wiring 12 between the gate electrode 11 and the first fixed wiring 12,
Between one region 10a of the diffusion region 10 divided by the gate electrode 11 and the second fixed wiring 13, and between the other region 10b of the diffusion region 10 divided by the gate electrode 11 and the third fixing. The wirings 14 are connected to each other through contact holes 15, and the fixed wirings 12 to 14 are exposed to the final wiring layer by the via holes 16.

[0007]

In the present invention, since the fixed wiring is arranged above the transistor, the wiring channel is not necessary, the transistors can be densely packed, and the integration density can be increased. Further, a flexible circuit configuration can be realized only by selectively connecting via holes in the final wiring layer, and the delivery time can be shortened.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 13 are views showing an embodiment of a basic layout method of a transistor according to the present invention. In FIG. 2, 20 is an LSI chip. The LSI chip 20 has a peripheral area (Peripheral reg) where input / output circuits and terminals are arranged.
ion) and the inner area (Inner regio
n) and a large number of transistor rows A, B, C, D, ... Are arranged in the internal region as shown in an enlarged view of a part thereof. Here, each column is composed of P-channel type or N-channel type transistors of the same type, and is arranged so that adjacent columns have different types.

Each row has a P-type or N-type impurity diffusion region formed in the longitudinal direction of the row.
On the surface of this diffusion region, many gate electrodes (Poly-Si
gate). The gate electrodes are arranged at equal intervals so as to traverse the diffusion region in the lateral direction. The diffusion region directly below the gate electrode is the channel region of the transistor, and the diffusion region between adjacent gate electrodes is the source (or drain). ) It is designed to function as an area.
The layout of FIG. 2 is excellent in layout ease because the P-type and N-type diffusion regions are regularly and alternately arranged and the gate electrodes are arranged at equal intervals.

The range surrounded by the broken line in the figure controls the current flowing through the channel region immediately below the gate electrode, that is, the current between the source (S) and the drain (D), by the voltage applied to the gate electrode (G). One FET (field ef
fect transistor). 3 shows the wiring of the first layer (1st laye) applied to the transistor layout of FIG.
rwiring) layout diagram. In this figure, two fixed wirings La and Lb arranged in parallel with the gate electrode and overlapping the diffusion region are used as a basic wiring unit, and a large number of wiring units are regularly arranged at intervals of the gate electrode. To do. For example, the wiring La that overlaps the gate electrode is connected to the gate electrode directly below via a contact hole (contact hole) Ca, and the wiring Lb functions as a diffusion region (source / drain) directly below via the contact hole Cb. Part). Here, 1 FET is 1
Including two wirings La and Lb forming one wiring unit and one wiring Lb ′ in an adjacent wiring unit, the wiring La is a wiring for a gate, the wiring Lb is a wiring for a drain (or a source), The wiring Lb ′ is used as a wiring for source (or drain). Hereinafter, the wiring La is referred to as a first fixed wiring, the wiring Lb is referred to as a second fixed wiring, and the wiring Lb ′ is referred to as a third fixed wiring. First to third fixed wirings La, Lb, Lb ′
The via holes Va _{1 to} Va ₃ , Vb _{1 to} Vb ₃ , V.
b ₁ ′ to Vb ₃ ′ are connected, and these via holes are exposed in the upper wiring layer (here, the second wiring layer) of the wiring layer on which the first to third fixed wirings are formed. ing.

FIG. 4 is a diagram in which a main part of an arbitrary transistor array (for example, a main part corresponding to _four FETs Q _{1 to} Q ₄ ) is hierarchized and symbolized. Represents a transistor, represents a contact hole, represents a fixed wiring, and represents a via hole, and these are built in advance. Further, indicates a wiring layer (final wiring layer: the second layer here) where the via hole is exposed, and this wiring layer is used as a program wiring layer when designing an LSI. That is, the wiring design of the final wiring layer allows free connection between the selected via holes and between the selected via hole and the power supply, and various logic circuits can be formed by appropriately combining the transistors.

FIG. 5 is a design example of a 2-input NAND gate. The inputs A1 and A2 are respectively applied to the gate electrodes of the two transistors 30 and 31 of the P-channel type transistor array, and these gate electrodes and the gate electrodes of the two transistors 32 and 33 of the N-channel type transistor array are connected. Connect the wires with wires 34 and 35,
Further, the drains of the transistors 30 and 31 are connected to each other by the wiring 36. Further, the drain of the transistor 31 is connected to the source of the transistor 33 by the wiring 37, the sources of the transistors 30 and 31 are connected to the high potential side power supply VDD by the wiring 38, and the drain of the transistor 32 is connected by the wiring 39 to the low potential side power supply. VS
Connect to S.

The gate electrodes of the two transistors 40 and 41 adjacent to the transistors 30 and 31 are connected to VDD by wirings 42 and 43, respectively, and the two transistors 4 adjacent to the transistors 32 and 33 are connected.
Gate electrodes 4 and 45 are connected to VSS by wirings 46 and 47, respectively. This is because the adjacent transistor is always kept in a cut-off state (normally-off state) to achieve electrical isolation from other circuits.

According to this structure, the wiring 3 is formed in the final wiring layer.
4, 35, 36, 37, 38, 39, 42, 43, 46
By simply programming 47 and 47, when both A1 and A2 are high logic, the transistors 32 and 33 are both turned on, and the logic appearing on the wiring 36 can be set to low level. Therefore, it is possible to configure a two-input NAND gate in which the output X is an A1 × A2 negative logic (NAND).

Incidentally, FIG. 6 shows an example of constructing a 4-input NAND gate in addition to the 2-input NAD gate described above.
It suffices to secure P-type and N-type transistors according to the number of inputs and design wirings 50 to 62 that connect these transistors and the power supply. 7 and 8 show
It is a figure explaining the isolation | separation method in case an adjacent circuit electrically performs a separate operation. In this case, as shown in FIG. 7, at least one transistor is secured between adjacent circuits, VDD is applied to the gate electrode if the transistor is a P-channel type, or if the transistor is an N-channel type, the gate is applied. Apply VSS to the electrodes. In this case, the secured transistor always operates as a normally-off transistor, so that adjacent circuits can be insulated and electrically separated.

FIGS. 9 and 10 show preferred wiring examples when the fixed wiring is used as a simple signal line. In FIG. 9, the fixed wiring used as a simple signal line is denoted by reference numeral 7.
When represented by 0 to 75, the gate electrodes and diffusion regions of the transistors (see reference numerals 77 to 79 in FIG. 10) connected to these fixed wirings are connected to a power supply or a signal of a predetermined potential. With this, the transistor can be normally operated as normally-off, and the fixed wiring can be used as a simple signal line without causing a malfunction.

FIG. 11 is a diagram specifically showing a pattern layout of transistors and fixed wirings arranged on a chip. The upper half of the drawing shows a virtual state in which the fixed wiring is removed to expose the transistor, and the lower half shows a state in which the fixed wiring is laid out. The gate electrode or diffusion region of the transistor pattern and the fixed wiring of the first layer are connected by a contact hole, and each fixed wiring is connected by a via hole to the second wiring layer (final wiring layer).
Exposed to.

FIG. 12 schematically shows the fixed wiring of FIG. 11, and FIG. 13 shows an actual final wiring layer using the schematic pattern. In FIG. 13, for example, one 4-input NAND gate 80 and 2
Inverter gates 81 and 82 are configured, and the right half is 1
One 3-input NAND gate 83 and one 2-input NOR gate 84 are configured. For each gate, by laying out the final wiring layer indicated by hatching appropriately,
It can be easily realized.

As described above, in this embodiment, since the fixed wiring is formed so as to overlap the transistor pattern and the fixed wiring is exposed to the final wiring layer, various designs can be made only by designing the final wiring layer. A logic circuit can be realized and the delivery time can be shortened. Moreover, since all the fixed wirings overlap the transistor pattern, the wiring channel can be eliminated, and the transistors can be densely arranged for the layout. Therefore, the transistors can be spread over the entire surface to increase the degree of integration, which is particularly suitable for the development of large-scale LSI.

In the embodiment, continuous transistors having a common diffusion region are used, but the present invention is not limited to this. For example, transistors independent from each other may be used, or a common portion may be used. It is also possible to group and arrange several transistors each having a. Further, in the embodiment, the example of the two-layer wiring in which the first layer is the fixed wiring layer and the second layer is the program wiring layer is shown, but it goes without saying that the number of layers may be more than two layers.

[0021]

According to the present invention, the transistors can be spread over the entire surface, and it is possible to increase the integration density of the transistors while realizing a short delivery time.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a layout diagram of a transistor pattern according to an embodiment.

FIG. 3 is a layout diagram including a transistor pattern and a fixed wiring according to an embodiment.

FIG. 4 is a symbol diagram of a hierarchical structure according to an embodiment.

FIG. 5 is a layout diagram of a final wiring layer when forming a 2-input NAND gate.

FIG. 6 is a 4-input NAND in addition to a 2-input NAND gate
FIG. 6 is a layout diagram of a final wiring layer when forming a gate.

FIG. 7 is a layout diagram of a final wiring layer in consideration of separation between adjacent circuits.

FIG. 8 is a diagram showing a separation transistor between adjacent circuits.

FIG. 9 is a layout diagram of a final wiring layer when the fixed wiring is simply used as a signal line.

FIG. 10 is a diagram showing a signal line separation transistor.

FIG. 11 is a specific layout diagram including a transistor pattern and a fixed wiring according to an embodiment.

FIG. 12 is a schematic layout diagram of the fixed wiring of FIG.

13 is a logic circuit connection diagram realized using the schematic layout of FIG.

FIG. 14 is a layout diagram of a conventional example.

[Explanation of symbols]

 10: Diffusion region 10a: One region 10b: The other region 11: Gate electrode 12: First fixed wiring 13: Second fixed wiring 14: Third fixed wiring 15: Contact hole 16: Via hole

Claims (1)

[Claims] 1. A transistor in which each portion of a transistor in a semiconductor substrate and a final wiring layer are connected by an existing fixed wiring, and an arbitrary wiring is provided on the final wiring layer, thereby enabling a flexible combination of the transistors. In the basic layout method of 1., a P-type or N-type diffusion region (10) is formed on a semiconductor substrate, and a gate electrode (11) is provided on the surface of the diffusion region, and at least a first wiring layer is formed. A plurality of fixed wirings (12 to 14) formed in the lowermost wiring layer including the gate electrode (11) are arranged in parallel with the gate electrode (11) and overlap the diffusion region (10); And the first fixed wiring (1
2) and the diffusion region (1) divided by the gate electrode (11).
0) one area (10a) and the second fixed wiring (13)
And the other region (10b) of the diffusion region (10) divided by the gate electrode (11) and the third fixed wiring (1).
The basic layout of the transistor is characterized in that the fixed wirings (12 to 14) are exposed to the final wiring layer by the via holes (16) by connecting the contact holes (15) to the wirings 4) respectively. Method.