JPH05190779A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To avoid a drop in the current-amplification factor of a reverse- direction vertical-type transistor and to avoid a drop in the high-speed operation of an IIL element due to the storage of minority carriers by a method wherein a self-aligned ultrahigh-speed transistor and the IIL element are integrated on the same chip. CONSTITUTION:An NPN transistor 32, an NPN transistor 33 and a horizontal- type PNP transistor 34 are formed and integrated on a silicon substrate 31 in a self-aligned manner. An emitter-extraction-part opening 42 for the NPN transistor 32 and a collector-extraction-part opening 43 for the NPN transistor 33 are formed in a self-aligned manner with base extraction electrodes 38a, 38b. A P-type intrinsic base layer 47 for the NPN transistor 32 is formed in an N-type epitaxial layer 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a self-aligned ultra high speed bipolar transistor and an IIL element formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art High-speed ECL (Emitter-Coupled Logic)
Circuits and other bipolar circuits such as analog circuits can be easily integrated on the same chip. For this reason, an integrated circuit in which a digital circuit and an analog circuit coexist is I
IL (Integrated Injection Logic) elements are widely used.

FIG. 3 shows a circuit configuration diagram of the IIL element. I
In a vertical transistor that constitutes an IL element, carriers move in the opposite direction, unlike a normal vertical transistor. A normal vertical transistor is arranged from a high-concentration diffusion layer near the surface to an emitter, a base, and a collector. On the other hand, the vertical transistor of the IIL element is arranged from the high-concentration diffusion layer near the surface to the collector, the base, and the emitter. That is, the vertical transistor of the IIL element has a reverse structure as compared with the normal vertical transistor. The IIL element is a vertical NP having such a reverse structure.
It is a logic element composed of an N-transistor 1 and a lateral PNP transistor 2.

The lateral PNP transistor 2 has a composite structure in which the base of the vertical NPN transistor 1 having a reverse structure is used as a collector. Here, the PNP transistor 2 functions as an injector 3 that injects charges into the base of the NPN transistor 1. Further, the vertical NPN transistor 1 operates as an inverter.

By the way, in recent years, bipolar transistors have been
It is described in Japanese Examined Patent Publication No. 2-108451 that a high-speed ECL circuit can be realized by miniaturization using a self-alignment technique. The contents will be described below with reference to the drawings.

FIGS. 4A to 4D are sectional views in order of steps for explaining a method for manufacturing an NPN bipolar transistor using a conventional self-alignment technique.

A buried collector layer 12 is formed on the surface of the silicon substrate 11. Then, the epitaxial layer 13 is grown on the silicon substrate 11. Next, LO for element isolation
The COS film 14 is formed in a predetermined region on the surface of the epitaxial layer 13. After that, a polysilicon film to be the base extraction electrode 15 and subsequently an oxide film 16 are grown on the entire surface. Further, boron, which is an impurity, is introduced into the polysilicon film serving as the base extraction electrode 15 by ion implantation. Oxide film 16 using the resist used in photolithography as a mask
Then, the polysilicon film to be the base extraction electrode 15 is selectively removed by etching. In this way, the intrinsic base region 17 on the surface of the epitaxial layer 13 is exposed (FIG. 4).
(A)).

Next, a nitride film 18 is grown on the oxide film 16 and the intrinsic base region 17. Thereafter, heat treatment is performed to remove boron as an impurity from the polysilicon film serving as the base extraction electrode 15 on the intrinsic base region 1 on the surface of the epitaxial layer 13.
7 is introduced into the peripheral portion to form the external base layer 19 (FIG. 4B).

Further, a polysilicon film is grown on the entire surface. Then, this polysilicon film is anisotropically etched. By this etching, the polysilicon side wall 20 is formed on the side wall of the polysilicon film 15 which is the base extraction electrode. This polysilicon sidewall 20
The nitride film 18 is removed by etching with using as a mask. Next, the emitter extraction electrode portion opening 21 is formed in self-alignment with the polysilicon film which is the base extraction electrode 15 (FIG. 4).
(C)).

Finally, a polysilicon film is grown on the entire surface. After that, the polysilicon film is etched using a resist formed by photolithography as a mask. As a result, the emitter extraction electrode 22 is formed. After that, boron, which is an impurity, is introduced into the emitter extraction electrode 22 by using ion implantation. Then, heat treatment is performed to introduce boron into the intrinsic base region 17 on the surface of the epitaxial layer 13 through the emitter extraction electrode portion opening 21. The intrinsic base layer 23 is formed as described above. Further, arsenic, which is an impurity, is introduced into the emitter extraction electrode 22 by using ion implantation. After that, arsenic as an impurity is introduced into the intrinsic base layer 23 through the emitter extraction electrode portion opening 21 by heat treatment. As a result, the emitter layer 24 is formed (FIG. 4D).

[0011]

SUMMARY OF THE INVENTION In the above conventional technique,
The base extraction electrode 15, the emitter extraction electrode opening 21, and the emitter layer 24 are formed in a self-aligned manner by using a polysilicon film for the base extraction electrode 15. Further, the intrinsic base layer 23 is formed by diffusing impurities from the polysilicon film which is the emitter extraction electrode 22. However, when the ECL circuit or the high frequency linear circuit and the IIL element are integrated on the same substrate by using the above-described conventional transistor structure, the following problems arise.

A transistor which operates at a very high speed is formed by using a self-alignment technique, and an IIL element is formed in another step. In this case, the number of steps is increased, the manufacturing cost is increased, and the production yield is reduced.

For this reason, it is necessary to form the vertical transistor having the reverse structure which constitutes the IIL element by using the self-alignment technique. An epitaxial layer 13 is formed below the intrinsic base layer that is the emitter of the vertical transistor having the reverse structure. The impurity concentration of the epitaxial layer 13 is lower than those of the buried collector layer 12 and the intrinsic base layer 23. Therefore, when the thickness of the region of the epitaxial layer 13 having a low impurity concentration is increased, the carrier injection efficiency is reduced and the current amplification factor is reduced. Therefore, the operation of the IIL element becomes unstable.

When the impurity concentration becomes thicker, I
When the IL element is operated, the number of minority carriers accumulated in the epitaxial layer 13 serving as the emitter layer of the vertical transistor having the reverse structure increases. The operation speed of the IIL element is determined by the charge / discharge of this minority carrier. Because of this II
The operation speed of the L element decreases.

In view of the above problems, it is an object of the present invention to provide a semiconductor integrated circuit having an IIL element which does not increase the number of steps and manufacturing cost and can operate stably at high speed.

[0016]

In order to solve the above-mentioned problems, a semiconductor integrated circuit device of the present invention comprises a first vertical semiconductor element having a forward structure on a semiconductor substrate of a first conductivity type,
At least a second vertical semiconductor element having a reverse structure of the IIL element, the second conductivity type emitter layer of the first vertical semiconductor element, and the second vertical semiconductor element of the second vertical semiconductor element. A second conductive type collector layer, a first conductive type outer base layer of the first vertical type semiconductor device, and a first conductive type base contact layer of the second vertical type semiconductor device. The emitter layer and the external base layer are formed in self-alignment, and the collector layer and the base contact layer are formed in self-alignment.

Also, a second conductive type semiconductor layer formed on the first conductive type semiconductor substrate, and two second conductive layer formed in the peripheral portion of the first and second semiconductor element regions in the semiconductor layer. 1
A conductive type first diffusion layer, a first conductive type first polycrystalline semiconductor film formed as an extraction electrode of the first diffusion layer, and a second conductive layer formed between the first diffusion layers. Type 2
And a second conductive type second polycrystalline semiconductor film formed as an extraction electrode of the second diffusion layer, and the first diffusion layer is bonded to the first semiconductor element region. A third diffusion layer of the first conductivity type formed shallower than the depth, and a fourth diffusion layer of the first conductivity type formed in the second semiconductor element region deeper than the depth of the first diffusion layer. Is.

In order to solve the above problems, a method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of forming a second conductive type semiconductor layer on a first conductive type semiconductor substrate, and a first step of forming the semiconductor layer. Forming a first diffusion layer of the first conductivity type in the semiconductor element region, forming a first polycrystalline semiconductor film on the semiconductor substrate, and forming a first polycrystalline semiconductor film on the first polycrystalline semiconductor film. A step of forming a first insulating film, a step of introducing a first impurity of a first conductivity type into the first polycrystalline semiconductor film,
A step of selectively etching away the first insulating film and the first polycrystalline semiconductor film to form a first opening;
Forming a second insulating film at least in the first opening; introducing the first impurity into the semiconductor layer to form a second diffusion layer of a first conductivity type; Forming a second opening in the second insulating film; growing a second polycrystalline semiconductor film in the second opening;
Selectively introducing a second impurity of the first conductivity type into the second polycrystalline semiconductor film in the second semiconductor element region other than the second semiconductor element region, and the second opening through the second opening.
Second impurity is introduced into the semiconductor layer to form a third diffusion layer, and a second diffusion layer is formed on all the second polycrystalline semiconductor films.
Introducing a conductive type third impurity, and introducing the third impurity into the semiconductor layer through the second opening,
The method includes a step of forming a fourth diffusion layer of the second conductivity type.

[0019]

According to the semiconductor integrated circuit and the method of manufacturing the same of the present invention, the base extraction electrode and the collector layer of the vertical transistor having the reverse structure forming the IIL element have the forward structure by using the self-alignment technique. It can be formed in the same process as the base extraction electrode and the emitter layer of a normal vertical transistor.

Thus, the vertical transistor having the forward structure and the IIL element can be integrated on the same substrate by using the self-alignment technique.

Further, in the vertical transistor of the forward direction structure which can operate at a very high speed using the self-alignment technique shown in the prior art, impurities are diffused from the emitter electrode formed of the polysilicon film to form the base layer. Form. However, in the manufacturing method of the present invention, the junction depth of the intrinsic base layer of the vertical transistor having the reverse structure forming the IIL element can be formed deeper than that of the vertical transistor having the forward structure. ..

Therefore, the region having a low impurity concentration in the epitaxial layer formed below the intrinsic base layer of the vertical transistor having the reverse structure can be thinned.

Since the region having a low impurity concentration in the epitaxial layer can be thinned in this manner, the current amplification factor of the vertical transistor having the reverse structure is not lowered.

Further, since the minority carriers are not accumulated, the IIL element can be operated at high speed.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention.

On the P-type silicon substrate 31 having a specific resistance of about 10 Ωcm, the following three regions are mainly formed.
The first is a vertical NPN transistor 3 that has an extremely thin base and has a forward structure capable of operating at ultra-high speed.
Area where 2 is formed. Two are regions where the vertical NPN transistor 33 having the reverse structure of the IIL element is formed.
The three are regions in which the lateral PNP transistor 34 serving as the injector of the IIL element is formed.

When the P-type silicon substrate 31 is used, the ultra-high speed vertical NPN transistor 32 and the vertical NPN transistor 33 which requires high speed operation by the IIL element are replaced by NP.
It can be composed of an N-type transistor. Therefore, the mobility of carriers is higher in the PNP transistor than in the NPN transistor. In addition, a shallow emitter-base junction can be formed in the NPN transistor due to the diffusion rate of each impurity. Therefore, the operating speed of the element can be increased.

An N type buried layer 35 is formed in a predetermined region on the surface of the silicon substrate 31. The buried layer 35 is
N-type buried collector layer 35 of NPN transistor 32
a and the buried emitter layer 3 of the NPN transistor 33
5b and.

Here, the buried emitter layer 35b of the NPN transistor 33 also serves as the base lead of the PNP transistor 34 of the IIL element. This buried layer 3
5 has a junction depth of 1-2 μm and a sheet resistance of 50-
It is 100Ω / □.

When the junction depth of the buried layer 35 is 2 μm or more, the parasitic junction capacitance becomes large. This prevents the device from operating at high speed. Sheet resistance is 100Ω /
When it is □ or more, the parasitic resistance becomes large, which prevents the device from operating at high speed. If the junction depth is 1 μm or less or the sheet resistance is 50 Ω / □ or less, the surface concentration of the burying layer 35 exceeds 3 × 10 ¹⁹ cm ⁻³ . Impurities in the buried layer 35 rise upward due to the heat treatment performed after the buried layer 35 is formed. As a result, the breakdown voltage of the device deteriorates.

Next, an N type epitaxial layer 36 is grown on the silicon substrate 31. Epitaxial layer 3
The film thickness of 6 is 1 μm, and its specific resistance is about 0.5 Ωcm. The thickness of the epitaxial layer 36 is 0.6-1.
It is used at about 2 μm. Here, the epitaxial layer 36
The thicker the film, the lower the speed at which the device operates. On the contrary, when the epitaxial layer 36 is thin, the element breakdown voltage of the element is lowered.

The epitaxial layer 36 serves as a collector in the NPN transistor 32 and serves as the NPN transistor 33.
Operates as an emitter and as a base in the PNP transistor 34. Therefore, the NPN transistor 32
This part of the epitaxial layer 36 is called an N type epicollector. Similarly, in the NPN transistor 3, it is called an epi-emitter.

A LOCOS film 37 for element isolation is formed on the surface of the epitaxial layer 36. The film thickness of the LOCOS film 37 is 1 to 1.5 μm. LOCOS
The film 37 is provided to electrically separate the NPN transistor 32 from the NPN transistor 33 or the PNP transistor 34.

If the film thickness of the LOCOS film 37 is smaller than the film thickness of the epitaxial layer 36, the breakdown voltage between the silicon substrate 31 and the P type diffusion layer is lowered. Here, the P-type diffusion layer is a base layer 47, 4 of NPN transistors 32, 33 described later.
8, external base layer 49, base contact layer 50, and P
The emitter layer 51 and the collector layer 5 of the NP transistor 34
Refers to 2. Further, a parasitic PNP transistor formed by the silicon substrate 31, the epitaxial layer 36 and the P type diffusion layer is formed.

When the parasitic PNP transistor is formed,
A leak current between the silicon substrate 31 and the P-type diffusion layer increases, or a latch-up phenomenon occurs, which deteriorates the characteristics.

Next, in a predetermined region on the silicon substrate 31,
A P-type polysilicon film is formed. The polysilicon film 38 is an injector lead electrode serving as a base lead electrode 38a of the NPN transistor 32, a base lead electrode 38b of the NPN transistor 33, and an emitter lead electrode 38c of the PNP transistor 34. Here, the base extraction electrode 38b is P
It also serves as a collector extraction electrode of the NP transistor 34. Further, the polysilicon film 38 constitutes a base lead electrode 38d of the NPN transistor 32 and a base lead electrode 38e of the NPN transistor 33. The base extraction electrodes 38d and 38e are provided to reduce the respective base resistances.

The thickness of this polysilicon film 38 is 400 n.
m, the sheet resistance is about 100Ω / □. The thickness of the polysilicon film 38 is 300 to 500 nm. When the thickness of the polysilicon film 38 is 300 nm or less,
The sheet resistance will increase. Conversely, the polysilicon film 38
When the film thickness is 500 nm or more, the step difference on the substrate surface increases. The sheet resistance of the polysilicon film 38 is 70 to 1
Used at 30Ω / □. If the sheet resistance of the polysilicon film 38 is 130Ω / □ or more, the base resistance increases. As a result, the operating speed of the device is reduced.

The sheet resistance of the polysilicon film 38 is 70Ω.
If it is / square or less, the impurity concentration of the external base layer formed by diffusion from the polysilicon film 38 becomes large and the external base layer becomes deep. As a result, the breakdown voltage of the device is lowered, and the operating speed of the device is lowered.

Further, the polysilicon film 38 has 1-1.1.
An opening 39 having a width of 5 μm is formed. At this time, if the width of the polysilicon film 38 is 1 μm or less, processing variations in pattern formation are likely to occur, resulting in variations in element characteristics. If the thickness is 1.5 μm or more, the capacity increases and the operation speed of the element decreases.

The inner wall of the opening 39 has a film thickness of 50 to 120 n.
A nitride film 40 of m is formed. Here, if the film thickness of the nitride film 40 is 50 nm or less, the parasitic capacitance that decreases the operation speed of the device increases. In addition, it is difficult to electrically insulate the element, which reduces the reliability of the element. On the other hand, if the film thickness is 120 nm or more, the stress of the film causes
The element characteristics will deteriorate.

The nitride film 40 in the regions where the respective contacts of the NPN transistors 32 and 33 are formed is removed, and the underlying silicon substrate 31 is exposed.

At this time, the nitride film 40 in the region of the PNP transistor 34 remains without being removed.

A polysilicon film is formed on the side wall of the nitride film 40. The polysilicon film in the regions where the contacts of the NPN transistor 32, the NPN transistor 33, and the PNP transistor 34 are formed is removed, and the polysilicon sidewall 41 is formed. Here, the opening width of the nitride film 40 formed in the NPN transistor 32 and the NPN transistor 33 is equal to the opening width of this polysilicon film. The width of the polysilicon sidewall 41 is about 200 nm.

Here, the width of the polysilicon side wall 41 needs to be optimized in accordance with the impurity concentration profile of each diffusion layer and the accuracy of processing equipment. Here, each diffusion layer refers to an external base layer 49, an intrinsic base layer 47, an emitter layer 53, a base collector layer 50, and a collector layer 54, which will be described later. If the polysilicon sidewall 41 is thick, the breakdown voltage of the device will be reduced. Also, the base resistance increases. If the film thickness is thin, the operation speed of the device becomes slow.
Here, the base resistance refers to the resistance of the intrinsic base layer 47, specifically, the resistance of the region where the intrinsic base layer 47 and the external base layer 49 overlap.

In the drawing, PNP transistor 34 and LO
Although the polysilicon sidewall 41 is formed on the COS film 37, it is not always necessary to form it here.

As described above, the polysilicon side wall 4 is formed.
1 and the nitride film 40 are opened to form an emitter lead-out opening 42 of the NPN transistor 32 and a collector lead-out opening 43 of the NPN transistor 33.

Here, the emitter lead-out portion opening 42 and the collector lead-out portion opening 43 are connected to the base lead-out electrodes 38a, 3a.
The distance to 8b is about 300 nm. That is,
It is formed in a self-aligned manner so as to be equidistant at any position around each opening.

An emitter extraction electrode 44 and a collector extraction electrode 45 are formed in the emitter extraction portion opening 42 and the collector extraction portion opening 43, respectively. The emitter extraction electrode 44 and the collector extraction electrode 45 have a film thickness of 3
It is formed of a polysilicon film having a thickness of about 00 nm. The thickness of the polysilicon film can be 200 to 350 nm. If this film thickness is thicker than 350 nm, the resistance of the electrode will increase. On the other hand, if the film thickness is less than 200 nm, the current amplification factor of the NPN transistor 32 decreases.
Further, if the film thickness is thin, when ions are implanted into this polysilicon film in order to reduce the resistance of the electrode, the ions penetrate the polysilicon film and are introduced into the region in the silicon substrate 31 where elements are formed. ..

At this time, the base extraction electrodes 38a, 38
CVD with a film thickness of 200 nm on b, 38d, and 38e
The oxide film 46 and the nitride film 40 are formed around it. As a result, the base extraction electrodes 38a, 38b,
38d and 38e are electrically separated from the emitter extraction electrode 44 or the collector extraction electrode 45.

The thickness of the CVD oxide film 46 is 150 to 3
It is good to set it to 00 nm. If the film thickness is thin, the parasitic capacitance will increase. Further, if the film thickness is large, the step difference on the substrate surface becomes large.

A P-type intrinsic base layer 47 of the NPN transistor 32 is formed in the epitaxial layer 36. The junction depth of the intrinsic base layer 47 is about 0.15 μm, and its surface concentration is about 1 × 10 ¹⁹ cm ⁻³ . The optimal junction depth of the intrinsic base layer 47 is about 0.1 to 0.20 μm. If it is thinner than this, the breakdown voltage of the device will be reduced. On the other hand, if the thickness is thicker than this, the operation speed of the element will be slow.

The surface concentration of the intrinsic base layer 47 is 5 ×.
It is preferable to use it in the range of 10 ^{18 to} 2 × 10 ¹⁹ cm ⁻³ . If the surface concentration is lower than this, the breakdown voltage of the element is lowered, and the base resistance of the intrinsic base layer 47 increases. If the surface concentration is high, the current amplification factor of the NPN transistor 32 is lowered, and the operating speed thereof is lowered.

Further, in the epitaxial layer 36, NP
The P-type base layer 48 of the N-transistor 33 is formed. The junction depth of the base layer 48 is about 0.5 μm, and the surface concentration is (1 to 3) × 10 ¹⁷ cm ⁻³ . It is appropriate that the junction depth of the base layer 48 is 0.4 to 0.7 μm. If the junction depth is shallower than this, the thickness of the epitaxial layer 36 having a low impurity concentration becomes thick. If it is thick, the operating speed of the device is reduced and the operating margin of the device is reduced. On the contrary, if the junction depth is deep, the junction capacitance increases, and the operating speed of the device also decreases. That is, in order to control the thickness of the epitaxial layer 36, it is necessary to accurately control the junction depth of the base layer 48.

Similarly, the impurity concentration of the base layer 48 is also an important factor. When the surface concentration of the base layer 48 is 1 × 10 ¹⁷ cm ⁻³ or less, the breakdown voltage of the device is lowered, and the margin for manufacturing variations is reduced.
If the surface concentration is 3 × 10 ¹⁷ cm ⁻³ or more, the junction capacitance increases and the operation speed of the device decreases.

A P-type external base layer 49 is formed in the element region immediately below the base extraction electrode 38a of the NPN transistor 32. The outer base layer 49 has a junction depth of about 0.3 μm and a surface concentration of (1 to 3) × 10.
It is formed to have a ^size of ²⁰ cm ^-3 . External base layer 4
The junction depth of 9 is preferably set to a value of 0.2 to 0.35 μm. The surface concentration of the external base layer 49 is 1 × 10 ²⁰ cm ^-3
Or less, or the junction depth of the external base layer 49 is 0.2
When it is less than μm, the base resistance increases and the breakdown voltage of the element decreases. The surface concentration is 3 × 10 ²⁰ cm
^-3 or more, the junction depth of the external base layer 49 is 0.35 μm
If it is above, the operating speed of the element is reduced.

A P-type base contact layer 50 of the NPN transistor 33 is formed in the element region immediately below the base extraction electrode 38b of the NPN transistor 33. The base contact layer 50 has a junction depth of 0.3 μm.
The surface concentration is (1 to 3) × 10 ²⁰ cm ⁻³ . Here, the base extraction electrode 38b is a PNP.
It also serves as a collector extraction electrode of the transistor 34.

The junction depth and the surface concentration of the base contact layer 50 are 0.3 μm because they are formed at the same time as the external base layer 49 of the NPN transistor 32. Therefore, the manufacturing conditions are exactly the same as those for the external base layer 49, and the junction depth is preferably 0.2 to 0.35 μm.

The P-type emitter layer 51 of the PNP transistor 34 is formed in the element region immediately below the injector extraction electrode which becomes the emitter extraction electrode 38c of the PNP transistor 34.
And a P-type collector layer 52 are formed. The junction depth between the emitter layer 51 and the collector layer 52 and the surface concentration are NP.
Since it is formed at the same time as the external base layer 49 of the N-transistor 32, the junction depth is also 0.2 to 0.3 μm and the surface concentration is (1 to 3) × 10 ²⁰ cm ⁻³ .

As described above, the outer base layer 49, the base extraction electrode 38b, the emitter extraction electrode 38c, the emitter layer 51 and the collector layer 52 all have a junction depth of about 0.2 to 0.3 μm. And the surface density is (1-3) ×
It is 10 ²⁰ cm ^-3 .

Furthermore, a P-type intrinsic base layer 47 formed below the emitter extraction electrode 44 of the NPN transistor 32.
The N-type emitter layer 53 has a junction depth of 0.05 μm.
The surface concentration is about 3 × 10 ²⁰ cm ⁻³ . The junction depth of the emitter layer 53 is 0.03 to 0.08 μm.
Set to. The surface concentration of the emitter layer 53 is preferably (2-5) × 10 ²⁰ cm ^-3 . If the surface concentration of the emitter layer 53 is 2 × 10 ²⁰ cm ⁻³ or less or the junction depth is 0.03 μm or less, the parasitic resistance increases and the operating speed of the element decreases. Further, if the surface concentration is 5 × 10 ²⁰ cm ⁻³ or more or the junction depth is 0.08 μm or more, the parasitic capacitance becomes large this time, and the operating speed of the device also decreases.

An N-type collector layer 54 is formed in the base layer 48 formed below the collector extraction electrode 45 of the NPN transistor 33. The collector layer 54 has a junction depth of 0.05 μm and a surface concentration of 3 × 10 ²⁰ cm ^−3.
It is a degree.

The collector layer 54 is formed at the same time as the emitter layer 53. Therefore, the junction depth is 0.03 ~
0.08 μm is suitable and the surface concentration is (2-5) × 10 ²⁰
It is ^recommended to use at cm ^-3 . Similarly, the surface density is 2 ×
10 ²⁰ cm ^-3 or less, or junction depth is 0.03 μm
If it is below, the parasitic resistance increases and the operation speed of the element decreases. If the surface concentration is 5 × 10 ²⁰ cm ⁻³ or less or the junction depth is 0.08 μm or more, the parasitic capacitance increases and the operating speed of the device also decreases.

The lateral diffusion length of each diffusion layer is about 80% in the depth direction. The emitter lead-out portion opening 42, the collector lead-out portion opening 43, the base lead-out electrode 38a,
The distance from 38b is maintained at about 300 nm. Therefore, the intrinsic base layer 47 and the external base layer 49 of the NPN transistor 32 have a sufficient impurity concentration so that the breakdown voltage of the element is not lowered and the resistance is not increased by the parasitic resistance. It needs to be overlapped. Further, since the respective electrodes are formed apart from the respective openings by a predetermined distance, the outer base layer 49 and the base contact layer 50 are formed in the emitter layer 53.
It is possible to avoid entering the region of the collector layer 54. The outer base layer 49 and the base contact layer 50
However, if it gets into the emitter layer 53 and the collector layer 54, the breakdown voltage of the element is lowered and further the leak is increased. Also,
The operating speed of the device also decreases.

Next, one embodiment of the method of manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to the step-by-step sectional views of FIGS.

First, as shown in FIG. 2A, the specific resistance 10
A window is opened in a predetermined region of a resist (not shown) on the surface of the (111) or (100) P-type silicon substrate 61 at about Ωcm by using photolithography. Arsenic or antimony ions are implanted using this resist as a mask. Ion implantation is performed in a dose amount (1-2) × 10
^An acceleration energy of 40 to 60 keV was used at ¹⁵ cm ^-2 . Next, the resist is removed by plasma ashing using oxygen gas. After that, heat treatment is performed at a temperature of 1200 ° C. for about 30 minutes. As a result, the junction depth is 1-2 μm.
Then, the N-type buried layer 62 having a sheet resistance of 50 to 100 Ω / □ is formed. The buried layer 62 is a vertical NPN transistor 63 having a forward structure capable of operating at a very high speed.
Embedded collector layer 62, and the lateral P of the IIL element
It serves as a buried emitter layer of the vertical NPN transistor 64 having a reverse structure that also serves as the base extraction of the NP transistor 65.

Further, a thickness of 1 μm is formed on the silicon substrate 61.
m, and an N type epitaxial layer 66 having a specific resistance of about 0.5 Ωcm is grown. The epitaxial layer 66 is formed under conditions of a temperature of 1050 ° C., a pressure of about 80 Torr, a gas of dichlorosilane (SiH ₂ Cl ₂ ) and arsine (As).
H ₃ ) mixed gas was used.

Next, a silicon nitride film is formed on the epitaxial layer 66. The silicon nitride film was grown by low pressure CVD using a mixed gas of dichlorosilane and ammonia (NH ₃ ) as a gas. Here, the film thickness of the silicon nitride film is about 120 nm.

Next, a predetermined resist pattern (not shown) is provided on the silicon nitride film by photolithography. Using this resist pattern as a mask, the silicon nitride film is removed by dry etching. Dry etching is performed using a mixed gas of Freon gas and bromine gas. By this etching, the silicon nitride film at the position where the element isolation region is formed is removed. Next, a silicon groove is formed in the epitaxial layer 66 by dry etching. Dry etching uses sulfur hexafluoride (SF
₆ ) Use gas. The depth of the silicon groove is set to be slightly larger than half the thickness of the epitaxial layer 66, here about 0.6 μm.

Further, the resist is removed by using oxygen plasma ashing. After that, the LOCOS film 67 for element isolation is formed by high pressure pyrooxidation at a pressure of about 8 atm. The LOCOS film 67 can be selectively formed by growing it using a silicon nitride film as a mask. At this time, the film thickness of the LOCOS film 67 was set to 1 to 1.5 μm.

In this way, the LOCOS film 67 is formed in the silicon trench.
When the above is formed, the film thickness of the LOCOS film 67 for reaching the silicon substrate 61 can be set to about half that in the case where there is no silicon groove. At this time, the bottom surface of the LOCOS film 67 is located below the bottom surface of the epitaxial layer 66. As described above, the LOCOS film 67 may have a thickness that is half the normal thickness, so that the oxidation time at the time of forming the LOCOS film 67 can be shortened. Therefore, it is possible to prevent impurities from rising from the buried layer 62 to the epitaxial layer 67 due to the heat treatment during oxidation.

Further, when the LOCOS film 67 is normally grown, the oxidized silicon expands. When the silicon groove is provided, the upper surface of the formed LOCOS film 67 substantially coincides with the surface of the epitaxial layer 66. That is, LO
The COS film 67 is filled in the silicon trench. Therefore, L
It is possible to suppress unevenness on the substrate surface caused by the formation of the OCOS film 67. If the surface has irregularities, the material to be etched remains in the concave portions or the step portions by anisotropic etching performed in a later step.

Here, the reason why the high-pressure pyrooxidation method is used is that the pyrooxidation can achieve an oxidation rate that is the same as or higher than that at a high temperature of about 1200.degree. Therefore, it is possible to prevent impurities in the buried layer 62 from rising to the epitaxial layer 66 and being diffused by the heat treatment. Thus, the epitaxial layer 6
If the diffusion of impurities into 6 is suppressed, the breakdown voltage of the device can be prevented from lowering.

Further, the silicon nitride film is removed by using phosphoric acid solution. After that, in the element region surrounded by the LOCOS film 67, the NPN transistor 64 in the IIL element is formed.
Ion implantation of boron is performed in the element region in which the element is formed. This ion implantation is selectively performed using a resist formed by photolithography as a mask. This ion implantation condition has an acceleration energy of 100 to 160 k.
The dose amount is about 5 × 10 ¹² to 2 × 10 ¹³ cm ⁻² at eV. After that, the resist is removed by using oxygen plasma ashing. Next, in a nitrogen gas atmosphere, the temperature is 900 ° C.
Then, annealing treatment is performed for about 30 minutes. As a result, NP
The base layer 68 of the N-transistor 64 is formed.

Next, as shown in FIG. 2B, the base extraction electrode of the NPN transistor 63 and the NPN transistor 64.
A polysilicon film 69 to be a base extraction electrode and an injector extraction electrode is formed. The polysilicon film 69 is
Film thickness 400 nm by low pressure CVD using silane gas
Form to a degree. Then, an oxide film 70 to be an insulating film between the polysilicon electrodes is grown to a film thickness of about 250 nm. The oxide film 70 is formed by low pressure CVD using a mixed gas of dichlorosilane gas and N ₂ O gas.

After that, the outside of the NPN transistor 63 is
Base contact of the NPN transistor 64
Layer, the emitter layer of the PNP transistor 65 and the collector
Boron, which is a diffusion source of impurities in the silicon layer, is ion-implanted. I
ON implantation is a dose amount of 1 × 10 ¹⁶cm^-2And acceleration energy
Gee is performed at about 60 keV. Ion injection under such conditions
When the boron is turned on, the boron passes through the oxide film 37 and becomes a policy.
Ions are implanted into the recon film 69.

Ions are implanted into the polysilicon film 69 after the oxide film 70 is formed in order to prevent boron from being introduced into the surface of the epitaxial layer 66. That is, when the oxide film 70 is grown by low pressure CVD, heat treatment at a temperature of about 800 ° C. is performed. At this time, if boron is already ion-implanted into the polysilicon film 69, the boron is solid-phase diffused and introduced into the surface of the epitaxial layer 66. When boron is introduced, NP
In the N transistors 63 and 64, even if an attempt is made to form a shallow base layer in a later step, the base layer becomes deep. As a result, the high frequency characteristics of the device deteriorate. Also, PN
In the P-transistor 65, the introduced boron easily causes the collector-emitter leakage.

Next, using the resist pattern (not shown) having a width of 1 to 2 μm as a mask, dry etching is performed in a mixed gas of CHF ₃ , ammonia and oxygen to remove the oxide film 70. In addition, SF ₆ and C ₂ Cl
The polysilicon film 69 is anisotropically etched and removed using a mixed gas with F ₅ . In this way, each polysilicon electrode is formed, and at the same time, the NPN transistor 63,
The base 71 of 64 and the PNP transistor 65
A region 72 serving as a base of is opened. Next, the resist pattern is removed by oxygen plasma ashing. After this,
A 120 nm-thickness silicon nitride film 73 is grown on the entire surface. The silicon nitride film 73 is grown by low pressure CVD using a mixed gas of dichlorosilane and ammonia.

The silicon nitride film 73 electrically insulates each polysilicon electrode. Therefore, a sufficient film thickness is required for reliability. However, if the film thickness is too thick, the element characteristics are deteriorated by the stress of the silicon nitride film 73. Therefore, the film thickness of the silicon nitride film 73, which has sufficient insulation characteristics and does not deteriorate due to stress, is 50 to 120 nm.

Then, in a nitrogen gas atmosphere, the temperature is set to 100.
Heat treatment is performed at about 0 ° C. for 30 to 60 minutes. By this
The boron impurities in the polysilicon film 69 are epitaxy.
Diffuses to the surface of the rule layer 66. In this way NPN tiger
Base contact layers of transistors 63 and 64 and PNP transistors.
P which becomes an emitter layer and a collector layer of the transistor 65. ⁺
The mold diffusion layer 74 is formed. Each diffusion layer has a junction depth
Is about 0.3 μm, and the surface concentration is (1 to 3) × 10²⁰c
m^-3It is a degree.

Next, as shown in FIG. 2C, a polysilicon film is grown on the entire surface of the silicon nitride film 73. The polysilicon film is grown at a thickness of about 200 to 300 nm by low pressure CVD using silane gas. After this,
Extremely anisotropic etching is performed on the polysilicon film. The anisotropic etching can be realized by performing in a mixed gas of SF ₆ and CCl ₄ . In this way, the polysilicon side wall 75 is formed. Using the polysilicon side wall 75 and a resist (not shown) formed by photolithography as a mask, the silicon nitride film 73 is etched in a mixed gas of CF ₄ , CHBr _3, and O ₂ . In this manner, the emitter lead-out opening 76 of the NPN transistor 63 and the collector lead-out opening 77 of the NPN transistor 64 are equidistant from the polysilicon film 69 serving as the base lead-out electrode at any position around the opening. Form in a self-aligned manner.

Here, in order to form the emitter leading-out portion opening 76 and the collector leading-out portion opening 77 in a self-aligned manner, a double layer of the silicon nitride film 73 and the polysilicon side wall 75 is used. The reason is that when the emitter junction of the NPN transistor 63 and the collector junction of the NPN transistor 64 are covered with the silicon nitride film 73, the effect as a protective film can be expected. That is, it is possible to prevent impurities from entering the peripheral portion of the emitter junction of the NPN transistor 63 from the film formed in the subsequent steps in which the silicon nitride film 73 is formed and the external atmosphere. If this impurity is trapped in the interface state existing near the surface around the emitter junction, the current amplification factor of the device is deteriorated and the reliability of the device is adversely affected. Further, since the coefficient of thermal expansion of polysilicon is the same as that of the silicon substrate, the stress of the polysilicon sidewall 75 is much smaller than that of the silicon nitride film 73. Therefore, the silicon nitride film 73 is made as thin as possible, and the thickness is compensated by the polysilicon sidewalls 75. As a result, the reliability of the element is not deteriorated by the stress of the silicon nitride film 73.

Finally, as shown in FIG. 2D, a polysilicon film is used to form a polysilicon electrode 78 serving as an emitter extraction electrode of the NPN transistor 63 and a collector extraction electrode of the NPN transistor 64. The polysilicon film is grown to a thickness of about 300 nm by low pressure CVD using silane gas. Further, the polysilicon electrode 78 is formed by etching the polysilicon film using a resist used in photolithography as a mask and using a mixed gas of SF ₆ and C ₂ ClF ₅ .

After that, boron is ion-implanted into the polysilicon electrode 78 using the resist pattern used for opening the region of the polysilicon electrode 78 as a mask.

After that, the resist is removed by oxygen plasma ashing. Next, heat treatment is performed in a nitrogen atmosphere. By this heat treatment, the boron impurities in the polysilicon electrode 78 are diffused to the surface of the epitaxial layer 66 through the emitter extraction portion opening 76 and the collector extraction portion opening 77. Due to the boron diffused on the surface of the epitaxial layer 66, the P-type base layer 7 of the NPN transistor 63 is formed.
9 is formed.

Further, a resist pattern which is exposed and developed is formed so as to open the region of the polysilicon electrode 78. Arsenic is ion-implanted into the polysilicon electrode 78 using this resist pattern as a mask. Ion implantation is
Acceleration energy is 40 to 80 keV and dose is 5 ×
It is performed at 10 ^{15 to} 2 × 10 ¹⁶ cm ^-2 .

After that, the resist is removed by oxygen plasma ashing. Next, heat treatment is performed in a nitrogen atmosphere. By this heat treatment, the arsenic impurity in the polysilicon electrode 78 is diffused to the surface of the epitaxial layer 66 through the emitter leading portion opening 76 and the collector leading portion opening 77. By the arsenic diffused on the surface of the epitaxial layer 66, the N-type emitter layer of the NPN transistor 63 and I
An N ⁺ diffusion layer 80, which will be the N-type collector layer of the NPN transistor 64 in the IL element, is formed.

Here, when boron ions are implanted into the polysilicon electrode 78 of the NPN transistor 63, the boron is prevented from penetrating the polysilicon electrode 78.
Therefore, the ion implantation condition is that the acceleration energy is 30 ke
V or less and the dose amount is (2 to 4) × 10 ¹⁴ cm ^-2
I am trying. After this, at a temperature of 900 to 950 ° C., 30 to
By heat treatment for about 60 minutes, the surface concentration is 1 × 10 ¹⁹ c
NP with a diffusion depth of about 0.1 to 0.15 μm at about m ^-3
A P-type base layer 79 of N transistor 63 is formed.

The N ⁺ diffusion layer 80 is heat treated at a temperature of 90.
At 0 ° C for about 30 minutes, the surface concentration should be 3 × 10 ²⁰ c
The depth can be set to about m ⁻³ and the depth can be set to 0.05 μm or less. Since the lateral diffusion length of each diffusion layer is about 80% in the depth direction, the P ⁺ diffusion layer 74 has a sufficient impurity concentration with the base layer 79 around the emitter extraction opening 76. , Can be overlapped. At the same time, it is possible to prevent the N ⁺ diffusion layer 80 and the P ⁺ diffusion layer 74 from being joined. Since the diffusion layers 74 and 80 have a high impurity concentration, when they are joined, a tunnel current is generated. Therefore, leakage current occurs in the reverse bias state, and the linearity of the current amplification factor of the element deteriorates in the forward bias state. In order to prevent this, it is desirable that the impurity concentration of one diffusion layer be 1 × 10 ¹⁸ cm ⁻³ or less.

As described above, the boron ion-implanted into the polysilicon electrode 78 of the NPN transistor 63 is diffused through the emitter extraction opening 76 by heat treatment to form the P-type base layer 79. Therefore, NP
The base layer 79 of the N-transistor 63 can be made extremely shallow.

By anisotropically etching the polysilicon film 69, the base region 71 of the NPN transistor is damaged. The anisotropic dry etching of the polysilicon film 69 is performed by using the base extraction electrode of the NPN transistor 63, the base extraction electrode of the NPN transistor 64 which also serves as the collector extraction electrode of the PNP transistor 65, and the injector extraction electrode serving as the emitter extraction electrode of the PNP transistor 65. Is used to form the. The damage formed in the base region 71 as described above reaches the inside of the substrate by the ion implantation when forming the base layer 79. If this extends to the junction of the diffusion layer and the junction is reverse-biased, there arise problems such as an increase in leak current and a reduction in manufacturing yield.

This can be avoided by using diffusion from the polysilicon film. The step of forming the base layer 68 of the NPN transistor 64 forming the IIL element by ion implantation must be placed before the step of forming the polysilicon electrode by anisotropic dry etching of the polysilicon film 69 for the same reason.

The base layer 68 of the NPN transistor 64 is formed relatively deep. Therefore, as in the NPN transistor 63, if it is formed by boron diffusion from the polysilicon electrode 78, an extremely shallow base layer 68 is formed. If the base layer 68 is shallow, the thickness of the epitaxial layer 66 having a low impurity concentration, which serves as an emitter, increases.
This reduces the operating speed of the device.

From the above, after forming the base electrode,
When the base layer 68 of the NPN transistor 64 is formed by using ion implantation, a problem of damage due to ion implantation occurs. On the other hand, when the diffusion is performed from the polysilicon film instead of the ion implantation, there is a problem that the depth of the base layer 68 becomes shallow. Here, as in the present embodiment, by forming the base layer 68 of the NPN transistor 64 by ion implantation and then forming the base electrode, problems regarding damage and the depth of the base layer can be solved.

[0094]

As described above, according to the semiconductor integrated circuit and the method of manufacturing the same of the present invention, the reverse vertical transistor forming the IIL element can also be formed by the self-alignment process,
The self-aligned ultra-high speed transistor and the IIL element can be integrated on the same chip. In addition, the base layer of the reverse vertical transistor that constitutes the IIL element can form a deeper junction than the ultra-shallow base layer of the self-aligned ultra-high speed transistor formed by impurity diffusion from the polysilicon emitter electrode. The low-concentration epitaxial layer portion below the base layer forming the emitter of the vertical directional transistor can be made small. Therefore, it is possible to avoid a decrease in the current amplification factor of the reverse vertical transistor, which is related to the low-concentration epitaxial layer portion below the base layer that serves as an emitter in the reverse vertical transistor, and a decrease in high-speed operation of the IIL due to the accumulation of minority carriers. be able to.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

2A to 2C are cross-sectional views in order of the processes, showing the method for manufacturing the same semiconductor integrated circuit.

FIG. 3 is a circuit diagram showing a configuration of a conventional IIL element.

4A to 4C are cross-sectional views in order of the processes, showing the configuration of a conventional self-aligned ultra-high speed transistor and a method of manufacturing the same.

[Explanation of symbols]

 31 silicon substrate 32, 33 NPN transistor 34 PNP transistor 35 buried layer 35a collector layer 35b emitter layer 36 epitaxial layer 37 LOCOS film 38 polysilicon film 38a, 38b, 38d, 38e base extraction electrode 38c emitter extraction electrode 39 opening 40 nitride film 41 Polysilicon sidewall 42 Emitter extraction part opening 43 Collector extraction part opening 44 Emitter extraction electrode 45 Collector extraction electrode 46 CVD oxide film 47 Intrinsic base layer 48 P-type base layer 49 External base layer 50 Base contact layer 51 Emitter layer 52 Collector Layer 53 Emitter layer

Claims (11)

[Claims] 1. At least a first vertical semiconductor element having a forward structure and a second vertical semiconductor element having a reverse structure of an IIL element on a semiconductor substrate of a first conductivity type. A second conductive type emitter layer of the first vertical semiconductor element, a second conductive type collector layer of the second vertical semiconductor element, and a first conductive type of the first vertical semiconductor element. Type external base layer and a first conductivity type base contact layer of the second vertical semiconductor device, the emitter layer and the external base layer are formed in a self-aligned manner, and the collector layer A semiconductor integrated circuit device, wherein the base contact layer and the base contact layer are formed in a self-aligned manner. 2. A lateral semiconductor element is formed on the semiconductor substrate, the diffusion depth and the impurity concentration of the emitter layer and the collector layer are substantially the same, and the external base layer and the base contact layer are formed. 2. The semiconductor integrated circuit device according to claim 1, wherein the junction depth and the impurity concentration of the emitter layer of the lateral semiconductor element and the collector layer of the lateral semiconductor element are substantially the same. 3. The semiconductor integrated circuit device according to claim 1, wherein the junction depth between the emitter layer and the collector layer is 0.03 to 0.08 μm. 4. The junction depth between the external base layer, the base contact layer, the emitter layer of the lateral semiconductor element and the collector layer of the lateral semiconductor element is 0.2 to 0.3 μm. The semiconductor integrated circuit device according to claim 1. 5. A semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and two second semiconductor layers formed in the peripheral portion of the first and second semiconductor element regions in the semiconductor layer. A first conductivity type first diffusion layer, a first conductivity type first polycrystalline semiconductor film formed as an extraction electrode of the first diffusion layer, and a second diffusion layer formed between the first diffusion layers. A second diffusion layer of a conductive type and a second polycrystalline semiconductor film of a second conductive type formed as an extraction electrode of the second diffusion layer are provided, and the first semiconductor element region is provided with the first semiconductor element region. A third diffusion layer of the first conductivity type formed shallower than the junction depth of the first diffusion layer and a first conductivity type formed in the second semiconductor element region deeper than the depth of the first diffusion layer. A semiconductor integrated circuit device comprising a fourth diffusion layer. 6. The first diffusion layer and the third diffusion layer of the first semiconductor element region overlap each other,
The semiconductor integrated circuit device according to claim 5, wherein the overlapping regions have the same impurity concentration. 7. A first insulating film (1) in which the second polycrystalline semiconductor film is formed on a sidewall of the first polycrystalline semiconductor film.
7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is formed at least in an opening having sidewalls 2) and a third polycrystalline semiconductor film provided on the first insulating film. 8. The depth of the isolation oxide film for electrically isolating the first semiconductor element region and the second semiconductor element region is deeper than the depth of the semiconductor layer. Semiconductor integrated circuit device. 9. The junction depth of the third diffusion layer is 0.1 to 0.1.
The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device has a thickness of 20 μm. 10. A step of forming a second conductive type semiconductor layer on a first conductive type semiconductor substrate, and forming a first conductive type first diffusion layer in a first semiconductor element region of the semiconductor layer. And a step of forming a first polycrystalline semiconductor film on the semiconductor substrate, a step of forming a first insulating film on the first polycrystalline semiconductor film, and the first polycrystalline semiconductor First on the membrane
A step of introducing a conductive type first impurity; a step of selectively etching away the first insulating film and the first polycrystalline semiconductor film to form a first opening; and at least the first opening. Forming a second insulating film in the first opening; introducing the first impurity into the semiconductor layer to form a second diffusion layer of the first conductivity type; and the second insulating film. Second on the membrane
Forming an opening in the second opening, a step of growing a second polycrystalline semiconductor film in the second opening, and the second polycrystal in a second semiconductor element region other than the first semiconductor element region. A step of selectively introducing a second impurity of the first conductivity type into the semiconductor film; and a step of introducing the second impurity into the semiconductor layer through the second opening to form a third diffusion layer. ,
The second conductive type third layer is formed on all the second polycrystalline semiconductor films.
And a step of introducing the third impurity into the semiconductor layer through the second opening to form a fourth diffusion layer of the second conductivity type. Manufacturing method of integrated circuit device. 11. A step of forming a second conductive type semiconductor layer on a first conductive type semiconductor substrate, and forming a first conductive type first diffusion layer in a first semiconductor element region of the semiconductor layer. And a step of forming a first polycrystalline semiconductor film on the semiconductor substrate, a step of forming a first insulating film on the first polycrystalline semiconductor film, and the first polycrystalline semiconductor First on the membrane
A step of introducing a conductive type first impurity; a step of selectively etching away the first insulating film and the first polycrystalline semiconductor film to form a first opening; and at least the first opening. Forming a second insulating film in the first opening; introducing the first impurity into the semiconductor layer to form a second diffusion layer of the first conductivity type; and the second insulating film. Forming a second polycrystalline semiconductor film on the film; forming a second opening in the second insulating film and the second polycrystalline semiconductor film; and at least in the second opening. A step of growing a third polycrystalline semiconductor film, and a second impurity of the first conductivity type selectively in the third polycrystalline semiconductor film in the second semiconductor element region other than the first semiconductor element region And introducing the second impurity into the semiconductor layer through the second opening, A diffusion layer of the second conductivity type, a step of introducing a third impurity of the second conductivity type into all at least the third polycrystalline semiconductor film, and a step of introducing the third impurity into the semiconductor through the second opening. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a fourth diffusion layer of the second conductivity type by introducing it into a layer.