JPH05190683A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To completely remove insulating compound on a surface of lower layer wiring to be exposed with a through hole when an SOG film is used to flatten a multilayer wiring structure. CONSTITUTION:After through holes are formed at interlayer insulating film 102, 103, 104 flattened on lower layer wiring 105, the lower layer wiring exposed with the hole by using chlorine series gas is etched to a depth of 500-1000Angstrom , further sputter-etched with argon ions in a sputtering apparatus, and then upper layer wiring is immediately formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a multi-layer wiring.

[0002]

2. Description of the Related Art With the high integration and high density of LSIs, it is important to make the wiring multi-layered, and it is extremely important to flatten the wiring when forming a multi-layered wiring structure.

A manufacturing process of a wiring region of a conventional semiconductor device having a multilayer wiring will be described with reference to FIG.

A semiconductor substrate 201 on which a transistor and a first-layer aluminum-based alloy wiring 205 have already been formed.
On top of it, for example, plasma enhanced SiO 2 is formed by the CVD method.
₂ (hereinafter referred to as PE-SiO ₂ ), a lower insulating film 202 is formed, and then an SOG film 203 is formed by spin coating, and then the upper insulating film 20 of PE-SiO ₂ is formed by a CVD method.
4 is formed. (FIG. 2a) Thereby, the planarized interlayer insulating layer is formed.

Then, a through hole is opened by a known photolithographic etching technique using the resist film 206. (FIG. 2B) Subsequently, the resist film 206 is removed by performing sputter etching with argon ions in the sputtering apparatus, and the first layer aluminum alloy wiring 20 in the through hole is formed.
The oxide of aluminum on No. 5 was removed (FIG. 2c), and an aluminum-based alloy was formed by a sputtering method without being exposed to an oxygen atmosphere.
07 is formed. (Fig. 2d)

[0006]

However, in the method described above, when the organic SOG for planarization or the inorganic SOG using the polymer organic solvent is used as the SOG film 203, the through hole etching shown in FIG. 2B is performed. At times, a compound of aluminum, carbon, and fluorine is formed on the first-layer aluminum wiring 205 in the through hole, in addition to the native oxide film of aluminum. Therefore, the conventional sputter etching shown in FIG. 2C has a problem that the removal of the compound containing aluminum is incomplete, resulting in defective conduction of the through hole.

[0007]

In a method of manufacturing a semiconductor element, after forming a through hole, a chlorine-based gas is used to remove the surface of the first-layer aluminum wiring exposed in the through hole by 5 times.
Etching is carried out from 00Å to 1000Å, and the natural oxide of aluminum produced thereafter is removed by sputter etching with argon ions, and the second layer aluminum alloy is formed by sputtering without being exposed to an oxygen atmosphere.

[0008]

In order to eliminate the problem of defective conduction of the through hole due to the compound of Al, C and F on the surface of the lower layer wiring in the through hole in the above-mentioned prior art, the present invention forms the through hole by etching. After that, the first layer Al wiring is etched by chlorine gas to 500Å to 1000Å. As a result, the compound of Al, C and F in the through hole is removed, and a good through hole can be obtained even with the conventional sputter etching amount.

[0009]

EXAMPLE A manufacturing process according to the present invention will be described with reference to FIG.

A lower layer insulating film 102 such as PE-SiO ₂ is formed by a CVD method on a semiconductor substrate 101 on which a transistor and a first layer Al wiring 105 related thereto are already formed.
Film is formed, followed by forming an SOG film 103 for planarization, followed by forming the upper insulating film 104 for example PE-SiO ₂ film, an interlayer insulating film. (FIG. 1a) After that, a resist film 106 is formed thereon, and a through hole is opened by the known photolithography and etching technique using the resist film 106 as a mask. (FIG. 1b) Subsequently, after removing the resist film 106, the first layer Al wiring 105 in the through hole is etched with chlorine-based gas. The etching depth is 100Å to 500Å. (FIG. 1c) Subsequently, sputter etching is performed with Ar ions in the sputtering apparatus. The depth of the sputter etch is 100Å ~
Set to 500Å. (FIG. 1d) Subsequently, an Al alloy that is not exposed to an oxygen atmosphere, such as Al-
Second layer wiring 10 is produced by generating Si by a sputtering method.
7 (Fig. 1e)

[0011]

As described above in detail, according to the present invention, after etching the through hole, the depth of the first Al wiring layer in the through hole is reduced to 500Å to 100 by chlorine-based gas.
Since it removes up to 0Å, it is an insulator of Al and C
Then, or the compound of F is removed, and only the native oxide film of Al remains. The etching amount of sputter etching by Ar ions necessary for removing the natural oxide film is reduced, and good through-hole characteristics can be obtained.

Further, since the etching amount of the Ar ion sputter etching is reduced, the etching amount of the film of the interlayer insulating film is reduced, and it can be expected to reduce the short circuit between the wiring layers.

[Brief description of drawings]

FIG. 1 is a diagram showing a multi-layer wiring manufacturing process according to the present invention.

FIG. 2 is a diagram showing a conventional multilayer wiring manufacturing process.

[Explanation of symbols]

 101 Semiconductor Substrate 102 Lower Layer Insulating Film 103 SOG Film 104 Upper Layer Insulating Film 105 Lower Layer Wiring 107 Upper Layer Wiring

Claims (1)

[Claims] 1. A step of planarizing an interlayer insulating film using an SOG film on a surface of a semiconductor device having a multilayer wiring structure on an element formed on a semiconductor substrate, and a step of forming a through hole in the interlayer insulating film. In the method of manufacturing a semiconductor device having the above-mentioned method, after the through hole is formed, the surface of the first-layer aluminum wiring exposed in the through hole is removed by using a chlorine-based gas.
Manufacture of a semiconductor device characterized by sequentially performing a step of etching from 00Å to 1000Å and a step of forming a second layer aluminum wiring by sputtering an aluminum alloy without further exposing it to an oxygen atmosphere immediately after sputter etching with argon ions. Method.