JPH05190678A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress generation of a stress on a periphery of a replaced satisfactory macrocell and particularly at a divided groove part of a rear surface side in a method for manufacturing a semiconductor integrated circuit in which a defective macrocell of a plurality of macrocells disposed to be solidly laid in a chip area is removed, and the satisfactory macrocell is instead disposed to relieve a semiconductor chip. CONSTITUTION:The method for manufacturing a semiconductor integrated circuit device has the steps 3 of removing a defective macrocell of a plurality of macrocells disposed to be solidly laid in a chip area and disposing instead a satisfactory macrocell to replace the defective macrocell, thereby relieving a semiconductor chip. In the case of the step 3e of fixing the satisfactory macrocell to fix the satisfactory macrocell disposed instead of the defective macrocell, inorganic material is buried in a divided groove at a rear surface side by an optical CVD method thereby to fix the satisfactory macrocell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a chip repair technique in a manufacturing process of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A chip rescue technique in a manufacturing process of a semiconductor integrated circuit device is disclosed in, for example, Japanese Patent Application No. 2-3326.
There is a description in No. 04, and the outline is as follows.

First, in the first wiring process, the SOI
(Silicon On Insulator) structure semiconductor wafer (hereinafter,
A plurality of macro cells having the same circuit function are laid out in a chip area (which may be simply referred to as a wafer).

The macro cell is a basic circuit element for forming a semiconductor integrated circuit device in the chip area, and at this stage, the individual macro cells are electrically separated from each other.

In addition, a main surface side dividing groove is formed around the macro cell so as to reach the buried insulating layer of the wafer having the SOI structure or to a position slightly deeper than the buried insulating layer, and the inside of the groove is a dioxide. An insulating film made of silicon (SiO ₂ ) is embedded.

Next, the circuit function and electrical characteristics of each macro cell in the chip area are inspected. Then, after removing the insulating film in the main surface side dividing groove around the macro cell determined to be defective by the inspection, on the back surface of the SOI structure wafer, at a position corresponding to the periphery of the defective macro cell,
A back surface side dividing groove reaching the main surface side dividing groove is formed, and a defective macro cell is taken out.

Then, by a method similar to that for the defective macro cell, a good macro cell taken out from a wafer having another SOI structure, for example, is fitted in the position where the defective macro cell is taken out, and thereafter, a composite material such as polyimide is put in the dividing groove on the back surface side. The good macrocell is fixed by embedding the resin.

Thereafter, in the secondary wiring step, the macrocells in the chip area are electrically connected by wiring,
A predetermined semiconductor integrated circuit is formed in the chip area.

[0009]

However, the present inventor has found that the above-mentioned conventional technique has the following problems.

Conventionally, in order to fix a good macrocell,
Although a synthetic resin such as polyimide was embedded in the rear surface side dividing groove, the synthetic resin generally has a low glass transition point although it has a high fluidity (for example, in the case of polyimide, it is 300 to 400 ° C.). In addition, because of the characteristics such as high coefficient of thermal expansion, the volume of the synthetic resin in the rear surface side dividing groove increases at the time of a predetermined heat treatment step of manufacturing a semiconductor integrated circuit device, and as a result, the groove portion Stress is generated,
There is a problem that the reliability of the semiconductor integrated circuit device decreases.

Further, since the synthetic resin generally has a water content, it is easy for moisture to enter the main surface side of the semiconductor chip through the rear side dividing groove portion. Therefore, there is a problem that the reliability of the semiconductor integrated circuit device is lowered.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of suppressing the occurrence of stress in the rear surface side dividing groove.

Another object of the present invention is to provide a technique capable of suppressing the phenomenon that moisture invades into the main surface side of the semiconductor chip through the back surface side dividing groove portion.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the invention according to claim 1 is a wafer
Macro Cells with Same Circuit Function in Different Chip Areas
The primary wiring step for arranging the
It is judged by the inspection process and the quality inspection of the macro cell.
Around the defined defective macro cell, the main surface side of the wafer and
And the back surface side from the main surface side split groove and the back surface side, respectively
Defect macro cells can be taken out by forming dividing grooves
And the good macro cell at the position of the bad macro cell.
After inserting the
The step of embedding a device and fixing a good macrocell, and
After the defective macro cell replacement process, the macro cell in the chip area is
To form a predetermined semiconductor integrated circuit device.
Method for manufacturing semiconductor integrated circuit device having secondary wiring step
It is what

According to a second aspect of the present invention, in the step of fixing the good macrocell, a CVD method using tetraethoxysilane is used instead of burying an inorganic substance in the rear surface side dividing groove by the photo CVD method. A method for manufacturing a semiconductor integrated circuit device in which an inorganic material is embedded is provided.

According to a third aspect of the present invention, in the step of fixing the good macrocell, instead of burying the inorganic substance by the photo-CVD method in the rear surface side dividing groove, a sol-like or gel-like inorganic substance is used. This is a method of manufacturing a semiconductor integrated circuit device to be embedded.

[0019]

The inorganic substance generally has a high glass transition point, a high melting point, and a low coefficient of thermal expansion. Therefore, according to the above means for embedding an inorganic substance in the rear surface side division groove, it is possible to suppress the phenomenon that stress is generated in the rear surface side division groove portion in a predetermined heat treatment step of manufacturing a semiconductor integrated circuit device.

Further, since it is generally difficult for moisture to pass through the inorganic substance, it is possible to suppress the phenomenon that moisture penetrates into the main surface side of the semiconductor chip through the back surface side dividing groove portion.

[0021]

1 is a process diagram for explaining a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is an overall plan view of a wafer immediately after completion of a primary wiring process, and FIG. Figure 2
4 is an enlarged plan view of a chip region formed on the wafer of FIG. 4, FIG. 4 is an enlarged plan view of a macro cell formed in the chip region of FIG. 3, and FIG. 5 shows a shift register circuit portion formed in the macro cell of FIG. FIG. 6 is a circuit block diagram, FIG. 6 is a timing chart of clock signals for synchronizing the shift register circuit unit, FIG. 7 is a diagram showing signal levels of control lines during operation of the shift register circuit unit, and FIG. 8 is an input shift register. FIG. 9, FIG. 9 is an internal circuit diagram of the input shift register shown in FIG. 8, FIG. 10 is a symbol diagram of the output shift register, and FIG. 11 is an internal circuit diagram of the output shift register shown in FIG. 12 is a cross-sectional view of the main part of the wafer immediately after the completion of the primary wiring process, FIG. 13 is a cross-sectional view of the main part of the wafer during the macrocell inspection process, and FIGS. 16 is a plan view of the wafer shown in FIG. 15, FIG. 17 is a cross-sectional view of the main part of the wafer for explaining the wafer rear surface side dividing groove forming step, and FIG. 18 is a wafer FIG. 19 is a cross-sectional view of an essential part of a wafer for explaining a modified example of the rear surface side division groove forming method. FIG.
FIG. 20 is a cross-sectional view of essential parts of a wafer showing a state in which a good macro cell for replacement is arranged in a removal area of a bad macro cell,
22 is a sectional view of an essential part of the wafer for explaining the good macrocell fixing step, FIG. 22 is a sectional view of an essential part of the wafer for explaining the step of filling a groove on the main surface side of the wafer, and FIG. FIG. 4 is a cross-sectional view of the main part of the wafer.

In this embodiment, a method of manufacturing a logic LSI chip, for example, will be described. However, the semiconductor integrated circuit to be manufactured is not limited to the logic LSI and can be variously modified.

FIG. 1 shows the manufacturing process of the semiconductor integrated circuit device of the first embodiment. The manufacturing process of the semiconductor integrated circuit device according to the first embodiment includes, for example, the following four processes. That is, the first wiring process 1, the macrocell inspection process 2, the defective macrocell replacement process 3, and the secondary wiring process 4. Then, the defective macro cell replacement step 3 further includes, for example, seven steps described later.

First, FIG. 2 shows a plan view of the wafer immediately after the completion of the primary wiring step 1. The wafer 5 is made of, for example, silicon (Si) single crystal, and its diameter is, for example, about 6 inches. For example, 32 chip regions 6 are arranged on the main surface of the wafer 5. The size of each chip region 6 is, for example, about 20 mm × 20 mm.

An enlarged plan view of the chip area 6 is shown in FIG. In each chip area 6, for example, 400 macro cells 7 are spread. The size of each macro cell 7 is, for example, about 1 mm × 1 mm.

In each macrocell 7, an in-cell circuit having the same circuit function is formed. However, at this stage, wiring is not connected between the macro cells 7. That is, the intra-cell circuit in each macro cell 7 is in a circuit independent state.

An enlarged plan view of the macro cell 7 is shown in FIG. In the center of the macro cell 7, for example, the in-cell circuit region 8
Are arranged. In the cell circuit area 8 in the cell, for example, 3K
An in-cell circuit such as a gate array having about a gate is formed.

However, the circuit in the cell is not limited to the gate array and can be variously changed, for example, 16K.
An SRAM (Static RAM) of about b to 64 Kb or an analog circuit may be used.

A plurality of input / output circuit areas 9 are arranged on the outer periphery of the in-cell circuit area 8. A predetermined input / output circuit such as an input / output buffer is formed in each input / output circuit area 9.

In each input / output circuit area 9, a pad 1 is provided.
0 is placed. The pad 10 is the second wiring step 4
In, a pad for connecting between the macro cells 7.

The number N of the pads 10 is, for example, N = 1.9G0.6 from the Lenz law when the number of gates is G. That is, for example, when G = 3000 gates, the number of pads N = 2
There are 32. Therefore, at least 232 pads 10 are formed in each macro cell 7.

By the way, in the present embodiment, as will be described later, in the macrocell inspection step 2, the electrical characteristics of each macrocell 7 are inspected by a prober or the like. However, 1 mm
232 pads 10 in the microscopic Muccle cell 7 called a corner
It is impossible to bring the probe needle into contact with. E
The same applies when a B (Electron Beam) tester is used.

Therefore, in this embodiment, the problem is solved by applying the scan test method. For general scan test methods, for example, REALIZE INC., Published February 29, 1984, "Custom LSI Application Design Handbook" P150
~ P154 and JP-A-57-69349, the description thereof is omitted here.

In this embodiment, a probe needle is brought into contact with a small number of test pads 11 formed on the main surface of the macro cell 7 to inspect the electrical characteristics of the in-cell circuit. ..

Each test pad 11 is arranged, for example, on the in-cell circuit region 8 of each macro cell 7. The number of test pads 11 is, for example, about 5 to 11. With such a number of pads, even with a 1 mm square macro cell 7, a test pad 11 having a size sufficient for contacting a probe needle can be formed. The size of each test pad 11 is, for example, about 50 μm × 50 μm.

The test pad 11 is the macro cell 7
Arranged regularly on top. That is, in this embodiment, since the macro cells 7 and the test pads 11 are regularly arranged, the probe needles can be regularly brought into contact with the test pads 11 of each macro cell 7 when inspecting the macro cells 7. It has become. Therefore,
The inspection of all macro cells 7 can be performed quickly and efficiently.

The test pad 11 is electrically connected to an in-cell circuit via a shift register circuit section, which will be described later, arranged on the outer periphery of the input / output circuit section region 9 shown in FIG. 4, for example. The shift register circuit portion is shown in FIG.

The shift register circuit section 12 is composed of a plurality of shift registers 13 connected in series by a wiring D.

The wirings CK0 and CK1 are wirings for transmitting a clock signal as shown in FIG. 6 to each shift register 13. The wirings TM and OS are control lines that control the operation of the shift register circuit unit 12. A signal for converting the shift register circuit unit 12 to the test mode is transmitted to the wiring TM. A signal for setting the detection data from the circuit in the cell to the shift register 13 is transmitted to the wiring OS. The signal levels of the control lines during the operation of the shift register circuit section 12 are shown in FIG.

The shift register 13 includes an input shift register and an output shift register, which will be described later. FIG. 8 shows the symbols of the input shift register 13a. Wiring S
I is a shift-in wiring, and wiring SO is a shift-out wiring. These wirings SI and SO correspond to the wiring D shown in FIG. The wiring GO is connected to the in-cell circuit.

FIG. 9 shows the internal circuit of the input shift register 13a. The wirings CK1 and CK0 are AND1 respectively
It is connected to the inputs of 4a and 14b. Also, the wiring OS
Is also connected to the other inputs of AND's 14a, 14b.

The outputs of the ANDs 14a and 14b are connected to the inputs of the ANDs 15a and 15b, respectively. Wiring S
I is a flip-flop (hereinafter, F
(Abbreviated as / F) 16a.

The output of the F / F 16a is connected to the F / F 16b via the AND 15b.

The output of the F / F 16b is connected to the input of the AND 17 and the wiring SO. Wiring TM is AND1
7 and AND18 inputs. AND1
The outputs of 7 and 18 are connected to the wiring GO through the OR 19.

That is, it is as follows. Wiring O
When the "L" signal is input to S, AND 14a, 14b
Operates and the clock signal is transmitted to the ANDs 15a and 15b.

The inspection data input from the wiring SI is synchronized with the clock signal of the F / Fs 16a, 16a.
Shifted in to b. At this time, when the “H” signal is input to the wiring TM, the AND 17 operates and the inspection data is input to the in-cell circuit.

On the other hand, when the "H" signal is input to the wiring OS, the ANDs 14a and 14b are inoperative, and the inspection data is not shifted.

Further, FIG. 10 shows an output shift register 13
The symbol b is shown. The wiring GI is connected to the in-cell circuit. FIG. 11 shows the internal circuit of the output shift register 13b.

The wiring SI is connected to the input of the AND20. The wiring OS is connected to the inputs of AND20 and AND21. The outputs of AND20 and 21 are connected to the input of AND23a via OR22. AND2
The wiring CK1 is connected to the other input of 3a.

The output of the AND 23a is connected to the input of the AND 23b via the F / F 16a. AND23b
The wiring CK0 is connected to the other input of. AND2
The output of 3b is connected to the wiring SO through the F / F 16b. The wiring GI connected to the in-cell circuit is connected to the input of the AND 21 and the pad 10 via the buffer 24.

That is, it is as follows. Wiring O
When the "L" signal is input to S, the AND 20 operates, and the detection data input from the wiring SI is shifted into the F / Fs 16a and 16b in synchronization with the clock signal.

On the other hand, when the "H" signal is input to the wiring OS, the AND20 becomes inactive, and instead, the AND21 operates and the detected data from the in-cell circuit transmitted to the wiring GI is synchronized with the clock signal. The F / Fs 16a and 16b are shifted in.

At this stage, when the "L" signal is input to the wiring OS again, the detection data is output to the shift register 1 for output.
3b outputs to the wiring SO. Note that the shift register circuit section 12 does not operate when the signal levels of the wirings TM and OS are both at "L" level.

As described above, in this embodiment, the inspection data serially input through the test pad 11 and the wiring D can be converted into a parallel signal via the shift register circuit section 12 and transmitted to the in-cell circuit. Is becoming

Further, the detection data outputted in parallel from the in-cell circuit can be converted into a serial signal via the shift register circuit section 12, and the signal can be taken out from the test pad 11. Therefore, the circuit in the cell can be inspected through a small number of test pads 11, such as 5 to 11.

Next, FIG. 12 shows a sectional view of an essential part of the wafer immediately after the completion of the primary wiring step 1. The wafer 5 has, for example, an SOI structure. The semiconductor layer 5a is, for example, S
It is made of i single crystal and has a buried insulating layer 5b as an upper layer.
Are formed. The embedded insulating layer 5b is made of, for example, Si.
It is made of O ₂ , and its thickness is, for example, about 0.5 μm.

A semiconductor layer 5c is formed on the buried insulating layer 5b.
Are formed. The semiconductor layer 5c is made of, for example, Si single crystal and has a thickness of, for example, about 2 to 3 μm.
A semiconductor integrated circuit element (not shown) is formed on the semiconductor layer 5c.

Further, each macro cell 7 is formed on the semiconductor layer 5c.
Insulator 2 for separating the elements between macro cells so as to surround
5 is formed. The insulator 25 is made of SiO ₂ , for example. The width of the insulator 25 is, for example, about 0.5 μm, and the depth of the insulator 25 reaches a position slightly deeper than the buried insulating layer 5b.

A multi-layer wiring layer 5d is formed on the semiconductor layer 5c. The thickness of the multilayer wiring layer 5d is, for example, 3 to 5
It is about μm. The in-cell wiring 26 is provided in the multilayer wiring layer 5d.
Are formed. The width of the in-cell wiring 26 is, for example, 2 μm.
m, the thickness is, for example, about 0.5 μm, and the wiring pitch is
For example, it is about 2.5 μm.

The thickness of the wafer 5 including the multilayer wiring layer 5d is, for example, about 500 μm. The broken line in FIG. 12 indicates the boundary of the macro cell 7.

In the macro cell inspection step 2, FIG.
As shown in FIG. 5, the probe needle 27 is brought into contact with the test pad 11 of each macro cell 7 to judge the quality of the macro cell 7. At this time, for example, the position data of the defective macro cell 7a is transmitted to the pattern data storage area of the electron beam direct writing apparatus (not shown).

The inspection items are, for example, a DC function test, a DC parameter test of input / output terminals, and an AC.
For example, a switching test.

Next, in the defective macro cell replacement step 3, the defective macro cell 7a is replaced with a good macro cell described later according to steps 3a to 3f shown in FIG.

In the wafer main surface side divided groove forming step 3a, the following processing is performed. First, as shown in FIG. 14, a resist 28 for electron beam direct writing, for example, is applied on the multilayer wiring layer 5d.

Subsequently, of the resist 28, only the resist portion located on the outer periphery of the defective macro cell 7a is removed by the electron beam direct writing method. The width of the resist removal region is, for example, about 2 to 3 μm. The pattern data at this time is automatically created based on the position data of the defective macro cell 7a described above.

After that, as shown in FIG.
Using the mask 8 as a mask, the main surface side U groove (main surface side dividing groove) 29 is formed. The U-groove 29 on the main surface side is removed by etching the multilayer wiring layer 5d and the insulator 25 for separating the elements between the macro cells under the resist removal region by, for example, the RIE method in which conditions are set so that only SiO ₂ is selectively etched. To form. A plan view of the wafer 5 after this processing is shown in FIG. As shown in FIG. 16, the main surface side U groove 29 is formed only on the outer periphery of the defective macro cell 7a.

Next, a wafer rear surface side division groove forming step 3b
In FIG. 17, as shown in FIG. 17, the back surface side U groove reaching the main surface side U groove 29 from the back surface side of the wafer 5 (back surface side dividing groove)
Form 30.

To form the U-shaped groove 30 on the back surface side, a resist (not shown) is used as a mask, for example, by the RIE method or the like in which conditions are set so that only Si is selectively etched.

At this time, since the buried insulating layer 5b forming the wafer 5 is made of SiO ₂ or the like, it acts as an etching stopper layer when forming the U groove 30 on the back surface side. Therefore, at this time, the cross-sectional shape of the U-groove 29 on the main surface side is not deformed, and the processing size of the U-groove 29 on the main surface side, the processing size of the defective macrocell removal region, and the like do not change. Therefore, the superiority of alignment and incorporation of a good replacement macro cell is not impaired.

Further, when forming the U-shaped groove 30 on the back surface side, the presence of the buried insulating layer 5b does not damage the macro cell 7 or the semiconductor integrated circuit element in the macro cell 7 to be taken out. Therefore, the method of taking out the macro cell 7 can be used as it is as a method of manufacturing a good macro cell.

In this way, the U groove 30 is formed from the back surface side of the wafer 5.
The reason for forming is that the back surface side of the wafer 9 may have a lower groove processing accuracy (about ± 5 μm) than the wafer main surface side.
This is because there is room for selection in the groove processing method described later, and the groove processing time can be shortened.

That is, the method of forming the U-shaped groove 30 on the back surface side is not limited to the dry etching method such as RIE, but various modifications can be made. For example, the following method may be used.

First, as shown in FIG. 18, the semiconductor layer 5a is formed.
Midway position, for example, a depth of 450 μm from the back surface of the wafer 5.
The U groove 30a is formed by a dicing blade having a diameter of about 1 to 2 mm up to a certain position.

After that, the remaining semiconductor layer 5a is removed by etching by the RIE method or the like in which conditions are set so that only Si is selectively etched, and the back surface side U groove 3 shown in FIG.
Form 0. In this case, the formation time of the back surface side U groove 30 can be shortened.

Alternatively, after the U groove 30a as shown in FIG. 18 is formed by the wet etching method, the remaining portion may be removed by the dry etching method. Further, as another method of forming the back surface side U groove 30, for example, an ultrasonic processing method or a laser processing method may be used.

Next, in the defective macro cell removing step 3c, the divided defective macro cells 7a are removed from the wafer 5. Note that FIG. 19 shows a cross-sectional view of an essential part of the wafer 5 immediately after the completion of this step 3c.

In the subsequent step 3d for incorporating a good macrocell, as shown in FIG. 20, the wafer 5 is placed upside down on the placing table 31, and then the good macrocell 7 for replacement is placed.
Is arranged in the defective macrocell removal region with its main surface facing downward. In this case, the good macro cell 7 is taken out from a wafer having another SOI structure, for example, in the same manner as the method of taking out the bad macro cell 7a described above.

Then, in this embodiment, in the good macrocell fixing step 3e, the good macrocell 7 is fixed by using, for example, an optical CVD method. At this time, for example, the following is performed.

First, the mounting table 31 on which the wafer 5 is mounted is mounted on the susceptor in the processing chamber of the photo CVD apparatus (not shown).

Subsequently, after introducing, for example, a silane-based reaction gas into the processing chamber of the photo-CVD apparatus, as shown in FIG. 21, a light beam 32 such as an excimer laser is introduced into the U-shaped groove 30 on the back surface side. Is irradiated to form a buried film 33a made of, for example, polysilicon.

That is, in this embodiment, since the back surface side U groove 30 is filled with the inorganic material having a higher melting point and a lower thermal expansion coefficient than the organic material, stress is applied to the back surface side U groove 30 during the subsequent heat treatment. The phenomenon that occurs can be suppressed.

However, the burying film 33a is not limited to polysilicon and can be variously changed, and may be SiO ₂ formed by the photo CVD method, for example.

[0083] Then, the wafer main surface dividing groove filling step 3f, as shown in FIG. 22, for example SiO ₂
An insulating film 34 of, for example, is deposited on the main surface of the wafer 5 by the CVD method or the like to fill the main surface side U groove 29.

In the subsequent wafer main surface side flattening step 3g, for example, the following processing is performed. First, as shown in FIG. 22, a planarizing insulating film 35 is deposited on the insulating film 34. At this time, the flattening insulating film 35 is deposited to such an extent that its upper surface becomes substantially flat. After that, the flattening insulating film 35 is etched back by, for example, the RIE method, and as shown in FIG.
The upper surface of 4 is flattened.

Then, in the secondary wiring step 4, the macro cells 7 are connected to each other by inter-cell wiring (not shown) to form a predetermined logic LSI in the chip area 6. The width of the inter-cell wiring is, for example, about 4 μm, and the thickness is, for example, 1
The wiring pitch is, for example, about 5 μm.

After that, a wafer test is performed to inspect the electrical characteristics of the logic LSI for each chip area 6 to determine whether each chip area 6 is good or bad, and then the wafer 5 is divided into the chip areas 6 by the wafer scribing process. Then, the chip manufacturing is completed.

As described above, according to this embodiment, in order to fix the good macro cell 7, the photo CVD is performed in the U-groove 30 on the back surface side.
By embedding an inorganic material such as polysilicon formed by a method or the like, it is possible to suppress a phenomenon in which stress is generated in the rear surface side division groove portion in a predetermined heat treatment step of manufacturing a semiconductor integrated circuit device.

In addition, since it is generally difficult for moisture to pass through the inorganic substance, it is possible to suppress the phenomenon that moisture penetrates into the main surface side of the semiconductor chip through the rear surface U groove 30 portion.

As a result, the reliability and yield of the semiconductor integrated circuit device can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the case where the inorganic material is embedded in the U-groove on the back surface side by the photo-CVD method has been described, but the present invention is not limited to this and various modifications can be made. By the CVD method using tetraethoxysilane (hereinafter referred to as TEOS)
O ₂ or the like may be embedded.

The CVD method in this case is, for example, O ₃ -TE in which TEOS and ozone (O ₃ ) are reacted under low pressure.
OS low pressure CVD method, O ₃ -TEOS atmospheric pressure CVD method of reacting TEOS and O ₃ under atmospheric pressure or T in plasma
There is a plasma TEOS method in which EOS is reacted.

FIG. 24 shows a cross-sectional view of essential parts of the wafer 5 after this processing step. In this case, in addition to the effect obtained in the above-mentioned embodiment, the buried film 33b is formed at a relatively low temperature (for example, 400
The effect that it can be formed is obtained at (-450 ° C.).

As another method of filling the U-shaped groove on the back surface side, there is a method of applying a sol-like or gel-like inorganic substance to the back surface of the wafer. In this case, for example, the following is done.

That is, after applying the coating agent containing silanol as a main component to the back surface of the wafer by spin coating or the like, the wafer is heat-treated at a predetermined temperature to evaporate the solvent in the coating agent and further polymerize. Let the reaction proceed,
An SOG (Spin On Glass) film is formed on the back surface side of the wafer.

FIG. 25 shows a cross-sectional view of the main part of the wafer 5 after this processing step. In this case, the process of forming the embedded film 33c is easy, and the throughput of forming the embedded film 33c is large, so that the throughput can be improved.

Further, although the case where the U-shaped groove on the main surface side is formed and then the U-shaped groove on the back surface is formed has been described in the above embodiment, the present invention is not limited to this and, for example, the order of those steps is described. You may reverse.

[0098]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the means for embedding an inorganic substance in the rear surface side dividing groove, it is possible to suppress the phenomenon that stress is generated in the rear surface side dividing groove portion during a predetermined heat treatment step of manufacturing a semiconductor integrated circuit device. Become. In addition, the inorganic substance is
Since it is generally difficult for moisture to pass through, it is possible to suppress the phenomenon that moisture penetrates into the main surface side of the semiconductor chip through the rear surface side division groove portion. As a result, the reliability and yield of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a process chart for explaining a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is an overall plan view of the wafer immediately after the completion of the primary wiring process.

FIG. 3 is an enlarged plan view of a chip area formed on the wafer of FIG.

FIG. 4 is an enlarged plan view of a macro cell formed in the chip region of FIG.

5 is a circuit block diagram showing a shift register circuit unit formed in the macro cell of FIG.

FIG. 6 is a timing chart of clock signals for synchronizing the shift register circuit unit.

FIG. 7 is a diagram showing a signal level of a control line during operation of a shift register circuit unit.

FIG. 8 is a symbol diagram of an input shift register.

9 is an internal circuit diagram of the input shift register shown in FIG.

FIG. 10 is a symbol diagram of an output shift register.

11 is an internal circuit diagram of the output shift register shown in FIG.

FIG. 12 is a fragmentary cross-sectional view of the wafer immediately after the completion of the primary wiring step.

FIG. 13 is a fragmentary cross-sectional view of a wafer during a macrocell inspection process.

FIG. 14 is a cross-sectional view of essential parts of a wafer for explaining a wafer main surface side divided groove forming step.

FIG. 15 is a cross-sectional view of essential parts of a wafer for explaining a wafer main surface side divided groove forming step.

16 is a plan view of the wafer shown in FIG.

FIG. 17 is a fragmentary cross-sectional view of the wafer for explaining the wafer rear surface side division groove forming step.

FIG. 18 is a cross-sectional view of essential parts of a wafer for explaining a modified example of the wafer rear surface side division groove forming method.

FIG. 19 is a fragmentary cross-sectional view of the wafer immediately after the defective macrocell removing step is completed.

FIG. 20 is a cross-sectional view of essential parts of a wafer, showing a state in which a good macro cell for replacement is arranged in a removal region of a bad macro cell.

FIG. 21 is a cross-sectional view of an essential part of a wafer for explaining a good macrocell fixing step.

FIG. 22 is a sectional view of the essential part of the wafer, for explaining the step of filling the groove on the main surface side of the wafer.

FIG. 23 is a cross-sectional view of essential parts of the wafer immediately after the flattening process on the main surface side of the wafer.

FIG. 24 is a fragmentary cross-sectional view of a wafer after a good macrocell fixing step which is a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 25 is a fragmentary cross-sectional view of a wafer after a good macrocell fixing step which is a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Description of Reference Signs] 1 primary wiring step 2 macro cell inspection step 3 defective macro cell replacement step 3a wafer main surface side dividing groove forming step 3b wafer back surface side dividing groove forming step 3c defective macro cell removing step 3d good macro cell incorporating step 3e good macro cell Fixing step 3f Wafer main surface side dividing groove filling step 3g Wafer main surface side flattening step 4 Secondary wiring step 5 Semiconductor wafer 5a Semiconductor layer 5b Embedded insulating layer 5c Semiconductor layer 5d Multilayer wiring layer 6 Chip area 7 Macro cell 7a Defective macro cell 8 Cell Circuit Area 9 Input / Output Circuit Area 10 Pad 11 Test Pad 12 Shift Register Circuit Section 13 Shift Register 13a Input Shift Register 13b Output Shift Register 14a AND 14b AND 15a AND 15b AND 16a F / F 16b F / F 17 AND 18 AND 19 OR 20 20 AND 21 AND 22 OR 23a AND 23b AND 24 Buffer 25 Insulator 26 In-cell wiring 27 Probe needle 28 Resist 29 Main surface side U groove (main surface side dividing groove) 30 Back surface side U groove (back surface) Side division groove) 30a U groove 31 Mounting table 32 Light beam 33a Embedded film 33b Embedded film 33c Embedded film 34 Insulating film 35 Flattening insulating film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mikio Hongo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Institute of Industrial Science, Hitachi, Ltd. (72) Inventor Tomoji Oishi 4026 Kuji-cho, Hitachi-shi, Ibaraki Hitachi Research Laboratory, Hiritsu Works

Claims (4)

[Claims] 1. A primary wiring step of arranging a plurality of macro cells having the same circuit function in a chip region of a semiconductor wafer, a step of inspecting the quality of the macro cells, and a defective macro cell determined by a quality inspection of the macro cells. By forming a main surface side division groove and a back surface side division groove from both the main surface side and the back surface side of the semiconductor wafer around the periphery of the semiconductor wafer, a step of taking out the defective macro cell and a good macro cell at the position of the defective macro cell are formed. After the insertion, the step of fixing the good macro cell by burying an inorganic substance in the back side division groove by the photo CVD method and the step of connecting the macro cells in the chip area after the step of replacing the defective macro cell are connected to each other to provide a predetermined semiconductor integrated circuit device. And a secondary wiring process for forming the semiconductor integrated circuit device. 2. In the step of fixing the good macrocell, instead of burying the inorganic substance by the photo CVD method, the inorganic substance is buried by the CVD method using tetraethoxysilane in the rear surface side dividing groove. The method for manufacturing a semiconductor integrated circuit device according to claim 1. 3. In the step of fixing the good macrocell, the sol-like or gel-like inorganic substance is embedded in the rear surface side dividing groove instead of burying the inorganic substance by the photo-CVD method. A method of manufacturing a semiconductor integrated circuit device according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor wafer is an SOI structure semiconductor wafer in which a semiconductor layer for forming a semiconductor integrated circuit element is formed on an insulating film. Device manufacturing method.