JPH04174538A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve yield by arranging test pads in each macrocell, judging whether the macrocell is perfect by comparison, eliminating imperfect macrocells on the basis of the data concerning whether cells are perfect, burying the perfect macrocells, and forming a circuit. CONSTITUTION:Macrocells 11 are regularly arranged in a chip region, and test pads 15 are regularly arranged in each cell 11. A circuit region 12 in a cell is arranged in the central part of the cell 11; pads 14 are arranged on the outer periphery; a shift register circuit part is arranged on the outer periphery of I/O circuit regions 13. At the time of inspection, probes 32 are made to abut against the pads 15, and inspection data are inputted to the circuit in a cell from the pads 15 via the shift register circuit part. Inspection data outputted to the pads 15 from the circuit in a cell are compared with expected values, and whether the cell is perfect is judged. Thus data concerning whether each cell is perfect are obtained. Macrocells which are decided to be imperfect are eliminated by an FIB method or the like, and replaced by perfect macrocells, which are buried. Thereby defects are surely relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor integrated circuit devices, and particularly to a technology for relieving defects in semiconductor integrated circuit devices.

[Conventional technology]

Conventionally, defect repair techniques for semiconductor wafer (hereinafter referred to as wafer) scale LSI include (1) Nikkei McGraw-Hill, published April 1, 1986, "Nikkei Microdevices April 1986 issue," P45. P46, (
2), I.E., Journal of Solid State Circuits.

Varnish C. Vol. 21, No. 5, October 1986 (IEEE
JOURNAL OF 5OLID-3TATE C
IRCLllTS, VOL, 5C-21°NO, 5,0
CTOBER1986) r Silicon Hybrid Wafer Scale Package Technology (S11i
con Hybrid Wafer-Scale Pa
ckage Technology) JP845~P8
51, (31, JP-A-62-147746).

In the documents (1) and (2) above, wafer scale integrated circuits (hereinafter referred to as WS I (Wafer 5cale)
Defect repair technology (referred to as "Integration") is explained. The outline is as follows. First, a defective chip area among the chip areas on the wafer is removed, and a hole having a planar rectangular shape passing through the main surface and back surface of the wafer is bored in the removed area. Next, the wafer is placed on a predetermined table with its main surface facing downward. Then, a non-defective semiconductor chip (hereinafter referred to as a chip) is placed into a hole drilled in the wafer with its main surface facing downward. The chip size of a good chip placed in the hole is, for example, about 4.98 mm square. After that, the gap between the good chip and the wafer is filled with epoxy resin or the like. Finally, the wafer is turned over and the pads of the good chips are interconnected to the pads of the good chip area on the wafer to form a WSI.

Further, the document (3) above also describes the WSI defect relief technology. The outline is (1) above,
(Similar to 21, remove the defective chip area on the wafer,
A defect relief technique is described in which a good chip is buried in the removed area and then the chips are interconnected to form a WSI.

[Problem to be solved by the invention]

Incidentally, in recent years, semiconductor integrated circuit devices are becoming larger in capacity and more sophisticated. As a result, devices are becoming more highly integrated and chips are becoming larger.

However, as chips become larger, the number of chip areas that can be formed on a wafer also decreases. Furthermore, as chips become larger and devices become more highly integrated, the incidence of defects caused by foreign objects and the like also increases. These greatly reduce the number of good chips obtained from one wafer. In other words, as the capacity and functionality of semiconductor integrated circuit devices increases, it is expected that it will become extremely difficult to maintain a chip yield that is competitive in terms of cost. For example, in highly integrated semiconductor integrated circuit devices, the defect density is 1/c.
The probability Y of manufacturing a defect-free chip of approximately 2On+m square under conditions such as ar is as follows. That is, Y#
e-'=2%. However, this cannot be used for production. Furthermore, it is extremely difficult to prepare as many chips as possible in the very low yield stage of early development, such as the stage of mask depacking of ffLsI, that is, the stage of logic verification, in order to confirm their reliability. Therefore, if things continue as they are, the performance of integrated circuits will have to be lowered in order to ensure chip yield. From this point of view, as future trends in semiconductor integrated circuit devices, how to achieve highly reliable defect relief will become an important issue.

In addition, in recent years, in semiconductor integrated circuit devices, ASIC
The development and manufacturing of custom products such as For custom products such as ASICs, chips are manufactured in accordance with the user's specifications and in the number of chips requested by the user. For this reason, although the number of types increases, the production quantity for each type does not usually increase. In other words, it is impossible to expect product cost reductions due to mass production effects. The cost of the product will be greatly influenced by the chip yield.

Therefore, in order to ensure a chip yield that is competitive in terms of cost, a highly reliable defect relief technique is required, similar to the above. On the other hand, in the case of custom products, if the product type changes, the wiring connection state, etc. will also change, so the failure mode etc. will also vary depending on the product type. For this reason, for example, the cause of the defect must be analyzed every time the product type changes, making the task of correcting the defect extremely difficult. Furthermore, it is difficult to analyze the cause of defects after the chip is manufactured, that is, after the wiring connection process is completed. Furthermore, it is nearly impossible to correct defects that occur during the initial stage of chip manufacturing after the chip is manufactured. Therefore, if things continue as they are, the performance of integrated circuits will have to be lowered in order to ensure chip yield. From this point of view, as future trends in semiconductor integrated circuit devices, how to realize defect relief with high applicability that can be applied to various types of chip modifications will become an important issue.

However, in the conventional techniques (1) to (3) above, defect relief in the chip area is not taken into consideration, so there is a problem that the conventional techniques cannot be applied as chip defect relief techniques.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can realize highly reliable defect relief.

Another object of the present invention is to provide a technique that can realize defect relief with high applicability.

Another object of the present invention is to avoid degrading the performance of the integrated circuit.
The purpose of the present invention is to provide a technology that can improve chip yield.

Another object of the present invention is to provide a technology that can accommodate increased capacity and higher functionality of semiconductor integrated circuit devices.

Another object of the present invention is to provide a technique that can support customization of semiconductor integrated circuit devices.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the invention as claimed in claim 1 provides that after a predetermined semiconductor integrated circuit element is formed in a chip region on a wafer, a plurality of macro cells having the same circuit function are regularly arranged in the chip region in a first wiring step. At the same time, test pads connected to the main circuit section in the macro cell through a shift register circuit section formed inside the macro cell are regularly arranged in each macro cell, and are unified to control each test pad in the chip area. When inspecting the electrical characteristics of macrocells,
The test data input in series through the test pad is converted into a parallel signal via the shift register circuit section, the signal is input to the main circuit section, and the detection data output in parallel from the main circuit section is shifted using the test data. It is converted into a serial signal via the register circuit section and output to the test pad.
The quality of the macrocell is determined by comparing the output detection data with the expected value, the quality information of the macrocell is created based on the determination result, and the defective macrocell is removed based on the quality information. This is a method for manufacturing a semiconductor integrated circuit device, in which good macrocells are buried in the removed region, and macrocells in the chip region are connected through a secondary wiring process to form a predetermined semiconductor integrated circuit in the chip region. .

The invention according to claim 2 provides a method for manufacturing a semiconductor integrated circuit device, in which the macro cells are arranged in a grid in a chip area, and when testing the macro cells, a plurality of macro cells located on the same straight line are simultaneously tested. It is something to do.

A third aspect of the invention provides a method for manufacturing a semiconductor integrated circuit device, in which the good macrocells are obtained from a wafer to be inspected.

The invention according to claim 4 provides a method for manufacturing a semiconductor integrated circuit device in which, when burying a good macrocell in the region from which the defective macrocell has been removed, the surface level of the good macrocell and the surface level of surrounding macrocells are set to be the same height. This is a method.

In the fifth aspect of the invention, when burying a good macrocell in the region from which the defective macrocell has been removed, a metal or a compound thereof is embedded between the good macrocell and surrounding macrocells, and after the good macrocell is fixed, the metal or The present invention provides a method for manufacturing a semiconductor integrated circuit device in which the buried upper part of the compound is flattened to match the surface of the macro cell.

According to a sixth aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device, in which the cross-sectional area of the wiring connecting between the macro cells is made larger than the cross-sectional area of the wiring within the macro cells.

The invention according to claim 7 provides an S
The electrical characteristic test is performed on the macrocell formed in the chip region of the OI structure semiconductor wafer, and based on the results, a main surface extending from the main surface side of the semiconductor wafer to the insulating layer is placed on the outer periphery of the defective macrocell. After the defective macrocell is taken out by a step of forming a side dividing groove using a photolithography technique and a step of forming a back side dividing groove reaching the main surface side dividing groove from the back side of the semiconductor wafer, the defective macrocell is removed. A method of manufacturing a semiconductor integrated circuit device includes placing and fixing a good macro cell taken out from the semiconductor wafer or another SOI-structured semiconductor wafer in the region from which the bad macro cell is removed in the same manner as in the taking out method.

In the eighth aspect of the invention, after forming a predetermined semiconductor integrated circuit element in a chip area on a wafer, a plurality of macro cells having the same circuit function are regularly formed in the chip area by a first wiring process. At the same time, test pads connected to the main circuit section in the macro cell through a shift register circuit section formed inside the macro cell are regularly formed in each macro cell, and are unified so as to connect each macro cell in the chip area. When testing the electrical characteristics of the The detection data outputted in parallel from the unit is converted into a serial signal via the shift register circuit unit and outputted to the test pad, and macro cell information is created based on the outputted detection data.
After removing predetermined macrocells based on the macrocell information, macrocells with different types of circuit functions are buried in the predetermined removal area, and the macrocells within the chip area are connected through a secondary wiring process. The present invention provides a method for manufacturing a semiconductor integrated circuit device in which a predetermined semiconductor integrated circuit is formed in the semiconductor integrated circuit device.

Another invention of the present application is to form main surface side dividing grooves around the macro cells on the main surface side of the wafer by high-precision processing, and to form grooves on the back surface around the macro cells on the back surface side of the wafer by low-precision processing. The present invention provides a method of manufacturing a semiconductor integrated circuit device in which side dividing grooves are formed and macro cells are removed.

Another invention of the present application is that before forming intra-macrocell wiring for forming a plurality of macrocells in a chip area of a wafer having an SOI structure, a main part of the wafer is provided on the outer periphery of each macrocell to be formed in the chip area. By providing in advance a main surface side dividing groove forming member that reaches the insulating layer inside the wafer from the surface side, and removing the main surface side dividing groove forming member during the macro cell removal process, the inside of the wafer can be formed from the main surface side of the wafer. The present invention is a method of manufacturing a semiconductor integrated circuit device in which main surface side dividing grooves reaching an insulating layer are formed.

Another invention of the present application is a semiconductor integrated circuit device in which dividing grooves are formed so that the main surface side dividing grooves and the back side dividing grooves are formed around the macro cell so that the positional accuracy of good macro cells and defective macro cells is formed. The manufacturing method is as follows.

[Effect]

According to the invention described in claim 1, only the defective portions within the chip area are removed at an early stage during the wafer process, that is, at a stage where the defect rate is high due to fineness and high integration. can be easily corrected. Therefore, for example, you can do as follows. That is, first,
Macrocells are formed within the chip area using cutting-edge process technology up to the first wiring step. Next, if a defective macrocell occurs, it is removed. Then, good macrocells manufactured using the most advanced process technology are placed in the area where the defective macrocells have been removed. By doing so, it is possible to reliably repair defects without lowering the performance of the semiconductor integrated circuit, and it is possible to improve the chip yield. Furthermore, defects are corrected at a stage before a predetermined semiconductor integrated circuit is formed in the chip area, that is, before the chip area has a function as a predetermined semiconductor integrated circuit, and immediately after a defect is discovered. Therefore, it becomes possible to realize defect relief with high applicability and certainty.

According to the second aspect of the invention, by simultaneously testing a plurality of macrocells when testing a macrocell, it is possible to test all macrocells in a chip area in a short time.

According to the above-mentioned invention as claimed in claim 3, by obtaining a replacement good macrocell from the same wafer to be buried in the removal area of the defective macrocell, the elements etc. between the good macrocell and other macrocells in the chip area can be changed. It becomes possible to approximate electrical characteristics.

According to the invention described in claim 4, the replacement good macrocell buried in the removal area of the defective macrocell and its If
By setting the surface height of the lWi to the same height as the macrocell, when the good macrocell is buried in the removal area of the defective macrocell, the surface height of those macrocells will be reduced between the good macrocell and the surrounding macrocells. There is no difference in level caused by the difference in Therefore, it is possible to prevent disconnection of inter-cell wiring connecting macro cells due to the step difference.

According to the invention described in claim 5, the upper part of the material buried in the groove between the replacement good macrocell buried in the removal area of the defective macrocell and the surrounding macrocells is flattened. There is no difference in level caused by the material buried in the groove between the good macrocell buried in the macrocell removal area and the surrounding macrocells. Therefore, it is possible to prevent disconnection of inter-cell wiring caused by the step.

According to the invention described in claim 6, the cross-sectional area of the inter-cell wiring connecting macro cells is made larger than the cross-sectional area of the intra-cell wiring within the macro cell, so that the inter-cell wiring becomes relatively long. This can suppress the increase in wiring resistance. That is, it becomes possible to suppress wiring delays and the like. Moreover, since the sensitivity to foreign matter in the inter-cell wiring is alleviated, wiring defects in the secondary wiring process can be reduced.

According to the invention described in claim 7, since the main surface side dividing grooves are formed with the precision of photolithography technology, the removal area of defective macrocells or the external dimensional accuracy of good macrocells can be made extremely high. It is also possible to improve the reproducibility of dimensions and the like. Further, when forming the back side dividing grooves by etching, for example, by using the insulating layer of the SOI structure wafer as a stopper layer, the dimensional accuracy of the main side dividing grooves will not be reduced. That is, when forming the back side dividing grooves, the dimensions of the defective macrocell removal region and the dimensional accuracy of the good macrocells are not reduced. Furthermore, since the machining accuracy of the back side dividing groove is lower than that of the main side, it is possible to perform rougher machining than the main side dividing groove.
There is also room for choice in processing methods.

According to the invention as set forth in claim 8 above, by arranging macro cells having different types of circuit functions within the chip area, the logic of the semiconductor integrated circuit can be changed or the functions of the semiconductor integrated circuit can be expanded. becomes possible.

[Example 1] Fig. 1 is a process diagram showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and Fig. 2 is an overall plan view of a wafer showing the chip area immediately after the completion of the first wiring process. , FIG. 3 is an enlarged plan view of the chip area shown in FIG. 2, FIG. 4 is an enlarged plan view of the macrocell formed in the chip area shown in FIG. 3, and FIGS. 5 and 6 are test samples. An enlarged plan view of the macrocell to explain why the pads are arranged in a staggered manner.
7 is a circuit diagram showing the shift register circuit formed in the macro cell shown in FIG. 4, FIG. 8 is a timing chart of a clock signal for synchronizing the shift register circuit, and FIG. 9 is a shift register circuit. A diagram showing the signal level of the control line during operation of the register circuit section, FIG. 10 is a symbol diagram of the input shift register, FIG. 11 is an internal circuit diagram of the input shift register shown in FIG. 10, and FIG. 12 13 is a symbolic diagram of the output shift register, FIG. 13 is an internal circuit diagram of the output shift register shown in FIG. 12, FIG. 14 is a cross-sectional view of the main part of the wafer immediately after the completion of the first wiring process, and FIG. 15 is an enlarged plan view of the chip area in the macro cell inspection process, the first
6 is an enlarged plan view of a chip area showing a modification of the macro cell inspection method, FIG. 17 is an enlarged plan view of a macro cell in a macro cell inspection process, FIG. 18 is a sectional view of a main part of a wafer in a macro cell inspection process, and FIG. 19 20 is an enlarged plan view of the chip area showing a defective macrocell, FIG. 20 is a cross-sectional view of the main part of the wafer in the process of removing the defective macrocell, and FIG. 21 is a cross-sectional view of the main part of the wafer when placing a good macrocell in the defective macrocell removal area. , FIG. 22 is a sectional view of a main part of a wafer showing a state in which good macrocells are buried in a defective macrocell removal area, and FIG. 23 is a sectional view of a main part of a wafer immediately after the completion of the secondary wiring process.

In the first embodiment, a method for manufacturing a logic LSI chip, for example, will be described. However, the target semiconductor integrated circuit is not limited to logic LSI and can be modified in various ways.

FIG. 1 shows the manufacturing process of a semiconductor integrated circuit device according to the first embodiment. The manufacturing process of the semiconductor integrated circuit device of Example 1 is as follows:
For example, it has the following process.

That is, a wafer manufacturing process 1, a diffusion process 2, a primary wiring process 3, a macro cell inspection process 4, a defective macro cell replacement process 5, a secondary wiring process 6, a wafer test process 7, and a wafer scribing process 8.

Hereinafter, in this embodiment 1, first, the first wiring process 3
The wafer and the chip area formed on the wafer will be explained with reference to FIGS. 1 to 11.

FIG. 2 shows the wafer after the first wiring step 3 has been completed. The wafer 9 is made of, for example, single crystal silicon (Si). The diameter of the wafer 9 is, for example, about 6 inches. For example, 3211 chip regions 10 are arranged on the main surface of the wafer 9. The size of each chip area 10 is, for example, about 20 mm x 20 mm.

An enlarged plan view of the chip region 10 is shown in FIG. Each chip area 10 includes, for example, 400 macro cells 11.
are arranged in a grid pattern. The size of each macro cell 11 is, for example, about 1 mm x 1 mm. Each macrocell 1
1, an intra-cell circuit (main circuit section) having the same function is formed. However, at this stage, the macro cells 11 are not interconnected by wiring. That is, the intra-cell circuits formed in each macro cell 11 are in a circuit-wise independent state. In the first embodiment, an insulator (not shown) is formed on the outer periphery of each macro cell 11 to electrically isolate the semiconductor integrated circuit elements of each macro cell 11.

An enlarged plan view of the macro cell 11 is shown in FIG. In the center of the macro cell 11, for example, an intra-cell circuit region 12 is arranged. In the intra-cell circuit region 12, an intra-cell circuit such as a gate array of approximately 3 gates is formed. However, the circuit within the cell is not limited to the gate array (various changes are possible. For example, the circuit within the cell may be SRAM (St
atic RAM) or a circuit having an analog function. A plurality of input/output circuit areas 13 are arranged around the outer periphery of the intra-cell circuit area 12 . In each input/output circuit area 13,
Predetermined input/output circuits such as human output buffers are formed. In addition, each input/output circuit area 13 has a pad 14.
is located. The pad 14 is a pad for interconnecting the macro cells 11 in a secondary wiring process 6 to be described later. The number N of pads 14' is, for example, N=1.9G'' from Lenz's law, where G is the number of gates. That is, if G=3000 gates, the number N of pads 14' is 232. Therefore, each At least 232 pads 14 are formed in the macrocell 11.

In the first embodiment, the electrical characteristics of each macro cell 11 are tested by blow μ or the like in macro cell test step 4, which will be described later. However, it is impossible to bring the probe needle into contact with the 232 pads 14 between the minute macrocells 11 of 1 ohm square. E B (
The same is true when using an Electron Beam (Electron Beam) tester. Therefore, in the first embodiment, this problem is solved by applying a scan test method. −
Regarding the boat fishing scan test method, for example, REALIZE INC., February 2, 1980.
Published on the 9th, [Custom LSI Application Design Handbook J]
Since it is described in P150 to PI34 and Japanese Unexamined Patent Publication No. 57-69349, it will be omitted here. In the first embodiment, a shift register circuit section, which will be described later, is interposed between the test pad 15 and the intra-cell circuit. As a result, in the first embodiment, a small number (for example, 5 to 111
It is possible to test the electrical characteristics of the circuit within the cell through the test pad 15 (approximately 1). Hereinafter, first, the test pad 15 will be explained, and then the shift register circuit section will be explained.

Each test pad 15 is arranged, for example, on the intra-cell circuit area 12 of each macro cell 11. test pad 15
The number is, for example, about 5 to 11 m. With this number of pads, it is possible to form a test pad 15 large enough to abut with a probe needle even on a 1 mm square macrocell 11. Each test pad 15
The size is, for example, about 508 m x 50 μm. Test pads 15 are regularly arranged on macrocell 11. That is, in the first embodiment, the macro cells 11 are regularly arranged within the chip region 10, and the test pads 15 are regularly arranged within each macro cell 11. As a result, when testing the macrocells 11, it is possible to regularly bring the probe needles into contact with the test pads 15 of each macrocell 11. Therefore, all macrocells II can be tested quickly and efficiently.

Further, in the first embodiment, the test pads 15 are arranged in a shifted manner, as shown in FIG. 4, for example. This is due to the following reason. When the probe needle comes into contact with the test pad 15 when testing the macro cell 11, the test pad! The upper part of 5 is depressed, and a step is created in that part. However, if an inter-cell interconnect for connecting macro cells 11 is formed directly above such a test pad 15, the inter-cell interconnect may be disconnected due to a step on the upper surface of the test pad. In order to prevent this, it is conceivable to form inter-cell wiring 16 between test pads 15, as shown in FIG. However, if the test pads 15 are simply arranged in a row, the space between the test pads 15 will become narrower.
The number of inter-cell wiring lines 16 that can be arranged between them is reduced. Therefore, in the first embodiment, as shown in FIG. 6, by shifting the position of the test pad 15,
A distance between adjacent test pads 15 is ensured.

As a result, the number of inter-cell interconnections 16 that can be formed between adjacent test pads 15 is increased.

Next, the shift register circuit section described above will be explained. The shift register circuit section is arranged on the outer periphery of the input/output circuit area 13 shown in FIG.

As shown in FIG. 7, the shift register circuit section 17 includes a plurality of shift registers 18 connected in series by wiring.

Wiring CKO and CKI are wiring for transmitting a lock signal to each shift register 18 as shown in FIG.

Further, the wirings TM and O3 shown in FIG. 7 are control lines for controlling the operation of the shift register circuit section 17. A signal for converting the shift register circuit section 17 into a test mode is transmitted to the wiring TM. A signal for setting detection data from the intra-cell circuit in the shift register 17 is transmitted to the wiring O8. FIG. 9 shows the signal levels of the control lines when the shift register circuit section 17 is in operation.

The shift register 18 shown in FIG. 7 includes an input shift register and an output shift register.

FIG. 10 shows the symbol of the input shift register 18a.

The wiring SL is a shift-in wiring, and the wiring SO is a shift-out wiring. These wirings ST and So correspond to the wiring shown in FIG. The wiring GO is connected to the intra-cell circuit. FIG. 11 shows the internal circuit of the input shift register 18a. Wiring CKI.

CKO is connected to the inputs of AND19a and 19b, respectively. Also, the wiring O8 is also AND 19a, 19b
connected to other inputs. The outputs of AND19a and 19b are AND20a, respectively.

20b. Wiring Sl is AND20
Flip-flop (hereinafter abbreviated as F/F) 2 via a
1a. The output of F/F 21a is AND
It is connected to F/F 2 l b via 20b.

The output of F/F21b is the input of AND22 and the wiring S
Connected to O. Wiring TM is AND22 and AN
Connected to the input of D23. The outputs of AND22 and 23 are connected to the wiring GO via 0R24. That is, when an "L" signal is input to the wiring O8, AND 19
a.

19b is activated and AND20a and 20bl: a clock signal is transmitted. The inspection data input from the wiring Sl is shifted into the F/Fs 21a, 2]b in synchronization with the clock signal. At this time, if an "H" signal is input to the wiring TM, A
The ND22 operates to input test data to the circuit within the cell. On the other hand, when an "H" signal is input to the wiring O8, ANDs 19a and 19b become inactive, and the test data is not shifted.

Next, FIG. 12 shows the symbol of the pressure shift register 18b. The wiring G1 is connected to the intra-cell circuit. 1st
FIG. 3 shows the internal circuit of the output shift register 18b.

The wiring SI is connected to the input of AND25. Wiring O
8 is connected to the inputs of AND25 and AND26. AND 25.26 output is AN via 0R27
Connected to the input of D28a. AND 28
A wiring CKI is connected to the other input of a. AND
The output of 28a is ANDed through F/F21a 28b
is connected to the input of The other input of AND28b is connected to the wiring CKO. The output of AND 28 b is connected to wiring SO via F/F 2 l b. The wiring connected to the circuit in the cell (I is the buffer 2
9 to the input of AND 26 and to pad 14. That is, when an "L" signal is input to the wiring O8, the AND 25 operates, and the test data input from the wiring ST is shifted into the F/Fs 21a and 21b in synchronization with the clock signal. On the other hand, when an "H" signal is input to the wiring O8, AND25 becomes inactive, and instead, AND26 operates, and the detection data from the circuit in the cell transmitted to the wiring Gl is synchronized with the clock signal to the F/
It is designed to shift into F21a and F21b.

゛At this stage, when the "L" signal is input to the wiring O3 again, the detection data is transferred from the output shift register 18b to the wiring S.
It is designed to output to O. In addition, the wiring TM, O3
When both the signal level and the signal level are "L" level, the shift register circuit section 17 does not operate.

In this way, in the first embodiment, test data input in series through the test pad 15 and wiring can be converted into parallel signals via the shift register circuit section 17 and transmitted to the circuit within the cell. There is. Furthermore, it is possible to convert the detection data outputted in parallel from the intra-cell circuits into a serial signal via the shift register circuit section 17, and to take out the signal from the test pad 15. For this reason, a small number of test pads 1, for example about 5 to 11
5, it is possible to inspect the circuit inside the cell.

Next, a method for manufacturing the semiconductor integrated circuit device of Example 1 will be explained with reference to FIGS. 1 to 25.

First, in the diffusion step 2 shown in FIG.
- Form source and drain regions of semiconductor devices such as FETs. After that, in the first wiring process 3,
The chip area 10 of the wafer 9 is connected by connecting the semiconductor elements.
The above-mentioned macrocell 11 is formed inside. In the first embodiment, as described above, the macro cells 11 are arranged in the chip region IO, for example, in a grid pattern. Wafer 9 at that time
A cross-sectional view of the main part is shown in FIG. The broken lines in the figure indicate the boundaries of the macrocells 11. The above-described intra-cell circuit, input/output circuit, etc. are formed by intra-cell wiring 30. The dimensions of the intra-cell wiring 30 are, for example, as follows. That is, the wiring width is approximately 2 μm, the wiring thickness is approximately 0.5 μm, and the wiring pitch is approximately 2.5 μm.

In the macro cell testing step 4, the electrical characteristics of each macro cell 11 are tested using, for example, a blow μ.

The inspection items are as follows, for example. That is, the tests include a DC function test, a DC parameter test of input/output terminals, and an AC switching test. The inspection is performed by moving the probe card 31a to each macro cell 11, as shown in FIG. 15, for example. Further, by utilizing the fact that the macro cells 11 are arranged in a lattice pattern, the following may be performed, for example. That is, as shown in FIG. 16, a plurality of macro cells 11 arranged along the column direction may be simultaneously tested using a longitudinal probe card 31b.

In this case, it becomes possible to shorten the inspection time compared to the case where the inspection is performed for each macro cell 11. FIG. 17 and FIG. 18 show the probe needle 32 in macro cell inspection step 4.
Indicates the status of The first thing that is obvious during the inspection is the probe needle 32.
Touch the test pad】5. The test data is transferred from the test pad 15 to the shift register circuit section 1 described above.
7 (see FIG. 7) to the intra-cell circuit. Then, based on the test data, the detection data outputted from the in-cell circuit to the test pad 15 via the shift register circuit section 17 is compared with the expected value. Based on the comparison information, the quality of the macro cell 11 is determined. At this time, quality information of the macro cell 11 is created. The quality information includes
Information such as the location markings of defective macrocells and good macrocells is recorded. In FIG. 19, a defective macro cell lla determined to be defective as a result of the inspection is indicated by diagonal lines.

Next, in the defective macro cell replacement step 5, for example, the following process is performed.

First, as shown in FIG.
Remove with high precision and as quickly as possible using a processing method such as on-beam processing. The liquid metal ion source of the FIB at this time is, for example, gallium (Ga). Further, the acceleration energy is, for example, about 30 KeV. Further, the depth of the removed region is, for example, about 20 μm. However, the defective macrocell lla may be removed from the back side of the wafer 9 or from both sides of the wafer 9. Furthermore, the process for removing the defective macrocell 11a is not limited to the FIB processing method. That is, various modifications can be made as long as the processing method can quickly remove the defective macrocell Ila and does not damage other surrounding macrocells ll. For example, a chemical processing method, a mechanical processing method, a processing method using ultrasonic waves, etc. may be used. In addition, these processing methods and FIB
It may be combined with a processing method. - After removing the defective macrocell lla, as shown in FIG. 21, a good macrocell llb for replacement is placed in the removed area of the defective macrocell lla. The replacement good macrocell llb may be obtained from another wafer or from the same wafer 9.

When obtaining a good macro cell llb for replacement from the same wafer 9, the following may be used, for example. That is, a replacement macrocell region (not shown) for obtaining a good replacement macrocell Ilb is arranged in the vicinity of each chip region IO.

When replacing the defective macrocell lla, a good macrocell lla for replacement is extracted from within the replacement macrocell area near the chip area lO where the defective macrocell lla has occurred.
Get lb. As a result, it becomes possible to approximate the electrical characteristics of the elements, etc. of the replacement good macrocell llb buried in the removal area of the defective macrocell lla and the other macrocells 11.

A good macro cell llb for replacement is obtained from the wafer 9 by, for example, FIB processing, and its thickness is set by back surface polishing or the like. At this time, the thickness of the replacement good macrocell llb is made to be the same as the depth of the removed region of the defective macrocell 11a. As a result, when the replacement good macrocell Ilb is buried in the removal area, the surface level of the replacement good macrocell Ilb and the surface level of the surrounding macrocells 11 are at the same height. Therefore, no step occurs at the boundary between the good replacement macrocell llb and the surrounding macrocells 11. As a result, it becomes possible to prevent disconnection of the inter-cell wiring 16 caused by the step.

After placing the replacement good macrocell Ilb in the removal area of the defective macrocell 11a, the groove between the replacement good macrocell Ilb and the surrounding macrocells 11 is filled in, as shown in FIG. The trench filling is performed by, for example, a photo-CVD method. That is, for example, by laser pyrolyzing molybdenum carbonium at a low temperature of around 150'C,
Fill in the groove. At this time, the groove embedding process is automated by, for example, detecting the end point of embedding. However, when filling the groove, the upper part 33 of the filling ends up rising. However, this induces disconnection of the inter-cell wiring 16. Therefore, in the first embodiment, after the groove embedding process, for example, while monitoring, the embedding upper part 33 is
The area is planarized by cutting using the IB processing method or the like. As described above, it is possible to arrange only good macro cells 11 within the chip area 10. That is, up to this stage, only good chip regions 10 can be formed on the wafer 9.

After that, in the second wiring process 6, each macro cell 1
1 is connected by an inter-cell wiring 16.

Then, a predetermined logic LSI is formed within the chip area 10. A sectional view of the main part of the wafer 9 at that time is shown in FIG.

The dimensions of the inter-cell wiring 16 at this time are, for example, as follows. That is, the wiring width is approximately 4 μm, the wiring thickness is approximately 1 μm, and the wiring pitch is approximately 5 μm. In the first embodiment, for example, the dimensions of the inter-cell wiring 16 are set larger than the dimensions of the intra-cell wiring 30 described above. This is, for example, for the following two reasons. The first reason is to reduce the wiring resistance of the inter-cell wiring 16. Since the inter-cell wiring 16 connects the macro cells 11, the wiring length is longer than that of the intra-cell wiring 30. However, as the wiring length increases, the wiring resistance also increases. Therefore, the wiring resistance is reduced by setting the dimensions of the inter-cell wiring 16 to be larger than the dimensions of the intra-cell wiring 30. The second purpose is to reduce wiring defects after the completion of the secondary wiring process 6. That is, the purpose is to reduce the occurrence of wiring defects during the secondary wiring process 6 by alleviating the sensitivity of the inter-cell wiring 16 to foreign matter. As a result, it becomes possible to suppress a decrease in chip yield due to wiring defects after the defective macro cell replacement step 5. By the way, the good macrocell llb for replacement is
Since it was later embedded in the wafer 9, some positional deviation occurred. However, due to the positional deviation, the replacement good macrocell 11b may not be able to be connected to other macrocells 11 in the chip area 10. Therefore, in the first embodiment, before the wiring pattern is transferred onto the photoresist using, for example, an electron beam direct drawing device, the following data processing is performed, for example. That is, first, the defective macrocell ll
Replacement good macro cell llb buried in the removal area of a.
Create position data. Next, positional deviation correction data is created based on the data. Then, the wiring pattern data of the electron beam direct writing apparatus is corrected based on the positional deviation correction data. Further, as another method for preventing poor connection of the inter-cell wiring 16, for example, the planar dimensions of the pads 14 may be set to be larger from the beginning in consideration of positional deviation.

In the wafer test step 7, the electrical characteristics of the logic LSI are tested for each chip region 10. and,
The quality of each chip area 10 is determined. After that, a wafer scribing process 8 is performed to form a good chip area 10 from the wafer 9.
and end chip production.

As described above, according to the first embodiment, it is possible to obtain the following effects.

(1) It is possible to remove only the defective portions within the chip area 10 and easily correct them at an early stage during the wafer process, that is, at a stage where the defect rate is high due to fineness and high integration. becomes. So, for example, we can do something like this: That is, first, a highly integrated and high-performance macrocell 11 is formed in the chip region 10 using the most advanced process technology. Next, the macrocell 11 is inspected and defects are removed. Then, a good macrocell llb created using the most advanced process technology is placed in the chip area 10 in place of the defective macrocell lla. That is, up to this stage, it is possible to configure the chip region IO with highly integrated and high-performance macrocells 11 created using the most advanced process technology. Thereafter, a large-scale logic LSI is formed within the chip area 10 by connecting the macro cells 11. By doing so, it is possible to reliably repair defects without degrading the performance of the logic LSI, and it is possible to improve the chip yield.

(2) and (11) above, it is possible to suppress the decline in chip yield caused by larger chips and higher integration of semiconductor integrated circuit devices.Therefore, it is possible to increase the capacity and high functionality of semiconductor integrated circuit devices. Therefore, for example, it becomes possible to promote the integration of computer systems into a single chip.

(3) Correct the defect before the logic LSI is formed in the chip area 10, that is, before the entire chip has the function of a predetermined semiconductor integrated circuit, and immediately after the defect is discovered. Therefore, it becomes possible to realize defect relief with high applicability and certainty.

(4) With (3) above, it becomes possible to respond to customization of semiconductor integrated circuits.

(5), above (21, (31), large-scale logic LSI
It becomes possible to proceed with the verification of the logic even during the low yield period in the early stage of development.

(6) By regularly arranging the macro cells 11 and the test pads 15, it is possible to test all the macro cells 11 in the chip area 10 in a short time. In particular, the macro cells 11 are arranged in a grid pattern, and a plurality of macro cells 1 are located on the same straight line during the macro cell inspection step 4.
By testing all macrocells 11 at the same time, it becomes possible to test all macrocells 11 in the chip area 10 in a shorter time.

(7) The test data input through the test pad 15 is converted into a parallel signal via the shift register circuit section 17, the signal is input to the circuit within the cell, and the test data is output in parallel from the circuit within the cell. By converting the detected data into a serial signal via the shift register circuit section 17 and outputting it to the test pads 15, the number of test pads 15 can be significantly reduced. Therefore, the size of the test pad 15 can be set to the size necessary for probe testing. As a result, high integration,
Moreover, it becomes possible to inspect the electrical characteristics of the fine macrocell 11.

(8) By obtaining a good macro cell llb for replacement from the wafer 9 from which the bad macro cell lla has been removed, the electrical characteristics of the elements, etc. of the good macro cell llb for replacement and the other macro cells 11 in the chip area 10 are evaluated. It becomes possible to approximate.

(9) By setting the surface level of the replacement good macro cell llb and the surrounding macro cells 11 at the same height, those macro cells 11. There is no difference in level between llb. Therefore, it is possible to prevent disconnection of the inter-cell wiring 16 due to the step.

Molybdenum carbonium or the like is embedded between the head and the good replacement macrocell llb and the surrounding macrocell 11,
After fixing the good macro cell llb for replacement, the buried upper part 33 is flattened, so that no step is caused by the buried upper part 33. Therefore, it is possible to prevent disconnection of the inter-cell wiring 16 due to the step.

αD, by setting the cross-sectional area of the inter-cell wiring 16 to be larger than the cross-sectional area of the intra-cell wiring 30, it is possible to suppress an increase in resistance of the inter-cell wiring 16, which has a relatively long wiring length. That is, it becomes possible to suppress wiring delays and the like. Furthermore, the sensitivity of the inter-cell wiring 16 to foreign matter is alleviated, making it possible to reduce defects in the inter-cell wiring 16.

0z, the above (9) to αυ make it possible to reduce wiring defects after the defective macro cell replacement step 5.

In other words, it is possible to suppress a decrease in chip yield due to wiring defects after the defective macro cell replacement step 5.

α3. The above (2), α2, makes it possible to reduce product costs.

[Embodiment 2] FIG. 24 is a process diagram showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. Figures 26 and 27
The figure is a cross-sectional view of a main part of the wafer for explaining the process of forming dividing grooves on the wafer main surface, FIG. 28 is a plan view of the main parts of the wafer shown in FIG. 27, and FIG. FIG. 30 is a cross-sectional view of a main part of a wafer to explain a modification of the method for forming the dividing grooves on the back side of UNINO. FIG. FIG. 32 is a cross-sectional view of the main part of the wafer for explaining the process of assembling a good macro cell for replacement. FIG. 33 is a cross-sectional view of the main part of the wafer for explaining the process of fixing the good macro cell. Figure 34 is a cross-sectional view of the main part of the wafer for explaining the process of burying side grooves on the main surface of the wafer;
The figure is a sectional view of the main part of the wafer immediately after the planarization process on the main surface of the wafer is completed.

FIG. 24 shows the manufacturing process of the semiconductor integrated circuit device of Example 20. The steps other than the defective macrocell replacement step 5 are the same as in the first embodiment. The defective macro cell replacement process 5 includes seven processes, for example, processes 5a to 5g.

Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the second embodiment will be explained in accordance with the steps shown in FIG. 24 with reference to FIGS. 25 to 35.

A cross-sectional view of the main part of the wafer 9 immediately after the completion of the first wiring process 3 is shown in FIG. The wafer 9 of the second embodiment is, for example, SOI (Silicon On In5ulat).
or) structure wafer. The semiconductor layer 9a is made of, for example, single crystal Si. An insulating layer (insulating layer inside the wafer) 9b is formed on the semiconductor layer 9a. Insulating layer 9b
is made of, for example, SiO*, and its thickness is, for example, 0
．． It is about 5 μm. A semiconductor layer 9 is formed on the insulating layer 9b.
C is formed. The semiconductor layer 9C is made of, for example, single crystal S.
i, and is formed by, for example, epitaxial growth. A semiconductor integrated circuit element is formed in the semiconductor layer 9C, and the layer thickness thereof is, for example, about 2 to 3 μm. Further, in the semiconductor layer 9C, an insulator (principal surface side dividing groove forming member) 34 for element isolation between macro cells is formed along the outer periphery of each macro cell 11. The insulator 34 is made of, for example, S i O*.

The width of the insulator 34 is, for example, about 0.5 μm, and the depth of the insulator 34 reaches a position slightly deeper than the insulating layer 9b. A multilayer wiring layer 9d is formed on the semiconductor layer 9C. The multilayer wiring layer 9d includes intra-cell wiring 30.
or is formed. The thickness of the multilayer wiring layer 9d is, for example, 3
~5 μm. Wafer 9 including multilayer wiring 19d
The thickness is, for example, about 500 μm. In addition, the 25th
The broken lines in the figure indicate the boundaries of the macrocells 11.

In the macro cell inspection step 4 for such a wafer 9, similarly to the first embodiment, the probe needle 32 (see FIG. 18) is brought into contact with the test pad 15 of each macro cell 11 to check the quality of each macro cell 11. judge. At this time, for example, position data of the defective macrocell 11a and the like are transmitted to a pattern data storage area of an electron beam direct lithography apparatus (not shown).

Next, in the defective macrocell replacement step 5, the 24th
Defective macrocell lla according to steps 5a to 5f shown in the figure
is replaced with a good macro cell as described below.

In the wafer main surface side dividing groove forming step 5a, the following processing is performed.

First, as shown in FIG. 26, on the multilayer wiring layer 9a,
For example, after applying the resist 35 for electron beam direct writing,
Pattern data is formed on the resist 35 by an electron beam direct writing method. The pattern data at this time is automatically created based on the position data of the defective macrocell lla described above. That is, only the resist portion located at the outer periphery of the defective macrocell lla is removed. The convergence of the resist removal area is
For example, it is about 2 to 3 μm.

Then, as shown in FIG. 27, a main surface side U-groove (main surface side dividing groove) 36 is formed using the resist 35 as a mask. The main surface side U groove 36 is made of, for example, Si○.

RI with conditions set to selectively etch only
The multilayer wiring layer 9d under the resist removed area is removed by the E method or the like.
Then, the insulator 34 for element isolation between macro cells is removed by etching. A plan view of the wafer 9 after this treatment is shown in FIG. As shown in FIG. 28, a main surface side U-groove 36 is formed only on the outer periphery of the defective macrocell lla. As described above, in the second embodiment, the main surface side U-groove 36 is formed with the processing precision of photolithography technology. For this reason, the plane and cross-sectional shape and processing dimensions of the main surface side U-groove 36, the dimensions of the removal area of the defective macrocell lla, etc. are controlled with extremely high precision (±
0.1 μm).

Then, the shape and dimensions of the main surface side U-groove 36, the dimensions of the removed region of the defective macrocell lla, etc. can be reproduced well. Therefore, it is possible to always perform extremely good alignment and installation of a good macro cell for replacement, which will be described later.

Next, in the wafer back side dividing groove forming step 5b,
As shown in FIG. 29, from the back surface side of the wafer 9 to the main surface side U
A back side U groove (back side dividing groove) 37 reaching the groove 36 is formed. In order to form the back surface 111U groove 37, a resist (not shown) is used as a mask and is formed by, for example, an RIE method under conditions such that only Si is selectively etched. By the way, the insulating layer 9b constituting the wafer 9 is St
Since it is made of ow etc., it acts as an etching stopper layer when forming the U-groove 37 on the back side. For this reason, when forming the backside U-groove 37, the cross-sectional shape of the main-surface side U-groove 36 may be deformed, or the machining dimensions of the main-surface side U-groove 36, the machining dimensions of the defective macrocell removal area, etc. may change. There's nothing to do.

Therefore, the advantages of positioning and incorporating a good macrocell for replacement are not impaired. Also, the back side U
When forming the groove 37, the macro cell 11 is
Furthermore, there is no possibility of damage to the semiconductor integrated circuit elements in the defective macrocell lla. Therefore, this macro cell extraction method can be used as a method for manufacturing good macro cells for replacement. The reason why the grooves 37 are formed from the back side of the wafer 9 in this way is that the groove processing accuracy on the back side of the wafer 9 is lower than that on the wafer main surface side (±5 μm).
Therefore, as will be explained later, there is some choice in the groove machining method.
This is because the groove machining time can be shortened. The method for forming the back surface 111U groove 37 is not limited to dry etching methods such as RIE, and can be modified in various ways, for example, the following method may be used. First, the third
As shown in FIG. 0, a U-groove 37a is formed in the middle of the semiconductor layer 9a, for example, from the back surface of the wafer 9 to a depth of about 450 μm using a dicing blade with a diameter of about 1 to 2 mtn. Thereafter, the remaining semiconductor layer 9a is etched by RIE, etc., with conditions set so that only Si is selectively etched.
is removed by etching to complete the U-groove 3 on the back side shown in FIG. In this case, the time required to form the backside U-groove 37 can be shortened. Alternatively, after forming the U groove 27a in FIG. 30 by wet etching, the remaining portion may be removed by dry etching.

Furthermore, as another method for forming the back side U-groove 37, for example, an ultrasonic processing method, a laser processing method, etc. may be used.

Next, in the defective macrocell removal step 5C, the defective macrocells 11a divided from the wafer 9 are removed.

FIG. 31 shows a sectional view of the main part of the wafer 9 immediately after the completion of this step 5c.

In the subsequent good macrocell integration step 5d, the third
As shown in FIG. 2, a good macrocell llb for replacement is placed in the defective macrocell removal area.

The good macrocell llb is taken out from another S01 structure wafer in the same manner as the bad macrocell lla as described above. In order to arrange the good macrocell llb in the bad macrocell removal area, for example, the following procedure is performed. First, the wafer 9 from which the defective macrocell 11a has been removed is
It is placed on the θ stage 38. Take control, stick 39
A predetermined adhesive 4 is applied to the lower surface of the good macrocell Ilb and the main surface of
0, the good macrocell Ilb is moved above the defective macrocell removal area of the wafer 9. As a method for holding the good macrocell llb, for example, a vacuum pad may be used. Thereafter, alignment is performed, and the good macrocell llb is moved downward in FIG. 32 and placed in the defective macrocell removal area.

In the good macrocell fixing step 5e, as shown in FIG. 33, a resin 41 such as polyimide is filled into the backside U-groove 37 to fix the good macrocell llb.

However, the resin 41 is not limited to polyimide, and can be changed in various ways. For example, the resin 41 may have properties such as a coefficient of thermal expansion close to that of Si, ease of filling into the U groove on the back side, and high thermal conductivity. Which material is preferred?

Next, in the main surface side dividing trench burying step 5f, as shown in FIG. Fill the groove 36.

In the subsequent wafer main surface side flattening step 5g, for example, the following process is performed. First, as shown in FIG. 34, a planarizing insulating film 43 is deposited on the insulating film 42. Then, as shown in FIG. At this time, the planarizing insulating film 43 is deposited to such an extent that the upper surface thereof becomes substantially flat.

Thereafter, the planarizing insulating film 43 is etched back by, for example, RIE, and the upper surface of the insulating film 42 is planarized as shown in FIG. 35.

Thereafter, the process moves to a second wiring process 6. The secondary wiring step 6 and subsequent steps are the same as in the first embodiment.

As described above, according to the second embodiment, it is possible to obtain the following effects.

(1) Since the U-groove 36 on the main surface side is formed with the precision of photolithography technology (±0.1 μm), defective macrocells
Dimensions of removal area of la and good macrocell for replacement
The precision of the processing dimensions b can be made extremely high, and the reproducibility of those dimensions etc. can also be improved. Also, when forming the back side U groove 37 by etching,
By using the insulating layer 9b as an etching stopper layer,
There is no reduction in the machining dimensional accuracy of the main surface side U-groove 36.

Therefore, when arranging the good macrocell llb in the defective macrocell removal area, it is possible to always perform its alignment, integration, etc. very well.

(2) According to (1) above, it is possible to make the flatness of the incorporated good macrocell 11b and the surrounding macrocells 11 extremely good.

(3), above fl+, (2) makes it possible to provide a highly reliable and good macro cell integration technology.

(4) When removing the defective macro cell Ilb, only the outer periphery of the defective macro cell Ilb needs to be grooved, so that the area to be removed can be significantly reduced compared to the case of the first embodiment. Therefore, the time required to remove the defective macrocell lla can be significantly shortened compared to the first embodiment.

(5) Machining of the U-groove 37 on the back side requires lower machining accuracy (±5 μm) than that on the main surface side, so it is possible to perform rougher machining than on the main surface side, and there is room for choice in the machining method. There is. Therefore, by forming grooves from the back side, it is possible to significantly shorten the groove processing time, for example, by selecting a processing method.

(6) Since the macrocell 11 can be taken out from the wafer 9 without damaging the inside of the macrocell 11, it becomes possible to manufacture a good macrocell Ilb by the same method used to remove the defective macrocell I1g. That is, it becomes possible to make the removal process for the defective macrocell lla and the manufacturing process for the good macrocell llb common.

(7) With the above (4) to (6), it is possible to achieve high throughput.

The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to Examples 1 and 2, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, in Embodiment 1.2, a case has been described in which a good replacement macro cell is placed in the chip area instead of a defective macro cell, but the invention is not limited to this. It may be placed in That is, by arranging macro cells having different circuit functions, it becomes possible to convert the logic function or expand the circuit function. For example, the 36th
As shown in the figure and Fig. 37, the R
ISC (Reduced In5truccio)
0EIC (Optical Elect) is installed on the chip 44, such as a
ronics Integrated C1rcuit
s) It is also possible to embed the cell 45. The 0EIC cell 45 may be placed in the defective macro cell removal area, or
It may be placed elsewhere. In this case, an optical fiber 4 is used in the signal transmission path between the chip 44 and the main memory or external memory.
By using 6, it becomes possible to transfer data at extremely high speed between them. Therefore, by using the chip 44 in, for example, a workstation, it is possible to significantly improve the performance of the workstation.

In other words, it becomes possible to create new product value.

In addition, in Example 1.2, a case was explained in which a prober was used in the macro cell inspection process.
The method is not limited to this, and for example, an EB tester may be used.

Furthermore, in the first embodiment, a case has been described in which a defective macro cell determined to be defective in the macro cell inspection process is removed, but the present invention is not limited to this.
For example, you may do as follows. That is, a spare macro cell is placed in advance in the chip area. The spare macrocells are distributed, for example, within the chip area. Similarly to the embodiments described above, macro cell quality information is created through a macro cell inspection process. Thereafter, in the secondary wiring process, wiring processing is not performed on defective macrocells based on the quality information of the macrocells.

Then, a good macrocell among the spare macrocells is used in place of the defective macrocell. In this way, a predetermined semiconductor integrated circuit is formed within the chip area.

Alternatively, for example, the following may be used. In other words, the intra-cell wiring within each macro cell in the chip area is inspected,
If a defect such as a disconnection or a short circuit is found in the intra-cell wiring, the defective location is corrected using an FIB processing method or the like. It also creates pass/fail information for macro cells within the chip area.

In the second wiring process, a predetermined semiconductor integrated circuit is formed by connecting good macrocells with wires based on the quality information. In either case, defects are removed at an early stage of the sea urchin process, making it possible to realize a highly reliable and highly applicable defect repair technique. Moreover,
Since the process of removing defective macrocells and burying good macrocells for replacement are not performed, the number of man-hours can be reduced accordingly.

In addition, in the second embodiment, the case where the dividing grooves are formed first from the main surface side of the wafer has been described, but the invention is not limited to this. For example, the insulation of the SOI wafer is first formed from the back surface side of the wafer. A dividing groove may be formed that reaches the layer. In this case as well, it is preferable to use the insulating layer of the SOI wafer as an etching stopper layer.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

(1), that is, according to the invention of claim 1 described above, in the initial stage of the wafer process, that is, the fine
Because of the high degree of integration, it is possible to remove only the defective portion within the chip area and easily repair the defective portion at a stage where the defect occurrence rate is high. So, for example, we can do something like this: That is, first, a macro cell is formed within the chip area using the most advanced process technology up to the first wiring process. Next, if a defective macrocell occurs, it is removed.

Then, good macrocells manufactured using the most advanced process technology are placed in the area where the defective macrocells have been removed.

By doing this, it is possible to reliably repair defects without degrading the performance of the semiconductor integrated circuit, and it is possible to improve the chip yield.As a result, it is possible to increase the size of semiconductor integrated circuit devices. - It is possible to suppress the decline in chip yield due to higher integration, and it becomes possible to respond to larger capacity and higher functionality of semiconductor integrated circuit devices.

Therefore, for example, it becomes possible to promote the integration of computer systems into a single chip. In addition, at a stage before a predetermined semiconductor integrated circuit is formed in the chip area, that is,
Since the defect is repaired before the entire chip area has a function as a predetermined semiconductor integrated circuit and immediately after the defect is discovered, it is possible to realize defect repair with high applicability and reliability. As a result, it becomes possible to respond to customization of semiconductor integrated circuit devices.

(2) According to the invention described in claim 2, by simultaneously testing a plurality of macrocells when testing a macrocell, it is possible to test all macrocells in a chip area in a short time.

(3) According to the above-mentioned invention as claimed in claim 3, by obtaining a good macro cell for replacement to be buried in the removal area of the defective macro cell from the same wafer, the good macro cell for replacement and other good macro cells in the chip area are It becomes possible to approximate the electrical characteristics of elements, etc. in the macro cell.

(4) According to the invention set forth in claim 4 above, by setting the surface level of the replacement good macrocell buried in the removal area of the defective macrocell and the surrounding macrocells to be at the same height, the good macrocell is removed. When a macrocell is buried in a region from which a defective macrocell has been removed, no step is created between the good macrocell and surrounding macrocells due to the difference in surface position of those macrocells. Therefore, it is possible to prevent disconnection of inter-cell wiring caused by the step. Therefore, it is possible to reduce wiring defects in the secondary wiring process, and it is possible to suppress a decrease in chip yield due to wiring defects after the defective macro cell replacement process.

(5) According to the invention set forth in claim 5 above, the upper part of the material buried in the groove between the replacement good macrocell buried in the defective macrocell removal area and the surrounding macrocells is flattened. As a result, there is no difference in level caused by the buried material between the good macrocell buried in the removal area of the defective macrocell and the surrounding macrocells. Therefore, it is possible to prevent disconnection of inter-cell wiring caused by the step. Therefore, it is possible to reduce wiring defects in the secondary wiring process, and it is possible to suppress a decrease in chip yield due to wiring defects after the defective macro cell replacement process.

(6) According to the invention described in claim 6, by making the cross-sectional area of the inter-cell wiring larger than that of the intra-cell wiring,
It is possible to suppress an increase in the wiring resistance of the inter-cell wiring, which has a relatively long wiring length. That is, it becomes possible to suppress wiring delays and the like. Furthermore, the sensitivity to foreign substances in the inter-cell wiring is alleviated, making it possible to reduce wiring defects in the secondary wiring process. Therefore, it is possible to suppress a decrease in chip yield due to wiring defects after the defective macrocell replacement step.

(7) With the above (1) to (6), it is possible to significantly improve the chip yield and reduce the cost of semiconductor integrated circuit devices.

(8) According to the invention set forth in claim 7, since the main surface side dividing groove is formed with the precision of photolithography technology, the dimensional accuracy of the defective macrocell removal area or the good macrocell can be extremely high. The reproducibility of these dimensions can also be improved. Furthermore, by using the insulating layer as a stopper layer when forming the back side dividing grooves, the dimensional accuracy of the main side dividing grooves is not reduced. That is, when forming the back-side dividing grooves, the dimensional accuracy of the defective macrocell removal area and the good macrocells does not deteriorate. Therefore, when arranging a good macrocell in the defective macrocell removal area, it is possible to perform alignment, integration, etc. extremely well. Furthermore, the machining accuracy of the back side dividing groove is lower than that of the main side, so it is possible to process the dividing groove rougher than that of the main side dividing groove, and there is room for choice in the machining method.As a result, the dividing groove It becomes possible to significantly shorten the formation time.

(9) According to the invention as set forth in claim 8 above, by arranging macro cells having different types of circuit functions in the chip area, the logical function of the semiconductor integrated circuit is converted;
It becomes possible to expand the functions of semiconductor integrated circuits. Therefore, it becomes possible to create new product value.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is an overall plan view of a wafer showing the chip area after the completion of the first wiring process, and FIG. FIG. 4 is an enlarged plan view of the chip area shown in FIG. 2, FIG. 4 is an enlarged plan view of the macrocell formed in the chip area shown in FIG. 3, and FIGS. Fig. 7 is a circuit diagram showing the shift register circuit formed in the macro cell shown in Fig. 4, and Fig. 8 is an enlarged plan view of the macrocell to explain the reason why the shift register circuit is synchronized. Fig. 9 is a diagram showing the signal level of the control line during operation of the shift register circuit section, Fig. 1O is a symbol diagram of the input shift register, Fig. 11 is shown in Fig. 10. Figure 12 is a symbolic diagram of the output shift register, Figure 13 is the internal circuit diagram of the output shift register shown in Figure 12, Figure 14 is the primary wiring process. 15 is an enlarged plan view of the chip area in the macro cell inspection process; FIG. 16 is an enlarged plan view of the chip area showing a modification of the macro cell inspection method; FIG. 17 is the macro cell inspection process. FIG. 18 is an enlarged plan view of the macrocell in the process. FIG. 18 is a sectional view of the main part of the wafer in the macrocell inspection process. FIG. 19 is an enlarged plan view of the chip area showing a defective macrocell. FIG. 21 is a cross-sectional view of the main part of the wafer when a replacement macro cell is placed in the defective macro cell removal area, and FIG. 22 is a main part of the wafer showing a state in which the replacement macro cell is buried in the defective macro cell removal area. 23 is a sectional view of a main part of the wafer immediately after the completion of the secondary wiring process; FIG. 24 is a process diagram showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG. 25 26 and 27 are sectional views of the main parts of the wafer for explaining the process of forming dividing grooves on the main surface of the wafer, and FIG.
7 is a plan view of the main part of the wafer, FIG. 29 is a sectional view of the main part of the wafer for explaining the step of forming dividing grooves on the back side of the wafer, and FIG. 30 shows a modification of the method for forming the dividing grooves on the back side of the wafer. FIG. 31 is a cross-sectional view of the main part of the wafer immediately after the defective macro cell removal process is completed, and FIG. 32 is a cross-sectional view of the main part of the wafer to explain the process of installing a good replacement macro cell. Figure 33 is a cross-sectional view of the main part of the wafer to explain the process of fixing a good macro cell, Figure 34 is a cross-sectional view of the main part of the wafer to explain the process of filling side grooves on the main surface of the wafer, and FIG. 36 is a cross-sectional view of a main part of the wafer immediately after the end of the surface-side planarization process, FIG. FIG. 37 is a side view of the chip area shown in FIG. 36; 1... Wafer manufacturing process, 2... Diffusion process, 3...
Primary wiring process, 4... Macro cell inspection process, 5...
- Defective macro cell replacement step, 5a... Wafer main surface side dividing groove forming step, 5b... Wafer back side dividing groove forming step, 5c... Defective macro cell removal step, 5d... Good macro cell integration step, 5e ... Good macro cell fixing process, 5f... Wafer main surface side dividing groove filling process, 5g
...Wafer main surface side flattening process, 6...Second wiring process, 7...Wafer test process, 8...Wafer scribing process, 9...Wafer, 9a...Semiconductor layer, 9b
... Insulating layer, 9C... Semiconductor layer, 9d... Multilayer wiring layer, 10... Chip area, 11... Macro cell,
lla... Defective macro cell, llb... Good macro cell for replacement, 12... Circuit area in cell, 13... Input/output circuit area, 14... Pad, 15... Test pad, 16... ... Inter-cell wiring, 17... Shift register circuit section, 18... Shift register, 18a... Input shift register, +8b... Output shift register, 19a, 19b, 20a, 20b, 22, 23,2
5, 26.28a. 28b---AND, 21a, 21b=flip-flop, 24.27...OR, 29...buffer, 30
... Wiring inside the cell, 31a, 31b... Probe card, 32... Probe needle, 33... Embedded upper part,
34...Insulator (main surface side dividing groove forming member), 35...
・Resist, 36...Main surface side U groove (main surface side dividing groove),
37...Back side U groove (back side dividing groove), 37a...
U groove, 38...XYθ stage, 39...stick, 40...adhesive, 41...resin, 42...insulating film, 43...flattening insulating film, 44...chip , 4
5...0EIC cell, 46...Optical fiber, D, C
KO, CKI, OS. TM, Sl, So, Gl, Go... wiring. Agent Patent Attorney Daiwa Tsutsui Figure 1, Figure 2, 11: Mac0 Cell, Figure 3, Figure 4, Figure 15: Test Pad, Figure 8, Figure 10, Figure 1, Figure 16, Figure 17, J 14, 24 figure

Claims (1)

[Claims] 1. After forming a predetermined semiconductor integrated circuit element in a chip area on a semiconductor wafer, a plurality of macro cells having the same circuit function are regularly arranged in the chip area through a first wiring process. At the same time, test pads connected to the main circuit section in the macro cell through a shift register circuit section formed inside the macro cell are regularly arranged in each macro cell, and then test pads are connected to the main circuit section in the macro cell through a shift register circuit section formed inside the macro cell. When testing the electrical characteristics of the Converts the detection data output in parallel from the unit into a serial signal via the shift register circuit unit and outputs it to the test pad, and determines the quality of the macro cell by comparing the output detection data with the expected value, Based on the determination result, macrocell pass/fail information is created, and after removing the defective macrocell based on the pass/fail information, good macrocells are buried in the removed area, and a second wiring process is performed between the macrocells in the chip area. 1. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a predetermined semiconductor integrated circuit within a chip region by connecting the two. 2. The semiconductor according to claim 1, wherein the macro cells are arranged in a grid in a chip area, and when testing the macro cells, a plurality of macro cells arranged in a row direction or a column direction are simultaneously tested. A method of manufacturing an integrated circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the good macrocell is obtained from a semiconductor wafer to be inspected. 4. The semiconductor integrated device according to claim 1, wherein when burying a good macrocell in the region from which the defective macrocell has been removed, the surface level of the good macrocell and the surface level of surrounding macrocells are set to be the same height. A method of manufacturing a circuit device. 5. When burying a good macrocell in the region from which the defective macrocell has been removed, a metal or its compound is embedded between the good macrocell and the surrounding macrocells, and after the good macrocell is fixed, the buried upper part of the metal or its compound is buried. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the planarization is performed to match the surface of the macro cell. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the cross-sectional area of the wiring connecting between the macro cells is made larger than the cross-sectional area of the wiring within the macro cell. 7. The electrical characteristic test is performed on the macrocell formed in the chip area of the SOI structure semiconductor wafer having an insulating layer between the semiconductor layers, and based on the result, the main surface of the semiconductor wafer is placed on the outer periphery of the defective macrocell. The defects are eliminated by a step of forming a main surface side dividing groove reaching the insulating layer from the side using a photolithography technique, and a step of forming a back side dividing groove reaching the main surface side dividing groove from the back side of the semiconductor wafer. After the macrocell is taken out, a good macrocell taken out from the semiconductor wafer or another SOI structure semiconductor wafer is placed and fixed in the removal area of the bad macrocell in the same manner as the method for taking out the bad macrocell. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 8. After forming a predetermined semiconductor integrated circuit element in a chip region on a semiconductor wafer, a plurality of macro cells having the same circuit function are regularly formed in the chip region by a first wiring process, and Test pads connected to the main circuit section in the macro cell through the internally formed shift register circuit section are regularly formed in each macro cell, and then the electrical characteristics of each macro cell in the chip area are tested. When testing, the test data input serially through the test pad is converted into a parallel signal via a shift register circuit section, and the signal is input into the main circuit section;
Based on the test data, the detection data output in parallel from the main circuit section is converted into a serial signal via the shift register circuit section and output to the test pad, and macro cell information is created based on the output detection data. After removing a predetermined macro cell based on macro cell information, burying a macro cell having different types of circuit functions in a predetermined removal area,
A method of manufacturing a semiconductor integrated circuit device, further comprising connecting macro cells within the chip region in a second wiring step to form a predetermined semiconductor integrated circuit within the chip region. 9. After forming a predetermined semiconductor integrated circuit element in a chip area on a semiconductor wafer, a plurality of macro cells having the same circuit function are regularly formed in the chip area by a first wiring process, and the macro cells are Test pads connected to the main circuit section in the macro cell through the internally formed shift register circuit section are regularly formed in each macro cell and are unified to test the electrical characteristics of each macro cell in the chip area. When doing so, the test data input serially through the test pad is converted into a parallel signal via the shift register circuit section, the signal is input to the main circuit section, and the test data is output in parallel from the main circuit section. The detected data is converted into a serial signal via the shift register circuit and output to the test pad, and the quality of the macro cell is determined by comparing the output detected data with the expected value, and based on the determination result. After creating macrocell quality information, when forming a predetermined semiconductor integrated circuit in the chip area by connecting good macrocells in the chip area based on the quality information in a secondary wiring process, 1. A method for manufacturing a semiconductor integrated circuit device, characterized in that a good macrocell out of spare macrocells formed in the first step is used in place of a defective macrocell. 10. After forming a predetermined semiconductor integrated circuit element in a chip area on a semiconductor wafer, a plurality of macro cells having the same circuit function are regularly formed in the chip area by a first wiring process, and the macro cells are Test pads connected to the main circuit section in the macro cell through the internally formed shift register circuit section are regularly formed in each macro cell, and then the electrical characteristics of each macro cell in the chip area are tested. When doing so, the test data input in series through the test pad is converted into a parallel signal via the shift register circuit section, the signal is input to the main circuit section, and the test data is output in parallel from the main circuit section. The test data is converted into a serial signal via the shift register circuit and output to the test pad, and the output detection data is compared with the expected value to determine the quality of the macro cell, as well as to inspect the wiring within the macro cell. As a result of the inspection, if a defect is found in the wiring within the macrocell, the defective part of the wiring is corrected, and then pass/fail information for the macrocell is created.Then, the second wiring process is performed to inspect the wiring within the chip area. A method for manufacturing a semiconductor integrated circuit device, characterized in that a predetermined semiconductor integrated circuit is formed in a chip region by connecting good macro cells based on the quality information.