JPH05190509A - Etching method - Google Patents

Abstract

PURPOSE:To provide an etching method with which the irregularity in size of trench aperture part can be reduced and also a trench, having desired shape inclined in desired direction, can be formed at the desired position of a semiconductor substrate. CONSTITUTION:The etching method, with which an inclined trench 22 is formed on a semiconductor substrate 10 by dry etching, consists of the following processes: (A) A process in which an etching-resisting layer is formed on the semiconductor substrate 10. (B) A process in which an aperture 16 is formed on the etching-resisting layer and a part of the semiconductor substrate 10 is exposed. (C) A process in which regions 12A and 12B, having different thermofluidity, are formed on the circumference of the aperture 16. (D) A process in which a heat treatment is conducted on the etching-resisting layer and an inclined part 20 is formed on the region 12A having high thermofluidity. (E) A process in which a part of the exposed semiconductor substrate is dry- etched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an etching method for forming an inclined trench in a semiconductor substrate by dry etching.

[0002]

2. Description of the Related Art In a semiconductor device, many circuit elements such as transistors and diodes are formed close to each other on the same substrate. Since the substrate is a semiconductor, electrical continuity occurs between the circuit elements via the substrate as it is. Therefore, it is necessary to form element isolation regions in order to perform such isolation between circuit elements.

Forming the inter-element isolation region diagonally for the purpose of, for example, lengthening the path length of the parasitic thyristor generated around the formed inter-element isolation region to prevent latch-up of the parasitic thyristor. Is proposed. To form the element isolation region obliquely, first, an inclined trench is formed in the semiconductor substrate, and then the trench is filled with an insulator such as silicon oxide.

As a method of forming an inclined trench,
A method of utilizing a fragile portion of a SiO ₂ film formed by the CVD method has been proposed (see Japanese Patent Laid-Open No. 61-26239). FIG. 5 is a schematic explanatory diagram of this method. According to this method, as shown in FIG.
A first SiO ₂ film 100 is formed in the upper predetermined region by a CVD method, and then a second SiO ₂ film 102 is formed by a CVD method so as to cover the first SiO ₂ film 100. next,
The second SiO ₂ film 1 is formed by performing reactive ion etching (RIE) using chlorine gas at a low pressure to increase ionicity.
02 is etched. Since the step portion 104 of the second SiO ₂ film 102 is weaker than the other portions, it is etched earlier. As a result, as shown in FIG. 5B, a second SiO ₂ film 102 having an oblique opening cross section is formed. By using the second SiO ₂ film 102 having such an opening cross section as an etching resistant layer and performing subsequent etching, inclined trenches 106 are formed in the semiconductor substrate 10 as shown in FIG. 5C. It

As another method for forming a tilted trench, a method has been proposed in which two layers made of materials having different etching resistances are placed opposite to each other with a portion serving as an opening portion of the trench being sandwiched on a semiconductor substrate ( JP-A-61-2623
No. 9). FIG. 7 is a schematic explanatory diagram of this method.
According to this method, first, as shown in FIG. 7A, on the semiconductor substrate 10, a portion 116 to be an opening portion of a trench.
A sandwiching A, a SiO ₂ film 110 and a photoresist film 112 having a lower etching resistance than SiO ₂ are formed. Next, the photoresist film 112 is heat-treated to form an inclined portion on the step portion 114. Next, the SiO ₂ film 110 and the photoresist film 112 are used as an etching resistant layer, and reactive ion etching is performed to form the inclined trench 116 in the semiconductor substrate 10 as shown in FIG. 7B. Form.

[0006]

[Problems to be Solved by the Invention] However, CVD
In the method shown in FIG. 5, which uses the fragile portion of the second SiO ₂ film 102 formed by the method, the first SiO ₂ film 100 is formed.
Step 1 of the second SiO ₂ film 102 formed around the
In order to utilize 04, the trench 106 has a first Si
A loop is formed around the O ₂ film 100, and the bottom of the trench 106 is formed only in a direction toward the first SiO ₂ film 100. FIG. 6 is a plan view showing this state. Therefore, it is difficult to form the trench inclined in the desired direction only at the desired position on the semiconductor substrate. In addition, in FIG.
The second SiO ₂ film 102 is shaded. Further, the region of the first SiO ₂ film 100 is shown by a broken line.

Further, in the method shown in FIG. 7 in which two layers having different etching resistances are opposed to each other, when the two layers are actually formed, misalignment due to the photolithography method occurs. There is a problem that it is difficult to make the dimensions of the etching layer constant, and therefore the dimensions of the trench opening cannot be made constant.

Therefore, an object of the present invention is to provide an etching method capable of reducing the variation in the size of the trench opening and forming a trench having a desired shape inclined in a desired direction at a desired position on a semiconductor substrate. To provide.

[0009]

In order to achieve the above object, a first aspect of the etching method of the present invention for forming an inclined trench in a semiconductor substrate by dry etching is characterized by the following steps. And (A) Step of forming an etching resistant layer on a semiconductor substrate (b) Step of forming an opening in the etching resistant layer to expose a part of the semiconductor substrate (c) Different heat flow to the etching resistant layer around the opening (D) A step of performing a heat treatment on the etching resistant layer to form an inclined portion in a region having high heat fluidity (e) A step of dry etching a part of the exposed semiconductor substrate

In order to achieve the above object, a second aspect of the etching method of the present invention for forming a tilted trench in a semiconductor substrate by dry etching is characterized by the following steps. (A) Step of forming an etching resistant layer on a semiconductor substrate (b) Step of forming a region having different heating fluidity in the etching resistant layer (c) Forming an etching resistant layer at the boundary between regions having different heating fluidity Step of forming an opening and exposing a part of the semiconductor substrate (d) Step of subjecting the etching resistant layer to a heat treatment to form an inclined part in a region having high heating fluidity (e) Exposing the exposed part of the semiconductor substrate Dry etching process

The step of forming the regions having different heating fluidity is performed by making one of the regions having different heating fluidity 50 °.
It is preferably composed of immersion in warm water of C or higher.

The etching resistant layer is preferably made of silicon dioxide containing one or more elements selected from the group of phosphorus (P), boron (B) and arsenic (As).
Specifically, examples of a material suitable for the etching resistant layer include silicon dioxide containing boron and phosphorus (BPSG), silicon dioxide containing phosphorus (PSG), and silicon dioxide containing arsenic (AsSG). ..

For example, a resist pattern is formed on the etching resistant layer by photolithography, and then the etching resistant layer is etched by reactive ion etching (RIE) to form a trench opening portion of the semiconductor substrate. The opening can be easily formed in the corresponding etching resistant layer.

According to the first aspect of the etching method of the present invention, after forming an opening in the etching resistant layer corresponding to the portion where the trench opening of the semiconductor substrate is to be formed, the shape of the trench to be formed is changed. Thus, regions having different heat fluidity are formed in the etching resistant layer around the openings. For example, in the case of forming a trench having a groove-shaped planar shape in a semiconductor substrate, after forming a groove-shaped opening in the etching resistant layer, a low heat flow rate is applied to the etching resistant layer in one region across the opening. It is only necessary to impart the property. Further, in the case of forming a trench having a cylindrical planar shape, after forming a cylindrical opening in the etching resistant layer, the etching resistant layer around the opening is appropriately divided into two and the etching resistant of one region is formed. It suffices to impart low heat fluidity to the layer.

According to the second aspect of the etching method of the present invention, regions having different heat fluidity are formed in the etching resistant layer. Next, an opening is formed in the etching resistant layer corresponding to a portion where the trench opening of the semiconductor substrate is to be formed, which is a boundary portion of regions having different heating fluidity, according to the shape of the trench to be formed. To do. Next, for example, when forming a trench having a groove-shaped planar shape in the semiconductor substrate, a groove-shaped opening is formed in the etching resistant layer.
Further, when forming a trench having a cylindrical planar shape,
A cylindrical opening is formed in the etching resistant layer.

[0016]

[Function] Silicon dioxide containing boron (B) and phosphorus (P) (hereinafter referred to as BPSG) is 900 ° in an N ₂ atmosphere.
It is known that when heated at about C, it exhibits heating fluidity easily. When BPSG is immersed in hot water at 90 ° C. for 30 minutes, for example, phosphorus (P) and boron (B) are eluted from the surface of BPSG. As a result, the heating fluidity changes significantly, and heating at about 900 ° C. shows almost no fluidity. 250 nm thick BP by SIMS analysis
When the depth distribution of phosphorus (P) and boron (B) in the SG film was measured, it was found that P and B were distributed almost uniformly in the BPSG film. However, BPSG is 90 °
When immersed in warm water of C for 30 minutes, elution of B and P was recognized from the surface to a depth of about 30 nm. B before soaking in warm water
And P concentration is 1 for P after immersion in warm water.
For the digits and B, the density decreases by one digit or more. As a result,
In such a BPSG film, the heating fluidity is remarkably lowered,
When heated to about 00 ° C, heating fluidity is not recognized.

From the above findings, in order to form regions having different heating fluidity, for example, a resist pattern is formed on the etching resistant layer by a photolithography method and, in this state, it is heated in hot water at 90 ° C. for 30 minutes. When soaked, B and P are eluted from the surface of the region of the etching resistant layer which is soaked in warm water. Next, by removing the resist pattern, regions having different heat fluidity can be formed. That is, in the etching resistant layer, the region which is covered with the resist and does not come into contact with hot water has a high heating fluidity. Further, the region covered with the resist and in contact with hot water becomes a region having low heating fluidity or a region not exhibiting heating fluidity.

The area of the etching resistant layer having a high heating fluidity is in a fluidized state, and the area of the etching resistant layer having a low heating fluidity is not fluidized or only slightly fluidized. The etching layer is heated. As a result, the inclined portion can be formed only in the region having high heat fluidity, and a suitable etching mask for oblique etching can be obtained. If the etching mask thus formed is used, a trench that is inclined from a region having high heating fluidity to a region having low heating fluidity during dry etching as the etching progresses deeper in the semiconductor substrate. Can be formed.

The position, inclination direction and shape of the trench formed by the etching method of the present invention are determined according to the position where the etching resistant layer is formed, the shape of the opening, the shape of the inclined portion and the like. The formation position of the etching resistant layer and the shape of the opening can be accurately defined by the photolithography method. Further, the regions having different heating fluidity in the etching resistant layer can be easily formed as desired by resist patterning and hot water immersion treatment. Therefore, it becomes possible to easily and accurately form a trench having a desired shape inclined in a desired direction in the semiconductor substrate.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be specifically described below with reference to the drawings based on the preferred embodiments. In the drawings, the same reference numerals represent the same or equivalent components.

(Embodiment 1) FIG. 1 is a schematic sectional view of a semiconductor substrate for explaining the process of embodiment 1 relating to the first aspect of the etching method of the present invention. In Example 1, thickness 1 containing 4% each of boron and phosphorus 1
an etching resistant layer 12 of μm silicon dioxide,
For example, it is formed on the semiconductor substrate 10 by the CVD method.

Next, a resist pattern 14 corresponding to the trench opening to be formed in the semiconductor substrate 10 is formed on the etching resistant layer 12 by photolithography (see FIG. 1A).

Next, the resist pattern 14 is used as a mask to etch the etching resistant layer 12 by an RIE apparatus to form a groove-shaped opening 16 in the etching resistant layer 12. The etching conditions are, for example, CHF ₃ / O ₂ = 75.
It can be / 8 sccm, 50 mtorr, and 1000 W. As a result, a part of the semiconductor substrate is exposed. After that, the resist pattern 14 is removed by plasma ashing treatment using oxygen gas.

Next, as shown in FIG. 1B, the opening 1
A resist pattern 18 is formed on the etching-resistant layer 12A on the right side of the drawing with 6 in between. Then, the etching resistant layer is immersed in 90 ° C. hot water for 30 minutes. Then
The resist pattern 18 is removed by plasma ashing treatment using oxygen gas (see FIG. 1C). By this hot water immersion treatment, boron and phosphorus are eluted to a depth of about 30 nm from the surface of the region 12B of the etching resistant layer which is not covered with the resist pattern 18. In the figure, a region where boron and phosphorus are eluted is indicated by a broken line. In this step, two regions having different heating fluidity, that is, a region 12A having high heating fluidity and a region 12B having low heating fluidity, are formed in the etching resistant layer around the opening 16.

Next, the etching resistant layer is subjected to heat treatment at 900 ° C. for 30 minutes in a nitrogen atmosphere. Under this heat treatment condition, the region 12A having a high heating fluidity is in a fluid state, but the region 12B having a low fluidity in which boron and phosphorus are eluted shows almost no fluidity. Therefore, as a result of this heat treatment, as shown in FIG. 2A, the region 12A of the etching resistant layer on the right side of the drawing flows across the opening 16 and its surface is inclined, and the inclined portion 20 is formed. To be done. A region 12B of the etching resistant layer in which boron and phosphorus are eluted from the surface on the left side of the drawing across the opening 16.
Does not fluidize, and no slope is formed on its surface.

Using the etching resistant layer thus obtained as an etching mask, for example, JP-A-61-2623
As described in Japanese Patent Publication No. 9, the semiconductor substrate 10 is etched by reactive ion etching using an RIE device. As a result, as shown in FIG. 2B, the tilted trench 22 can be formed in the semiconductor substrate 10. After that, the etching resistant layer is removed, and the trench 22 is filled with an insulator such as silicon oxide by, for example, thermal oxidation or a CVD method. As a result, the trench 22 can effectively function as an element isolation region.

(Embodiment 2) The etching method of the present invention described in Embodiment 2 is a modification of Embodiment 1. Example 1
Similarly to the above, an etching resistant layer 12 made of silicon dioxide containing 4% each of boron and phosphorus is formed on the semiconductor substrate 10. Next, a part of the etching resistant layer 12 is selectively removed to form a groove-shaped opening, and further, boron and phosphorus are removed from the surface of the etching resistant layer by photoresist pattern formation and hot water immersion treatment. The eluted region 12B is formed (see FIG. 3A). The region 12A is a region having high heating fluidity in which boron and phosphorus are not eluted from the surface of the etching resistant layer.
In addition, in FIG. 3A, a broken line is attached to a portion corresponding to the region 12B.

After that, by performing heat treatment, as shown in FIG. 3B, the sloped portion 20 is formed on the surface of the region 12A having high heating fluidity in which boron and phosphorus were not eluted.
To form. Using these etching resistant layers as an etching mask, the semiconductor substrate 10 is etched using an RIE apparatus. As a result, it is possible to form a plurality of trenches 22 that are inclined in a desired direction as shown in FIG.

(Embodiment 3) FIG. 4 is a schematic sectional view of a semiconductor substrate for explaining the process of embodiment 3 relating to the second aspect of the etching method of the present invention. Also in Example 3, a thickness 1 containing 4% of boron and 4% of phosphorus, respectively.
an etching resistant layer 12 of μm silicon dioxide,
It is formed on the semiconductor substrate 10.

Next, as shown in FIG. 4A, a resist pattern 18 is formed on the portion 12A of the etching resistant layer. Then, the etching resistant layer is immersed in 90 ° C. hot water for 30 minutes. Next, the resist pattern 18 is removed by plasma ashing treatment using oxygen gas.
By this hot water immersion treatment, boron and phosphorus are eluted to a depth of about 30 nm from the surface of the region 12B of the etching resistant layer not covered with the resist pattern 18 (see FIG. 4B). In addition, in FIG. 4B, a region where boron and phosphorus are eluted is indicated by a broken line. By this process, two regions having different heating fluidity, that is, a region 12A having high heating fluidity and a region 12B having low heating fluidity are formed in the etching resistant layer.

Next, a resist pattern 14 corresponding to a trench opening to be formed in the semiconductor substrate 10 is formed on the etching resistant layer 12 by the photolithography method (see FIG. 4C). Next, the etching resistant layer 12 is etched using the RIE device using the resist pattern 14 as a mask, and the groove-shaped opening 1 is formed in the etching resistant layer 12.
6 is formed. The etching conditions are, for example, CHF ₃
/ O ₂ = 75/8 sccm, 50 mtorr, 1000
It can be W. The opening 16 is formed at the boundary between the regions 12A and 12B. As a result, a part of the semiconductor substrate is exposed. After that, the resist pattern 14 is removed by plasma ashing treatment using oxygen gas (see FIG. 4D).

Next, the etching resistant layer is subjected to heat treatment at 900 ° C. for 30 minutes in a nitrogen atmosphere. Under this heat treatment condition, the region 12A having a high heating fluidity is in a fluid state, but the region 12B having a low fluidity in which boron and phosphorus are eluted shows almost no fluidity. Therefore, this heat treatment causes the region 12A of the etching resistant layer on the right side of the drawing to flow and the surface thereof to be inclined, and the inclined portion 20 to be formed, as in the case shown in FIG. It is formed. A region 12B of the etching resistant layer in which boron and phosphorus are eluted from the surface on the left side of the drawing across the opening 16.
Does not fluidize and no slopes are formed on its surface.

Using the etching resistant layer thus obtained as an etching mask, the semiconductor substrate 10 is etched at the RIE element position. As a result, as shown in FIG. 2B, the tilted trench 22 can be formed in the semiconductor substrate 10.

The etching method of the present invention has been described above based on the preferred embodiments, but the present invention is not limited to these embodiments. Not only the RIE method but also the RIBE (Reactive Ion Beam Etching) method can be used to form the inclined trench in the semiconductor substrate. Further, the etching method of the present invention can be applied to the case of forming an element isolation region or the case of forming a trench type capacitor in a DRAM manufacturing process.

[0035]

According to the etching method of the present invention, it is possible to form an etching mask inclined in a desired direction. Therefore, it becomes possible to easily form a trench having a desired shape inclined in a desired direction at a desired position on the semiconductor substrate. Further, the size and position of the opening of the etching resistant layer can be fixed and accurately defined as compared with the conventional method.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor substrate for explaining each step of a first embodiment of the present invention.

FIG. 2 is a schematic partial cross-sectional view of the semiconductor substrate for explaining each step, continuing from FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of a semiconductor substrate for explaining each step of the second embodiment of the present invention.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor substrate for explaining each step of the third embodiment of the present invention.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor substrate for explaining each step of a conventional etching method for forming a trench.

6 is a plan view of a semiconductor substrate obtained by the conventional etching method for forming a trench shown in FIG.

FIG. 7 is a schematic partial cross-sectional view of a semiconductor substrate for explaining each step of a conventional etching method for forming a trench different from FIG.

[Explanation of symbols]

 10 Semiconductor Substrate 12 Etching Resistant Layer 12A Region with High Heating Fluidity 12B Region with Low Heating Fluidity 14,18 Resist 16 Opening 20 Slope 22 Trenches

Claims (4)

[Claims] 1. An etching method for forming an inclined trench in a semiconductor substrate by dry etching, comprising: (a) forming an etching resistant layer on the semiconductor substrate; and (b) forming an opening in the etching resistant layer. Forming, and exposing a part of the semiconductor substrate; (C) forming a region having different heating fluidity in the etching resistant layer around the opening; and (D) applying heat treatment to the etching resistant layer. An etching method comprising: a step of forming an inclined portion in a region having high heat fluidity; and (e) a step of dry etching a part of the exposed semiconductor substrate. 2. An etching method for forming an inclined trench in a semiconductor substrate by dry etching, comprising: (a) a step of forming an etching resistant layer on the semiconductor substrate; and (b) different heat flow for the etching resistant layer. And (c) a step of forming an opening in the etching resistant layer at the boundary between the areas having different heat flow properties to expose a part of the semiconductor substrate, and (d) the etching resistant layer. And a step of forming an inclined portion in a region having a high heating fluidity, and (e) a step of dry-etching a part of the exposed semiconductor substrate. 3. The method according to claim 1, wherein the step of forming the regions having different heating fluidity comprises immersing one of the regions having different heating fluidity in hot water at 50 ° C. or higher. The etching method described. 4. The etching resistant layer is made of silicon dioxide containing one or more elements selected from the group consisting of phosphorus (P), boron (B) and arsenic (As). The etching method according to claim 1, claim 2 or claim 3.