JPH05190441A - Formation method of resist pattern - Google Patents
Formation method of resist patternInfo
- Publication number
- JPH05190441A JPH05190441A JP200592A JP200592A JPH05190441A JP H05190441 A JPH05190441 A JP H05190441A JP 200592 A JP200592 A JP 200592A JP 200592 A JP200592 A JP 200592A JP H05190441 A JPH05190441 A JP H05190441A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- silylating
- layer
- resist pattern
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、レジストシリル化プロ
セスを用いたレジストパターンの形成方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a resist pattern using a resist silylation process.
【0002】[0002]
【従来の技術】図2に従来のレジストシリル化プロセス
を用いたレジストパターン形成工程を示す。まず、被加
工膜又は基板1上にスピンコート法により膜厚1500
0〜30000Åでシリル化用レジスト2を塗布し(図
2(a))、所定の形状のクロム(Cr)マスクを用い
て露光を行う(図2(b))。2. Description of the Related Art FIG. 2 shows a resist pattern forming process using a conventional resist silylation process. First, a film thickness of 1500 is formed on the film to be processed or the substrate 1 by spin coating.
The silylation resist 2 is applied at 0 to 30000Å (FIG. 2A), and exposure is performed using a chromium (Cr) mask having a predetermined shape (FIG. 2B).
【0003】次に、ヘキサメチルジシラザン((C
H3)3Si−NH−Si(CH3)3)雰囲気で150〜
200℃、3〜4分間加熱し、上記露光領域をシリル化
し、レジストシリル化層4を形成する(図2(c))。
その後、エッチングガスとしてO2を用いドライエッチ
ングを行い、レジストパターンを形成する(図2(d)
(e))。Next, hexamethyldisilazane ((C
H 3) 3 Si-NH- Si (CH 3) 3) 150~ atmosphere
The exposed area is silylated by heating at 200 ° C. for 3 to 4 minutes to form a resist silylated layer 4 (FIG. 2C).
After that, dry etching is performed using O 2 as an etching gas to form a resist pattern (FIG. 2D).
(E)).
【0004】上記に示した様に、レジストシリル化層4
を酸素プラズマに対する耐性向上の処理せずレジストエ
ッチングを施す場合、レジストシリル化層4の酸化速度
よりエッチング速度の方が速いため、レジストエッチン
グのマスクであるレジストシリル化層4のレジストエッ
チング中の後退が大きくなる。マスクの後退について、
発明者の実験では、深さ方向に対して7%もの後退が認
められた。上記後退が多く起こる場合には、現在、例え
ば、露光量を大きくすること等により、レジストシリル
化層4を所定のマスクサイズより太めに作ることにより
後退による影響を抑制している。As indicated above, the resist silylated layer 4
When resist etching is performed without improving the resistance to oxygen plasma, since the etching rate is higher than the oxidation rate of the resist silylated layer 4, the resist silylated layer 4 that is a mask for resist etching recedes during resist etching. Becomes bigger. Regarding the retreat of the mask,
In the inventors' experiment, a recession of as much as 7% was observed in the depth direction. If a large amount of recession occurs, the influence of the recession is currently suppressed by making the resist silylated layer 4 thicker than a predetermined mask size, for example, by increasing the exposure amount.
【0005】[0005]
【発明が解決しようとする課題】図2に示す工程を用い
た場合、レジストエッチング時にレジストシリル化層4
が横方向にエッチングされ、寸法変換差の大きなレジス
トパターンが形成される。 また、上記の様にレジスト
シリル化層4を事前に太めに作る場合、パターン寸法が
小さくなるとスペース部が小さくなるため、露光装置の
解像力限界以下になることがある。また、レジストシリ
ル化層4は横方向のみならず、縦方向にも深くなるた
め、エッチング後のレジスト剥離が行いにくくなる。When the process shown in FIG. 2 is used, the resist silylated layer 4 is formed during resist etching.
Are laterally etched to form a resist pattern having a large difference in size conversion. Further, when the resist silylated layer 4 is made thicker in advance as described above, the space portion becomes smaller as the pattern size becomes smaller, so that it may be less than the resolution limit of the exposure apparatus. Further, the resist silylated layer 4 becomes deep not only in the horizontal direction but also in the vertical direction, so that it becomes difficult to remove the resist after etching.
【0006】本発明は、レジストシリル化層表面に酸化
膜を形成することにより、レジストシリル化層のエッチ
ング中の後退を防止する手段を提供することを目的とす
る。An object of the present invention is to provide a means for preventing the resist silylated layer from receding during etching by forming an oxide film on the surface of the resist silylated layer.
【0007】[0007]
【課題を解決するための手段】本発明のレジストパター
ン形成方法は、レジストシリル化プロセスを用いたレジ
ストパターン形成方法において、被加工膜又は基板上に
シリル化用レジストを塗布し、所定のパターンで露光し
た後に露光領域をシリル化する工程と、上記工程により
形成されたレジストシリル化層をマスクとして、所定の
量のエッチングを行った後、前記レジストシリル化層表
面を酸化する工程と、上記工程後、前記未反応シリル化
用レジストをドライエッチングにより除去し、レジスト
パターンを形成する工程とを有することを特徴とするも
のである。A resist pattern forming method of the present invention is a resist pattern forming method using a resist silylation process, in which a silylating resist is applied onto a film to be processed or a substrate to form a predetermined pattern. A step of silylating the exposed area after exposure, a step of oxidizing the resist silylation layer surface after performing a predetermined amount of etching using the resist silylation layer formed in the above step as a mask, and the above step Then, the unreacted silylation resist is removed by dry etching to form a resist pattern.
【0008】[0008]
【作用】上記工程を用いることにより、レジストシリル
化層のエッチング中での後退を抑制し、寸法変換差の小
さなレジストパターンが形成できる。By using the above steps, it is possible to suppress the receding of the resist silylated layer during etching, and to form a resist pattern with a small dimensional conversion difference.
【0009】[0009]
【実施例】以下に、一実施例に基づいて、本発明を詳細
に説明する。EXAMPLES The present invention will be described in detail below based on examples.
【0010】図1は本発明の一実施例のレジストパター
ン形成工程図である。FIG. 1 is a process diagram of forming a resist pattern according to an embodiment of the present invention.
【0011】まず、被加工膜又は基板1上にスピンコー
ト法により膜厚15000〜30000Å程度でシリル
化用レジスト2を塗布し(図1(a))、所定の形状の
クロム(Cr)マスクを用いて露光を行う(図1
(b))。First, a silylation resist 2 having a film thickness of about 15,000 to 30,000 Å is applied onto a film to be processed or a substrate 1 by a spin coating method (FIG. 1A), and a chromium (Cr) mask having a predetermined shape is applied. Exposure is carried out (Fig. 1
(B)).
【0012】次に、ヘキサメチルジシラザン雰囲気で1
50〜200℃、3〜4分間加熱し、上記露光領域をシ
リル化し、レジストシリル化層4を形成する(図1
(c))。Next, 1 in a hexamethyldisilazane atmosphere
The exposed area is silylated by heating at 50 to 200 ° C. for 3 to 4 minutes to form a resist silylated layer 4 (FIG. 1).
(C)).
【0013】次に未反応のシリル化用レジスト2をO2
をエッチングガスとして用い、ドライエッチングによ
り、膜厚の25〜50%程度除去した(図1(d))
後、以下の条件で、レジストシリル化層4の表面を酸化
する。例えば、バレル型アッシング装置を用い、温度2
00℃程度、流量300sccm,圧力400mTor
rでO2ガスを流し、10分程度酸化することにより、
レジストシリル化層4表面にシリコン有機物を含む酸化
膜5が形成される(図1(e))。Next, the unreacted silylating resist 2 is changed to O 2
25% to 50% of the film thickness was removed by dry etching using Al as an etching gas (FIG. 1D).
After that, the surface of the resist silylated layer 4 is oxidized under the following conditions. For example, a barrel type ashing device is used, and temperature 2
About 00 ° C, flow rate 300sccm, pressure 400mTorr
By flowing O 2 gas at r and oxidizing for about 10 minutes,
An oxide film 5 containing a silicon organic substance is formed on the surface of the resist silylated layer 4 (FIG. 1E).
【0014】次に、未反応のシリル化用レジスト2をO
2ガスをエッチングガスとして用い、ドライエッチング
を行い、レジストパターンを形成する(図1(f))。
その後、酸化膜5は除去せず、被加工膜又は基板1のエ
ッチングを行う。Next, the unreacted silylation resist 2 is replaced with O.
Dry etching is performed using 2 gases as an etching gas to form a resist pattern (FIG. 1F).
After that, the film to be processed or the substrate 1 is etched without removing the oxide film 5.
【0015】[0015]
【発明の効果】以上詳細に説明した様に、本発明を用い
ることにより、レジストシリル化層の酸素プラズマ耐性
が向上し、従来より所望の寸法との差の小さなレジスト
パターンが得られる。As described in detail above, by using the present invention, the oxygen plasma resistance of the resist silylated layer is improved, and a resist pattern having a smaller difference from a desired dimension than in the past can be obtained.
【図1】本発明の一実施例のレジストパターン形成工程
図である。FIG. 1 is a process drawing of a resist pattern forming process according to an embodiment of the present invention.
【図2】従来のレジストパターン形成工程図である。FIG. 2 is a process diagram of a conventional resist pattern forming process.
1 被加工膜又は基板 2 シリル化用レジスト 3 クロムマスク 4 レジストシリル化層 5 酸化膜 1 Processed Film or Substrate 2 Silylation Resist 3 Chromium Mask 4 Resist Silylation Layer 5 Oxide Film
Claims (1)
ストパターン形成方法において、 被加工膜又は基板上にシリル化用レジストを塗布し、所
定のパターンで露光した後に露光領域をシリル化する工
程と、 上記工程により形成されたレジストシリル化層をマスク
として、所定の量のエッチングを行った後、前記レジス
トシリル化層表面を酸化する工程と、 上記工程後、前記未反応シリル化用レジストをドライエ
ッチングにより除去し、レジストパターンを形成する工
程とを有することを特徴とするレジストパターン形成方
法。1. A method of forming a resist pattern using a resist silylation process, which comprises applying a silylation resist on a film to be processed or a substrate, exposing the exposed film with a predetermined pattern, and then silylating the exposed region, A step of oxidizing the surface of the resist silylation layer after performing a predetermined amount of etching using the resist silylation layer formed in the step as a mask, and after the step, dry etching the unreacted silylation resist. A step of removing and forming a resist pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP200592A JP2902513B2 (en) | 1992-01-09 | 1992-01-09 | Method of forming resist pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP200592A JP2902513B2 (en) | 1992-01-09 | 1992-01-09 | Method of forming resist pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05190441A true JPH05190441A (en) | 1993-07-30 |
JP2902513B2 JP2902513B2 (en) | 1999-06-07 |
Family
ID=11517284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP200592A Expired - Fee Related JP2902513B2 (en) | 1992-01-09 | 1992-01-09 | Method of forming resist pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2902513B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100281113B1 (en) * | 1997-12-29 | 2001-04-02 | 김영환 | Patterning method of semiconductor device |
KR100379651B1 (en) * | 1996-11-27 | 2003-07-22 | 동경 엘렉트론 주식회사 | Method for manufacturing semiconductor device |
JP2003529930A (en) * | 2000-03-30 | 2003-10-07 | 東京エレクトロン株式会社 | Dry silylation plasma etching method |
US8877634B2 (en) | 2012-04-05 | 2014-11-04 | Samsung Electronics Co., Ltd. | Methods of forming a fine pattern on a substrate and methods of forming a semiconductor device having a fine pattern |
-
1992
- 1992-01-09 JP JP200592A patent/JP2902513B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100379651B1 (en) * | 1996-11-27 | 2003-07-22 | 동경 엘렉트론 주식회사 | Method for manufacturing semiconductor device |
KR100281113B1 (en) * | 1997-12-29 | 2001-04-02 | 김영환 | Patterning method of semiconductor device |
JP2003529930A (en) * | 2000-03-30 | 2003-10-07 | 東京エレクトロン株式会社 | Dry silylation plasma etching method |
US8877634B2 (en) | 2012-04-05 | 2014-11-04 | Samsung Electronics Co., Ltd. | Methods of forming a fine pattern on a substrate and methods of forming a semiconductor device having a fine pattern |
Also Published As
Publication number | Publication date |
---|---|
JP2902513B2 (en) | 1999-06-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11921427B2 (en) | Methods for making hard masks useful in next-generation lithography | |
CN1881078B (en) | Method for forming an anti-etching shielding layer | |
JPH10125659A (en) | Etching method of organic antireflection layer (arc) | |
TW201841221A (en) | Method for reducing lithography defects and pattern transfer | |
JPH07273023A (en) | Method of application of photoresist | |
JPH05190441A (en) | Formation method of resist pattern | |
JPH0466345B2 (en) | ||
JPH0883786A (en) | Manufacture of semiconductor device | |
JP3392231B2 (en) | Pattern formation method | |
JPS6227384B2 (en) | ||
JP4780264B2 (en) | Method for forming chromium-based photomask | |
JP4675450B2 (en) | Method for forming a thin film pattern | |
JPH07321091A (en) | Etching and wiring forming method | |
JPH04176123A (en) | Manufacture of semiconductor device | |
JP3660280B2 (en) | Method for forming fine resist pattern | |
JPH07106310A (en) | Dry etching method | |
US20050130421A1 (en) | Method for removing a resist mask with high selectivity to a carbon hard mask used for semiconductor structuring | |
JP2937537B2 (en) | Pattern formation method | |
JP3535364B2 (en) | Method for manufacturing semiconductor device | |
JP3354901B2 (en) | Method of forming fine pattern, semiconductor device and method of manufacturing semiconductor device | |
JP2005109035A (en) | Manufacturing method for semiconductor device | |
JPH0394425A (en) | Removal of resist | |
JPS6386434A (en) | Formation of resist pattern | |
JP3563138B2 (en) | Pattern forming method using photosensitive resin composition | |
JPS58110044A (en) | Pattern formation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |