JPH05189962A - Dram controller - Google Patents

Abstract

PURPOSE:To improve the responsiveness of a read/write access request by enabling the read/write access request issued in a refresh cycle to be executed without awaiting the completion of refresh. CONSTITUTION:The count value of a counter 2 is outputted as a memory address MA via a buffer A3 in the refresh cycle, and the refresh is applied to a corresponding row address. When a select signal, the inverse of CS is activated during the refresh cycle and the access request is issued, a comparator 7 compares a row address RA from the outside with the value of the counter 7, and sets a comparator output signal, the inverse of MAT, at a low level when coincidence is obtained. A control circuit 1a detecting the low level of the signal, the inverse of MAT switches a mode from a refresh mode to an access mode by activating a signal, the inverse of CAS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM controller for controlling a DRAM (dynamic random access memory) which requires a refresh operation within a fixed period.
In particular, the present invention relates to a DRAM controller having means for coping with a case where a refresh operation and an access request overlap.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional DRAM controller. In the figure, 1c is a select signal CS * that becomes active during external access (* replaces the upper line. Signals with * become active at low level), high level when external access request is read,
The read / write control signal R / W * and the interval timer output signal φ _I which become low level at the time of writing are input, and the row address strobe signal RA is input to the DRAM.
Ready signal RDY that outputs S *, column address strobe signal CAS *, write enable signal WE *, and is activated when preparation for an external access request is completed.
The control circuit outputs * and outputs output enable signals OE * 1 to OE * 3 to various buffers.

Further, 2 is the timing of the rise of the output enable signal OE * 1 output from the control circuit 1c,
A counter having the same number of bits as the number of bits of the row address of the DRAM in which the count value is incremented by 1, and 3 outputs the count value of the counter 2 to the address bus as the memory address MA when the output enable signal OE * 1 is activated. The buffers A and 4 output the row address signal RA to the address bus when the output enable signal OE * 2 is activated, and the buffers 5 and 5 are the column address signal CA when the output enable signal OE * 3 is activated. To the address bus are buffers C and 6 which are timing circuits for generating the timing of the refresh operation for generating the output signal φ _I which becomes the low level at a constant time interval.

Next, the operation of this conventional example when an external access is requested will be described. If the address for accessing RA and CA from the outside is read as R / W *, a high level is input, and if it is a write, a low level is input. When CS * becomes active, the DRAM controller starts the access operation. The control circuit 1c checks the conflict with the refresh operation (called arbitration), and if there is no conflict, activates OE * 2 for the buffer B4, outputs RA as MA through the buffer B4, and then activates RAS *. To do.

After a certain time, OE * for the buffer B4
2 is inactive, OE * 3 for buffer C5 is active, CA is output as MA, and then CAS
* Is activated. The control circuit 1c also activates WE * for a write cycle and deactivates WE * for a read cycle according to the input R / W * signal. After a certain period of time, when the access is completed, RDY * is activated to notify the outside that the access is completed.

Next, the refresh operation will be described with reference to the timing chart of FIG. The interval timer 6 outputs to the control circuit 1c an interval timer output signal φ _I which goes low at a predetermined time interval (t _RC ). When the control circuit detects a low level of φ _I , it performs arbitration with external access and starts a refresh operation. In the refresh operation, OE * 1 becomes active for the buffer A3, and the count value of the counter 2 is output as MA. Next, RAS * is activated and refreshment is performed for a predetermined time (t
After _RAS ), RAS * is returned to inactive.

Next, OE * 1 for the buffer A3 is made inactive, and the counter 2 is incremented at the rising edge of this signal. This count value becomes a row address to be refreshed next, that is, a refresh address, and thereafter, the entire DRAM is refreshed by sequentially scanning the row address. Such a refresh method is called RAS only refresh. From the perspective of the DRAM, the difference between the RAS only refresh operation and the read / write access operation is that the latter outputs the column address to the address bus and activates CAS *.

The operation when there is an external access request during the refresh period will be described with reference to FIG. The procedure until the interval timer output signal φ _I becomes low level and the refresh operation is started is the same as in the case of FIG.

When CS * becomes active and an external access request arrives during the refresh operation, the access operation is started after a fixed time elapses after the refresh operation is completed. That is, after the refresh operation is completed, OE * 2 is set to low level, RA is output as MA through the buffer B, and RAS * becomes active after a certain time (t _RP ) has passed since RAS * became inactive. To do. After that, CA is output as MA through buffer C, and CA is output.
Access is completed by making S * active. Fixed time: t _RP is called RAS precharge time,
After returning RAS * to inactive, R during this period
Activating AS * is prohibited.

[0010]

DISCLOSURE OF THE INVENTION The conventional DRA described above
In the M controller, if there is an access request during the refresh period, the access side is unconditionally suspended, and access is not started until the refresh operation period (t _RAS + t _RP ) ends, resulting in poor responsiveness. there were.

In particular, when the row address to be refreshed and the row address on the access side match, refreshment is executed twice consecutively for the same address, resulting in unnecessary refresh operation. It was being appreciated.

[0012]

The DRAM controller of the present invention includes a comparator for generating an output signal that becomes active when the row address signal from the outside and the value of the counter for determining the refresh address match, the refresh address and the row address. In the case of an access request in which the addresses match, a control circuit having a function of outputting the column address as a memory address and activating CAS * to switch the operation of the DRAM to a normal read / write operation is provided.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, the same parts as those of the conventional example of FIG. 4 are designated by the same reference numerals, and a duplicate description will be omitted.

In this embodiment, a comparator 7 is added which compares the row address RA with the count value of the counter 2 and outputs an output signal MAT * which becomes active when the two coincide with each other. In addition to the function similar to that of the conventional example, a request for external access is issued during the refresh operation, and the comparator output signal MAT *
The function to activate OE * 3 and CAS * when is activated is added.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. Up to the point where the refresh operation is activated, it is the same as in the conventional example.
The value of the counter 2, that is, the refresh address is output as, and RAS * is activated to start RAS only refresh. If an access request is input from the outside and CS * becomes active within that period, the row address to be accessed and the refresh address are compared by the comparator 7, and if they match, the comparator output signal MAT
* Becomes active.

When MAT * becomes active, the control circuit 1
a switches the operation mode from the refresh operation to the read / write access. That is, OE * for buffer A3
After making 1 inactive, O for buffer C5
Column address C as MA with E * 3 activated
A is output, and then CAS * is activated. At this time, a high level or a low level is output as WE * according to the R / W * signal. When the access is completed, RDY * is activated to notify the outside that the access is completed.

When the row address of the read / write access request coming during the refresh operation does not match the refresh address, the comparator output signal MAT * remains inactive, and the same operation as in the case of the conventional example shown in FIG. 6 is performed. To do.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In this embodiment, a DR for 2-port access
The present invention is applied to an AM controller, and a buffer for port 0, a comparator, and a signal have a subscript 0.
However, the subscript 1 is added to the buffer, the comparator and the signal for the port 1. Further, the control circuit 1b has two
Has been modified for the port.

The operation of the DRAM controller in this embodiment is similar to that of the first embodiment, and the row address and refresh address of the access request from each port are respectively transferred by the comparators 7 ₀ and 7 ₁ . In comparison, if they match, the refresh operation is changed to normal read / write access to operate.

In this embodiment, the 2-port DRAM controller is explained, but even in the case of 3-port or more, a multiport DRAM controller can be constructed by installing a comparator at each access port.

[0021]

As described above, the DRAM of the present invention
When an external access request is issued during the refresh operation, the controller compares the row address of the access request with the refresh address, and when both match, switches the operation mode of the DRAM from the refresh mode to the access mode. According to the present invention, the requested access can be executed faster, and unnecessary refresh operation can be omitted.

Specifically, when the operation mode is switched, at least the RAS precharge time (t _RP )
Is unnecessary, and for example, in a DRAM having an access time of 100 ns, t _RP is about 80 ns, and the access time can be shortened by about one access time.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a timing chart for explaining a refresh operation of a conventional example.

FIG. 6 is a timing chart when an access request occurs during a refresh operation in the conventional example.

[Description of Reference Signs] 1a, 1b, 1c Control circuit 2 Counter 3 Buffer A 4, 4 ₀ , 4 ₁ Buffer B 5, 5 ₀ , 5 ₁ Buffer C 6 Interval timer 7, 7 ₀ , 7 ₁ Comparator RA, RA ₀ , RA ₁ row address signal CA, CA ₀ , CA ₁ column address signal CS *, CS * ₀ , CS * ₁ select signal R / W *, R / W * ₀ , R / W * ₁ read / write control signal RDY * , RDY * ₀ , RDY * ₁ Ready signal MA Memory address signal RAS * Row address strobe signal CAS * Column address strobe signal WE * Write enable signal OE * 1, OE * 2, OE * 2 ₀ , OE * 2 ₁ , OE *
3, OE * 3 ₀ , OE * 3 ₁ output enable signal φ _I Interval timer output signal MAT *, MAT * ₀ , MAT * ₁ Comparator output signal

Claims (1)

[Claims] 1. A first three-state buffer for outputting a row address signal to a DRAM address bus, a second three-state buffer for outputting a column address signal to a DRAM address bus, and a counter for designating a refresh address of DRAM. A third 3-state buffer for outputting the count value of the counter to the address bus of the DRAM, a comparator for comparing a row address signal with the count value of the counter, and an interval timer for generating a timing for activating a refresh operation. A control circuit which receives an access request from the outside and an output signal of the interval timer and outputs various control signals for controlling the operation of the DRAM and output enable signals for the first, second and third three-state buffers. And, the control The DRAM has a function of switching the operation mode of the DRAM from the refresh mode to the read / write mode when an access request is externally issued during the refresh period and a coincidence signal is received from the comparator. controller.