JPH04349295A - Semiconductor storing element - Google Patents

Abstract

PURPOSE:To unnecessitate a refresh control generator or a demand mediation circuit, etc., in an external part and to eliminate the time prolongation of memory access by refreshing. CONSTITUTION:This element is provided with a bit line 102 for exclusive refreshing, a word line 103 and a sense amplifier 13, and the row address for refreshing of a memory cell 18 is decoded by a row address decoder 10 for refreshing. A refreshing interval and the row address for refreshing are generated with a refresh control part 7 by receiving a clock signal from the external part. By a memory access mediating part 8, when a memory access demand and a refresh demand are overlapped to the same row address of the memory cell 18, these both access are mediated and contention-controlled so that access to the same address of the memory cell 18 are unoverlapped. By a multiplexer 17 and a demultiplexer 16, the input/output data with the external part controlled in the memory access mediating part 8 is switched.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory element used as a memory element in an information processing apparatus, and more particularly to a dynamic random access memory (DRAM).

0002

[Prior Art] Conventionally, this type of DRAM has either achieved refresh control in an external circuit or achieved refresh by generating a refresh address within the chip simply by inputting a refresh signal to a refresh-dedicated terminal. (self-refresh, automatic refresh), etc., but in all DRAMs, control is performed to arbitrate conflicts between memory access requests and refresh requests and permit only one of the requests.

0003

[Problems to be Solved by the Invention] In this conventional DRAM, normally, when a memory access request and a refresh request conflict, arbitration is performed, and the request with a higher priority is granted, while the other request is masked and made to wait. This has the disadvantage that only one of the requests can be accepted, and the memory cycle of the one that is forced to wait is extended. Furthermore, since a request arbitration circuit, a refresh generation circuit, etc. are required externally, there is a drawback that the circuit scale becomes large.

0004

[Means for Solving the Problems] A semiconductor memory element of the present invention has a bit line, a word line, and a sense amplifier.
word lines and sense amplifiers, a refresh row address decoder that decodes refresh row addresses of memory cells, a refresh control unit that receives an external clock signal and generates refresh intervals and the refresh row address, and an external Memory access for controlling conflicts so that when a memory access request and a refresh request conflict with the same row address of the memory cell, these memory accesses and refresh accesses are arbitrated so that accesses to the same address of the memory cell do not overlap. It includes an arbitration section, and a multiplexer and a demultiplexer that switch input/output data to and from the outside controlled by the memory access arbitration section.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a DRAM chip showing an embodiment of the present invention, and FIG. 2 is a partial circuit diagram showing an example of the memory array of FIG.

In FIG. 1, input port 1 receives a row address strobe signal (hereinafter referred to as RAS), a column address strobe signal (CAS), and an output enable signal (
This is a port for inputting memory access control signals such as a write enable signal (hereinafter referred to as WE) and a write enable signal (hereinafter referred to as WE). Address input port 2 is a port for inputting row addresses and column addresses necessary for memory access. The refresh control input port 3 is a clock signal (hereinafter referred to as CLK) input port for generating refresh requests at regular intervals and generating refresh addresses. Data input/output port 4 is for memory data (hereinafter referred to as DA).
This is a port for inputting and outputting T). A memory access control unit (hereinafter referred to as MAC) 5 is a control unit that controls memory access timing using RAS, CAS, OE, and WE input from the input port 1. An address buffer (hereinafter referred to as ADB) 6 is a buffer that receives an address input from the address input port 2. Refresh control unit (
Reference numeral 7 (hereinafter referred to as RFC) is a control unit that determines the refresh interval based on the CLK input from the refresh control clock input port 3, and generates a refresh request signal (corresponding to RAS in this case) and a refresh row address. A memory access arbitration unit (hereinafter referred to as ARB) 8 is an arbitration unit that arbitrates so that the same address on a memory cell is not accessed when a memory access and an internal refresh request overlap at the same row address. A memory access row address decoder (hereinafter referred to as MAD) 9 is a row address decoder that decodes a row address input from the address input port 2. A refresh row address decoder (hereinafter referred to as RFD) 10 is a decoder that decodes a refresh row address generated by RFC7. Column address decoder for memory access (
Reference numeral 11 (hereinafter referred to as MCD) is a decoder that decodes a column address input from the address input port 2. A memory access sense amplifier (hereinafter referred to as MSA) 12 holds data for one row address during memory access. Refresh sense amplifier (hereinafter referred to as R)
SA) 13 holds memory data for one row address for refresh. An output data buffer (hereinafter referred to as DOB) 14 is a buffer for data output. An input data buffer (hereinafter referred to as DIB) 15 is a buffer for data input. The output data control multiplexer (hereinafter referred to as MPX) 16 and the input data control demultiplexer (hereinafter referred to as DMX) 17 are controlled by the ARB8, and input/output data during memory access is MS
The data line is switched after deciding whether to correspond to A12 or RSA13. A memory cell array (hereinafter referred to as MEM) 18 is a memory cell section that stores external input/output data.

[0007] RFC7 transmits the refresh request signal a to M
AC5 outputs a memory access request signal b to ARB8. MAC5 outputs CASc to MCD11 to make the column address valid, and sets WEd to DIB15 and DMX16.
Output it to write enable and set OEe to DOB14,
Output to MPX17 and enable output. ARB8 outputs RASf to MAD9 to validate the row address for memory access, and outputs refresh RASg to RFD10 to validate the row address for refresh. Further, the ARB 8 controls the DMX 16 and MPX 17 using an input data control signal h and an output data control signal i. ADB6 transfers a memory address via memory address bus 27, RFC7 transfers a refresh address via refresh address bus k, and DMX1
6 transfers memory data via memory data buses m and n.

FIG. 2 shows an equivalent circuit for the minimum storage unit of 1 bit of the MEM 18 in FIG. 1, and the refresh word line 103 and memory access word line 104 are RF
This is a signal line for selecting data for one row address decoded by D10 and MCD11. Transistors (hereinafter referred to as Qr and Qm) are connected to each word line 103, respectively.
, 104 is a switching transistor that turns on when selected.

Next, the operation of this embodiment will be explained. First, regarding the memory refresh operation, the RFC 7 continues counting with a timer based on the CLK from the refresh control clock input port 3, and transmits the refresh request signal a generated at certain regular intervals to the ARB 8. ARB8 checks the presence or absence of memory access request signal b when refresh request signal a is input, and even if there is a memory access request, it compares both row addresses for refresh and memory access, and refreshes unless the request is to the same address. Receive request signal a and refresh RASg
is output to RFD10. RFD 10 decodes the address and selects the corresponding word line. For example, if the refresh word line 103 is selected, the ME
Inside M18, Qr is turned on and the data information stored in C is transferred to RSA via refresh bit line 102.
13. This latched data is charged to the same address again at the trailing edge of the refresh RAS 24. With the above operations, refresh for one row address is completed. The entire MEM 18 is refreshed by repeating the above-described operation at regular intervals.

Next, regarding the memory access operation, when RAS is input from input port 1, MAC 5 accesses ARB.
A memory access request signal b is output to 8. When ARB8 receives memory access request signal b, it checks the presence or absence of refresh request signal a, and even if there is a refresh request, unless the request is for the same row address, it accepts memory access request signal b and outputs RASf to MAD9. . This RASf makes the row address input from the address input port 2 valid, the MAD 9 decodes the address, and selects the corresponding word line for memory access. For example, when the word line 104 for memory access is selected, Qm is turned on inside the MEM 18, and the data information stored in C is passed through the bit line 101 for memory access to the sense amplifier MS.
Data for one row address is latched into A12. After that, the MAC is configured using the CAS input from input port 1.
5 generates CASc. As a result, the column address input from address input port 2 becomes valid, and the MC
The column address is decoded in D11, and the state value of MSA12 corresponding to the selected bit line is
In the case of memory read access, the data is sent to the MPX 17 via the memory data bus n. Here, the data on the memory data bus n side is sent to the DOB 14 under the control of the output data control signal i. and DOB1 by OEe
4 is controlled and DAT is output to data input/output port 4. On the other hand, in the case of memory write access, DAT input from the data input/output port 4 is received by the DIB 15, controlled by WEd, and sent to the DMX 16. The DMX 16 is controlled by the input data control signal h, and rewrites the contents of the MSA 12 corresponding to the bit line selected by the column address via the memory data bus n. In both accesses, the contents of the sense amplifier are charged onto the MEM 18 at the trailing edge of RAS, and the memory access cycle is completed.

The above is a memory access operation in the case where there is no conflict with refresh for the same row address; when a conflict occurs, the operation is as follows. ARB
8 grants access rights to memory access requests and refresh requests on a first-come, first-served basis. Therefore, when both requests conflict, the following three patterns are possible. First, the first pattern is a case where a memory access request is granted access rights first, and a refresh request to the same row address occurs during that access cycle. The second pattern is a case where a refresh request is granted access rights first, and a memory access request to the same row address occurs during the refresh. Furthermore, the third pattern is a case where a refresh request and a memory access request occur simultaneously to the same row address.

First, in the first pattern, by masking and eliminating refresh requests that occur later, the conflicting row address portion is naturally refreshed by memory access, and since the refresh request is masked, the same row Access to the address can be avoided.

Next, in the second pattern, memory access requests that occur later are masked so that RASf is not output, and CA output from the MAC 5 is
Sc is input as is, and the memory is set so that MPX17 is selected in the case of a memory read sequence and DMX16 is selected in the case of a memory write sequence, respectively, by the data output control signal i and data input control signal h output from ARB8. By controlling data bus m, RSA1
The data on the bit line corresponding to the column address made valid by CASc latched at 3 is read/written for memory access. By doing so, it is possible to arbitrate conflicts between refresh and memory access to the same row address without masking memory access.

Next, in the third pattern, by masking refresh requests and giving priority to memory access,
Memory access and refresh can be performed simultaneously in the same cycle as in the first pattern.

In this embodiment, contention arbitration in these three patterns is possible, so both refresh and memory access can be performed without time delay.

[0016]

[Effects of the Invention] As explained above, the present invention has a dedicated refresh function inside the memory chip, thereby eliminating the need for an external refresh control generation circuit, request arbitration circuit, etc., as in the prior art. This has the effect of eliminating the need to extend memory access time due to refresh.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DRAM chip showing one embodiment of the present invention.

FIG. 2 is a partial circuit diagram showing an example of the inside of the memory cell array in FIG. 1;

[Explanation of symbols]

1 Input port 2 Address input port 3 Refresh control clock input port 4
Data input/output port 5 Memory access control unit (MAC) 6
Address buffer (ADB) 7 Refresh control section (RFC) 8 Memory access arbitration section (AR
B) 9 Row address decoder for memory access (MAD) 10 Row address decoder for refresh 11
Column address decoder for memory access (M
CD) 12 Memory access sense amplifier (MSA)
13 Refresh sense amplifier (RSA) 1
4 Data output buffer (DOB) 15
Data input buffer (DIB) 16 Input data control demultiplexer (DMX) 17 Output data control multiplexer (MPX) Qm
Memory access switching transistor Qr
Refresh switching transistor C
capacitor

Claims (1)

[Claims] 1. In a semiconductor memory element having a bit line, a word line, and a sense amplifier, a bit line, a word line, and a sense amplifier dedicated for refresh, and a refresh row address decoder that decodes a refresh row address of a memory cell; a refresh control unit that receives a clock signal from the outside and generates a refresh interval and the refresh row address; and a refresh control unit that receives a clock signal from the outside and generates a refresh interval and the refresh row address; a memory access arbitration unit that arbitrates between refresh accesses and controls contention so that accesses to the same address of the memory cell do not overlap, and a multiplexer that switches input/output data between external data controlled by the memory access arbitration unit. and a demultiplexer.