JPH05183384A - Perfect reconfiguration filter - Google Patents

Abstract

PURPOSE:To provide a perfect reconfiguration filter in which a synthesized signal can become the same signal as an input signal by applying a simple arithmetic operation to a filter group of small scale and in which no orthogonal intersection occurs in the filter group in which the input signal is divided into bands, and used in the case where the signals in divided bands are synthesized after being transmitted or encoded. CONSTITUTION:At a transmission side, band limitation is applied to the input signal by a first LPF 11, and the band limitation is applied to the output of the first LPF 11 by a second LPF 13, and the output of the first LPF 11 and that of a subtractor 16 which subtracts the output of the second LPF 13 from the input signal are transmitted. respectively. At a reception side, the band limitation is applied to the transmitted output of the first LPF 11 by a third LPF 19 with the same configuration as that of the second LPF 13. and it is added on the transmitted output of the subtractor 16 by an adder 20, and arithemtic processing is applied to the output of the first LPF 11 and that of the adder 20 alternately, and the output of the adder 20 and that of the arithmetic processing are outputted alternately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a perfect reconstruction filter used for band-dividing a signal for coding or transmission.

[0002]

2. Description of the Related Art Generally, when a frequency band of a signal is divided and encoded or transmitted, it is desirable that the signal synthesized after decoding and receiving is the same as the original signal. As a conventional perfect reconstruction filter, for example, there is one using a quadrature mirror filter (QMF). FIG. 8 is a block diagram showing the configuration of this conventional perfect reconstruction filter. The operation will be described below with reference to FIG.

Reference numeral 1 is an input terminal, 2 is a first low-pass filter (hereinafter, LPF), 3 is a first high-pass filter (hereinafter, HPF), and 4 and 5 are thinning circuits. , 6 and 7 are transmission lines, 8 and 9 are interpolation circuits, 10
Is a second LPF, 11 is a second HPF, 12 is an adder,
Reference numeral 13 is an output terminal. First, the signal input from the input terminal 1 is divided into two bands by the first LPF 2 and the first HPF 3. Each of the divided signals is thinned out by a thinning circuit 4,
5, the interpolation components 8 and 9 interpolate through the transmission lines 6 and 7, and then the aliasing components are removed by the second LPF 10 and the second HPF 11, respectively. The outputs of the second LPF 10 and the second HPF 11 are added by the adder 12 and output from the output terminal 13. Here, in order to completely reconstruct the output of the adder 12 into the original signal, the transfer function of the first LPF is H ₁ (z) and the transfer function of the first HPF is H ₂ (z). , The transfer function of the second LPF is G
_{If 1} (z) and the transfer function of the second HPF are G ₂ (z),

[0004]

[Equation 1]

The following conditions are required. The perfect reconstruction filter using this quadrature mirror filter is edited by Hiroshi Harashima, "Image Information Compression," edited by Television Society, Ohmsha,
See p192-197 for details.

[0006]

However, in the above-described conventional configuration, four types of filters are required, each filter has a large number of taps, and when the vertical frequency of the image signal is band-limited, A large amount of line memory is used to delay one horizontal scanning time, which causes a problem of increasing the circuit scale.

The present invention solves the above-mentioned problems of the prior art by using two types of filters, and each filter is
It is an object of the present invention to provide a perfect reconstruction filter that can be configured by one or two line memories and can significantly reduce the circuit scale.

[0008]

In order to achieve this object, a perfect reconstruction filter of the present invention comprises a first low-pass filter for band-limiting an input signal at a transmitting side or an encoding side, and a first A first thinning circuit for thinning out the output of the first low pass filter, a second low pass filter for band limiting the output of the first thinning circuit, and a second thinning circuit for thinning the input signal; The output of the second low-pass filter is subtracted from the output of the second thinning circuit, and the output of the first thinning circuit is band-passed on the receiving side or the decoding side. A third low-pass filter for limiting, an adder for adding the output of the first subtractor and the output of the third low-pass filter, and an output of the adder from the output of the first decimation circuit. A second subtractor for subtracting the output of the adder and the second It has a configuration with a switch for selecting alternately output as an input and an output of the subtractor.

[0009]

According to the present invention, with the above-mentioned configuration, the signal obtained by dividing the band and combining is the same as the signal before the division, regardless of the configuration of the orthogonal mirror filter.

[0010]

1 is a block diagram showing the configuration of an encoding apparatus according to a first embodiment of the present invention. In FIG. 1, 1
0 is an input terminal, 11 is a first low-pass filter (hereinafter referred to as LPF) that band-limits the input signal, 12 is a first thinning circuit that thins the output of the first LPF 11 to 1/2,
13 is a second band limiting circuit for the output of the first thinning circuit 12.
LPF, 14 is a delay circuit that delays the input signal, 15 is a second thinning circuit that thins the output of the delay circuit 14 to 1/2, and 16 is a second LP from the output of the second thinning circuit 15.
F13 is a subtractor for subtracting the output of F13, 17 is a transmission line for transmitting the output of the first decimation circuit 12, 18 is a transmission line for transmitting the output of the subtractor 16, and 19 is a first band limiting the output of the transmission line 17. 3 LPF, 20 is an adder for adding the output of the transmission line 18 and the output of the third LPF 19, 21 is the transmission line 1
A coefficient circuit for doubling the output of 7; a subtractor 22 for subtracting the output of the adder 20 from the output of the coefficient circuit 21; a switch 23 for alternately outputting the outputs of the adder 20 and the subtractor 22; Is an output terminal.

The operation of the above configuration will be described with reference to the signal conceptual diagram of FIG. In FIG. 2A, the amplitude at each sampling point of the input signal is shown. First LPF 11
After being band-limited by the transfer function H (z) = (1 + z ^-1 ) / 2 of, the first decimation circuit 12 decimates it to 1/2,
The output is as shown in FIG. However,
In the signal conceptual diagram in (3), the delay time of the filter is omitted.

The output of the first decimation circuit 12 is the second LP.
At F13, the transfer function H (z) = (3 + z ^-1 ) / 4
The band is limited by, and the output is as shown in FIG. The output of the second LPF 13 is subtracted by the signal C from the signal A in the subtractor 16 to obtain the output of FIG.
The signal shown in FIG.

The signal B and the signal D are sent via the transmission lines 17 and 18, and the band of the signal B is band-limited by the third LPF 19 having the same configuration as the second LPF 13 on the receiving side or the decoding side. The output is similar to that of FIG. The signal D and the signal C are added by the adder 20.
The signal E shown in (E) is obtained. The signal B is doubled in the coefficient circuit 21, and the output and the signal E are subtracted from the doubled signal B in the subtractor 22.
The signal shown in (F) is input to the switch 23.
In the switch 23, the signal E and the signal F are alternately output, so that the same signal as the input signal A is obtained.

As described above, according to this embodiment,
After the band is divided by the two types of filters of the first LPF 11 and the second LPF 13 which are not orthogonal to each other, the second LPF 1
The signal before division can be completely reconstructed by the third LPF 19 having the same configuration as that of No. 3 and a simple arithmetic process.

Next, the perfect reconstruction filter of the second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the perfect reconstruction filter in this embodiment. In FIG. 3, 30 is an input terminal and 31 is a first LP.
F and 32 are the first thinning circuit, 33 is the second LPF, and 3
4 is a delay circuit, 35 is a second decimation filter, 36 is a subtraction circuit, 37 and 38 are transmission lines, 39 is a third LPF, 4
0 is an adder, 41 is an arithmetic circuit, 42 is a switch, and 43 is an output terminal.

In this embodiment, the transfer function of each LPF is different from the transfer function of the LPF in the first embodiment, and the coefficient circuit 21 and the subtractor 22 are replaced with an arithmetic circuit 41 accordingly. The operation of the above configuration will be described with reference to the signal conceptual diagram of FIG. However, in the signal conceptual diagram of FIG. 4, a delay time such as a filter is omitted.

In FIG. 4A, the amplitude value at each sampling point in the input signal A is shown. First LPF3
After being band-limited by the transfer function H (z) = (1 + 2z ^-1 + z ^-2 ) / 4 of 1, the first decimation circuit 32 decimates it by 1/2, and the output signal B is shown in FIG. The signal is as shown in B). The signal B output from the first decimation circuit 32 is transferred by the second LPF 33 to the transfer function H (z) = (1 + z
^-1 ) / 2, the output signal C is band-limited by Fig. 4
As shown in (C). The output of the second LPF 33 is
By subtracting the signal C from the signal A decimated in the subtractor 36, the signal shown in FIG. 4D is obtained.

The signal B and the signal D are sent via the transmission lines 37 and 38, and the signal B is transmitted to the second LPF 33 on the receiving side.
The band is limited in the third LPF 39 having the same configuration as the above, and the signal C is obtained. The signal D and the signal C are input to the adder 40 and become the signal E shown in FIG. Signal B and signal E
Is input to the arithmetic circuit 41. The configuration of the arithmetic circuit 41 is shown in FIG. The signal B is input from the terminal 50, and the signal E is input from the terminal 52. Now, the signal B is (a + 2b + c)
/ 4 and the signal E is c, the output of the coefficient circuit 51 is a +
2b + c. The output of the delay circuit 53 is a and the output of the adder 54 is a + c. Then, the output of the subtractor 55 becomes 2b, which is 1/2 in the coefficient circuit 56.
And output as b. Therefore, the output of the arithmetic circuit 41 becomes the signal F as shown in FIG. The signal E and the signal F are input to the switch 42 and alternately output, so that the same signal as the input signal A is output from the output terminal 43.

As described above, according to this embodiment,
3-tap first LPF 31 and 2-tap second LPF 31
The third LPF 3 having the same configuration as the second LPF 33 after band division is performed by the two non-orthogonal filters 33.
9 and a simple arithmetic processing circuit 41 can completely reconstruct the signal before division.

Next, the perfect reconstruction filter of the third embodiment of the present invention will be described. The configuration block diagram of the third embodiment is the same as the configuration of the above-described second embodiment, and therefore will be omitted. The difference is that the first, second and third LPs
They are the transfer functions of F31, 33, 39 and the arithmetic processing method of the arithmetic circuit 41.

The operation of the above configuration will be described with reference to the signal conceptual diagram of FIG. However, in the signal conceptual diagram of FIG. 6, a delay time such as a filter is omitted.

FIG. 6 (A) shows the amplitude value of the signal at each sampling point in the input signal A. First LPF3
The transfer function of 1 is band-limited by the transfer function H (z) = (1 + 4z ^-1 + 3z ^-2 ) / 8, and then the first decimation circuit 32 halves it.
And the output signal B becomes a signal shown in FIG. 6 (B). The signal B output from the first thinning circuit 32 is transferred by the second LPF 33 to the transfer function H (z) = (5 + 3).
The band is limited by z ^-1 ) / 8, and the output signal C is as shown in FIG. 6 (C). The output of the second LPF 33 is obtained by subtracting the signal C from the signal A decimated by the second decimating circuit 35 in the subtractor 36, and
The signal D is as shown in (D).

The signal B and the signal D are transmitted through the transmission lines 37 and 38, and the signal B is transmitted to the second LPF 3 on the receiving side.
The band is limited by the third LPF 39 having the same configuration as the signal No. 3, and the signal C is obtained. The signal D and the signal C are input to the adder 40 and become the signal E shown in FIG. The signal B and the signal E are input to the arithmetic circuit 41. The configuration of the arithmetic circuit 41 is shown in FIG. The signal B is input from the terminal 60, and the terminal 62
Signal E is input. Now, the signal B is (3a + 4b +
c) / 8 and the signal E is c, the output of the coefficient circuit 61 is 3a + 4b + c. The output of the delay circuit 63 is a, the output of the coefficient circuit 64 is 3a, and the output of the adder 65 is 3a + c. The output of the subtractor 66 is 4b
The coefficient circuit 67 outputs 1/4 and outputs it as b from the terminal 68. Therefore, the output of the arithmetic circuit 41 becomes the signal F as shown in FIG. Signal E and signal F
Is input to the switch 42 and alternately output,
The same signal as the input signal A is output from the output terminal 43.

As described above, according to this embodiment,
3-tap first LPF 31 and 2-tap second LPF 31
The third LPF 3 having the same configuration as the second LPF 33 after band division is performed by the two non-orthogonal filters 33.
9 and a simple arithmetic circuit 41 can completely reconstruct the signal before division.

In the third embodiment, the case where the input signal is a wideband video signal and the vertical frequency of the video signal is divided and synthesized will be described. When the vertical frequency of the input wideband video signal is divided into ½ and the divided low frequency components are used as the standard video signal, it is desirable that the divided signals have an interleave relationship. Therefore, the first LPF 31 is provided for each field of the input video signal.
Of the second LPF 33 and the third LPF 39 by switching the transfer function of H (z) = (1 + 4z ^-1 + 3z ^-2 ) / 8 and H (z) = (3 + 4z ^-1 + z ^-2 ) / 8. Similarly, the function is H (z) = (5 + 3z ^-1 ) / 8 and H (z) = (3+
Switch to 5z ^-1 ) / 8. As a result, the signal B is a signal obtained by dividing the input wideband video signal into halves and has an interleave relationship. Further, in the case of combining, it is needless to say that the signal before division can be completely reconstructed by the same operation as that of the above-described embodiment.

In the second embodiment, the second LP
The transfer function of F33 and the third LPF 39 is H (z) = (1
+ Z ^-1 ) / 2, but the second LP with H (z) = 1
It is also possible to omit F33 and the third LPF 39. Further, in the case of combining, it is needless to say that the signal before division can be completely reconstructed by the same operation as that of the above-described embodiment.

[0027]

As described above, according to the present invention, a perfect reconstruction filter can be constructed by using a non-orthogonal filter having a small number of taps, which is practically used in a high efficiency coding apparatus using band division. The effect is very large.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a perfect reconstruction filter according to a first embodiment of the present invention.

FIG. 2 is a signal conceptual diagram for explaining the operation of the perfect reconstruction filter in the first embodiment.

FIG. 3 is a block diagram showing the configuration of a perfect reconstruction filter according to a second embodiment of the present invention.

FIG. 4 is a signal conceptual diagram for explaining the operation of the perfect reconstruction filter in the second embodiment.

FIG. 5 is a block diagram showing a configuration of an arithmetic circuit according to the second embodiment.

FIG. 6 is a signal conceptual diagram for explaining the operation of the perfect reconstruction filter according to the third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an arithmetic circuit according to the third embodiment.

FIG. 8 is a block diagram showing a configuration of a conventional perfect reconstruction filter.

[Explanation of symbols]

 11,31 First low-pass filter 12,15,32,35 Thinning circuit 13,33 Second low-pass filter 16,21,36 Subtractor 17,18,37,38 Transmission line 19,39 Third low pass filter 20,40 Adder 22,42 Switch

Claims (11)

[Claims] 1. A first low-pass filter for band-limiting an input signal on a transmitting side or an encoding side; a first thinning circuit for thinning out an output of the first low-pass filter; A second low-pass filter that band-limits the output of the first thinning circuit, a second thinning circuit that thins the input signal, and a second low-pass filter that outputs the output of the second thinning circuit. A first subtractor for subtracting the output of the filter, a third low-pass filter for band limiting the output of the first decimation circuit on the receiving side or the decoding side, and the first subtraction An adder that adds the output of the adder and the output of the third low-pass filter, a second subtractor that subtracts the output of the adder from the output of the first decimation circuit, and the adder Input and the output of the second subtractor Perfect reconstruction filter and a switch for selecting alternately output to. 2. The perfect reconstruction filter according to claim 1, wherein the first low-pass filter is a non-recursive filter that arithmetically processes two consecutive sampled signals. 3. The transfer function of the first low-pass filter is H (z) = (1 + z ^-1 ) / 2, and the transfer function of the second low-pass filter is H (z) = The perfect reconstruction filter according to claim ^{1, wherein} (3 + z ^-1 ) / 4. 4. A first low-pass filter that band-limits an input signal on a transmitting side or an encoding side; a first thinning circuit that thins out an output of the first low-pass filter; A second low-pass filter that band-limits the output of the first thinning circuit, a second thinning circuit that thins the input signal, and a second low-pass filter that outputs the output of the second thinning circuit. A third low-pass filter for band-limiting the output of the first decimation circuit on the receiving side or the decoding side, and a subtractor for subtracting the output of the filter; An adder for adding the output of the low-pass filter of No. 3, an arithmetic circuit for performing arithmetic processing with the output of the first decimation circuit and the output of the adder as inputs, and the output of the adder and the With the output of the arithmetic circuit as input Perfect reconstruction filter and a switch for selecting alternately output. 5. The perfect reconstruction filter according to claim 1, wherein the second low-pass filter and the third low-pass filter have the same configuration. 6. The perfect reconstruction filter according to claim 1, wherein the second and third low-pass filters are non-recursive filters that perform arithmetic processing on two sampled signals. 7. The second low-pass filter interpolates the output of the first low-pass filter and matches the sampling position of the output of the second decimation circuit with the sampling signal. The perfect reconstruction filter according to claim 1 or 4, characterized in that: 8. The perfect reconstruction filter according to claim 4, wherein the first low-pass filter is a non-recursive filter that arithmetically processes three consecutive sampled signals. 9. The transfer function of the first low-pass filter is H (z) = (1 + 2z ^-1 + z ^-2 ) / 4, and the transfer function of the second low-pass filter is H (z The perfect reconstruction filter according to claim 4, wherein z) = (1 + z ^-1 ) / 2. 10. The transfer function of the first low-pass filter is H (z) = (1 + 4z ^-1 + 3z ^-2 ) / 8, and the transfer function of the second low-pass filter is H (z The perfect reconstruction filter according to claim 4, wherein z) = (5 + 3z ^-1 ) / 8. 11. The input signal is a video signal, and the transfer function of the first low-pass filter is H (z) = (1 + 4z ^-1 + 3z ^-2 ) / 8 and H (z) for each field of the input signal. z) = (3 + 4z ^-1 + z ^-2 ) / 8, and the transfer function of the second low-pass filter is also H (z) = (5 + 3z ^-1 ) / 8 and H (z) 5. The perfect reconstruction filter according to claim 4, wherein: (3 + 5z ^-1 ) / 8.