JPH0362059B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD This invention relates to the processing of digital information, and more particularly to apparatus for processing digital video signals in television systems. Digital devices for processing television signals have been proposed in the past, and among such devices, digital video tape recorders and transmitting devices for transmitting and/or receiving digital video signals have been proposed. Digital signals are typically generated by sampling an analog signal at a predetermined frequency and digitizing the sampled signal by assigning each sample to a particular level. This level value, like the number of bits in the digital word representing each sample signal, is a factor in determining the accuracy of the processing. Another factor is the number of samples taken in a given time, ie the sampling frequency. It is clear that the higher the sampling frequency, the higher the potential accuracy. It is therefore desired, and indeed is done, to choose as high a sampling frequency as possible, although a high sampling frequency requires a large amount of so-called bandwidth at some points in digital television systems, e.g. videotape recorders. There are difficult issues that require reducing the sample size to take into account. We use a digital divider circuit to decimate the digital words after they pass through the digital input filter, which allows the sampling number,
That is, it has been proposed to reduce the word rate. This is satisfactory and the signal can be recorded. During playback, an output interpolation filter can be used to reconstruct the original number of words. Such a pair of processes is called "generation." In practice, there are often many "generations" before the final television image is formed, for example when using "chromakey" techniques. If input and output filtering were to be performed in each production, the gradient characteristics of the filter would result in a reduction in resolution in each production. This is a serious drawback, and becomes even more significant for color component signals in proportion to the number of generations. It is an object of the present invention to monitor a digital signal, to know whether the signal has been previously filtered, and to control whether or not further filtering is performed. It is advantageous to use special filters as input filters, and it is even more advantageous to combine the checking and filtering devices into a single unit so that several parts can be used in common. In order to understand the invention more easily, an embodiment of the invention will be described below by way of example in conjunction with the accompanying drawings, in which: FIG. FIG. 1 shows, in block diagram form, the basic parts of a digital video system used to perform "production." The inputs to the system shown in FIG. 1 are already in digital form. That is, assume that it is made up of a series of digital words, each consisting of a plurality of bits, for example 8 bits. The input digital words a ₀ , a ₁ to a _o are passed through a digital filter 1 to form filtered words b ₀ , b ₁ to b _o , and then processed in a selection circuit 2 to the next stage device. Predetermined words are decimated from the words b ₀ , b ₀ , b _{1 -bo} in order to reduce the total number of words that need to be acted upon, for example by a video tape recorder (not shown).
In this embodiment, every other word is thinned out so that the number of words is halved. For example, if you want to reconstruct a signal after it has been processed in a video tape recorder, it is necessary to feed the processed digital signal into a circuit 3 that replaces every other word with a zero, and then feed the resulting signal into an interpolation filter 4. be. The interpolation filter 4 does not necessarily have to be the same as the input filter 1, but it is preferable that they be the same. It is clear that the attenuation of the output from the interpolation filter 4 each time a "generation" occurs becomes progressively larger as the number of generations increases. Figure 2 can be used as input filter 1.
1 shows one type of filter according to the invention. The filter comprises two word latches 10 and 11 connected in series and clocked at the word frequency by a clock signal.
By using multiplier circuits 13, 14, 15 and adder circuit 16, the three input words are summed together in proportion to produce an output word. Letting the input digital words be a ₀ , a ₁ , a ₂ , a ₃ , the output words from adder circuit 16 will be a series of words b _o of the form: b ₀ =1/4a _-1 +1/2a ₀ +1/4a ₁ b ₁ =1/4a ₀ +1/2a ₁ +1/4a ₂ b ₂ =1/4a ₁ +1/2a ₂ +1/4a _3These words b _o is then connected to an input word latch 21, schematically represented on the left side of FIG.
2 to a circuit 2 having A further latch 24 is shown driven by the antiphase of circuit 23, but is not normally present. The output from latch 22 is a series of digital words, consisting of alternately decimated words from the series of words _bo fed to latch 21. The output of latch 22 can be recorded or transmitted, but if it is desired to reconstruct the original signal constituted by words a , the number of words can be reduced, for example by inserting zero words between the words that were being stored or transmitted. It is necessary to increase the number to the original number. This can be achieved by using the circuit configuration shown on the right side of FIG. This circuit has a data selector switch 30 driven at 1/2 the word frequency, and the output of the selector switch 30 will be either the word bo _or the zero word because the zero word is sent to the other input of the selector switch. The output of data selector switch 30 is then latched at the word frequency by word latch 31 to form a series of words c _o .
In this example, c _o will have the following configuration. c _-1 = 0 c ₀ = b ₀ = 1/4a _-1 + 1/2a ₀ + 1/4a ₁ c ₁ = 0 c ₂ = b ₂ = 1/4a ₁ + 1/2a ₂ + 1/4a ₃ c ₃ = 0 etc. The word c _o is then sent to an interpolation filter 4, shown in more detail in FIG. As it can be seen that the configuration of this input filter is the same as the input filter 1 shown in _FIG . It is to state that. d ₀ =1/8a _-1 +1/4a ₀ +1/8a ₁ d ₁ =1/16a _-1 +1/8a ₀ +1/8a ₁ +1/8a ₂ +1/16a ₃ d ₁ =1/8a ₁ +1/4a ₂ +1/8a ₃ d ₃ =1/16a ₁ +1/8a ₂ +1/8a ₃ +1/8a ₄ +1/16 a ₅ etc. Word d _o is then doubled by circuit 47 to form word e _o , where e ₀ = 2d ₀ e ₁ = 2d ₁ , etc. When circuits such as those described above (FIG. 1) are connected in cascade, the output e _o of one circuit becomes the input a _o of another circuit. When it is desired that the frequency response should not depend on whether a signal has passed through one or more of the above circuits, whether the circuits are connected in cascade or not, an interpolation filter can convert high word rates to low word rates. Therefore, the above desire can be achieved if there is only one non-zero multiplication coefficient in a group of coefficients spatially separated by a number of words equal to the value obtained by division. That is, a coefficient group has coefficients separated by at least one different coefficient, and the interpolation filter 4
The interpolation filter coefficients include only one non-zero value coefficient K ₀ when the word b _o does not want to be changed.
When thinning words at a word ratio of 2:1,
A filter having the following coefficients will satisfy this condition.

TABLE These two-dimensional examples for word rates thinned out in regular order from line to line assume an initial number of words per line, ie an odd number of words. Furthermore, it is believed that an odd number of non-zero terms are needed at an even integer rate to reduce the word rate. In the original example, if n is an even number, the result of the filtering is: e _o-1 = (e _o-2 + e _o )/2 e _o+1 = (e _o + e _o+2 )/2 Therefore, if the following relationship exists at the input of the filter, this means that the signal is already filtered. It can be indicated whether the signal has been processed or not, and the signal has the characteristics of a filtered signal. _ao-1 = ( _ao-2 + _ao )/2 _ao+1 = ( _ao + _ao+2 )/2 For example, the latter example occurs in a uniform feed where each signal is the same. Whenever this occurs, the value of a _o can be used directly in place of b _o . This is sufficient to ensure that the value of b _o in the first encoding and the value of b _o in subsequent encodings are the same, and also to ensure successive filtering in all parts of the image that have already been filtered. Enough to make sure to prevent. In special effects, the foreground may be unfiltered but the background may be filtered, or vice versa. More generally, if n is even and the filter is of type k _-3 , 0, k _-1 , k ₀ , k ₊₁ , 0, k ₊₃ , and k _-3 a _o-4 +k _-2 a _o-2 +k ₁ a _o +k ₃ a _o+2 -k ₀ a _o-1 =0 ...1 and k _-3 a _o-2 +k _-1 a _o +k ₁ a _o+2 +k ₃ For terms such as a _o+4 −k ₀ a _o+1 =0 . . . 2, the signal should be treated as filtered and the filter should be bypassed. That is, equation (1) can be expanded as follows. K _-3 a′ _o-4 =K _-3 K ₀ b _o-4 K _-1 a′ _o-2 =K _-1 K ₀ b _o-2 K ₁ a′ _o =K ₁ K ₀ b _o K ₃ a′ _o+2 =K ₃ K ₀ b _o+2 Therefore, K _-3 a′ _o-4 +K _-1 a′ _o-2 +K ₁ a′ _o +K ₃ a′ _o+2 =K ₀ {K _{- 3} b _o-4 +K _-1 b _o-2 +K ₁ b _o +K ₃ b _o+2 }=K ₀ a′ _o- 1Therefore, K _-3 a′ _o-4 +K _-1 a′ _o-2 +K ₁ a′ _o +K ₃ a′ _o+2 −K0a′ _o-1 = 0 In this way, if the digital signal sample a _o satisfies equation (1), the digital signal is one-dimensionally interpolated with the following coefficients. It has the characteristics of the signal output from the filter 4. In other words, filter processing has been performed. The same can be said about equation (2). FIG. 5 shows a preferred embodiment of an input filter and apparatus combination for monitoring an input signal to determine whether the input signal has been previously filtered. Although such a combination is not necessary, it is considered to be advantageous when monitoring in units of one word, which is almost essential for chroma keying, for example. The filter portion of the circuit is similar to that of FIG. Input word a is sent to latch 51 and then to another latch 52 in series with latch 51. The two latches are controlled at word frequency by a clock signal. Addition circuit 53 adds input word n+1 and the output from latch 52 which was input word n-1, and the resulting addition signal is sent to addition/subtraction circuit 55 via multiplication or scaling circuit 54.
latch 5 representing the input word n.
The output of 1 is added to or subtracted from this sum signal after scaling by scaling circuit 56. The output of latch 51 is also sent to another latch 57, and the output of latch 57 is sent to one input of data selector 58. The output of data selector circuit 58 is sent to latch 59. The other input of the data selector circuit 58 is supplied with alternating output signals from the adder/subtracter circuit 55 via a latch 60. The output of latch 60 is connected to latch 22 shown in FIG.
, and therefore when data selector circuit 58 is controlled to receive data from latch 60, the output from latch 59 is a digitally filtered signal. The remainder of the circuit shown in FIG.
from latch 57 to determine whether the input has already been filtered and toggle data selector circuit 58 to indicate that it will not be filtered by the circuit shown in FIG. This is for controlling the operation of the data selector circuit 58 by receiving signals. Therefore, in this case the output from latch 59 is the same as the input to the circuit, except that every other word is decimated. This monitoring is accomplished by sending the output from adder/subtracter circuit 55 to another latch 61 which is clocked at the same frequency as latch 60 but in antiphase with it, and in comparator circuit 62 to latch 61.
The output of is compared to a reference number or reference band, e.g. 0 or +1 to -1. The output of the comparator is a binary digit indicating whether the input signal has been previously filtered. A 1-bit latch 63 is provided for timing purposes, and the input and output of latch 63 are fed as inputs to gate circuit 64, which is used to control the switching of data selector circuit 58. The embodiment described above reduces the word rate by a factor of two. Other factors can also be used, e.g. 4, but
In this case, the above-mentioned circuit is changed accordingly. As mentioned earlier, the filter section in FIG. 5 may be completely separate from the monitor section;
In this case the filter is the same as shown in FIG. One advantage of the preferred embodiment is that it is only necessary to replace the input filter of an existing device. FIG. 6 shows an example of a two-dimensional filter for reducing the number of samples by half from 455 to 2771/2 according to special case 1 mentioned above. The lower part of the figure is identical in operation to the lower part of FIG. 5, and the upper part performs an operation similar to the upper part of FIG. In this case, 455 samples are taken for each line of video. In view of the similarities between FIGS. 5 and 6, similar parts are designated by the same reference numerals and a detailed description of these parts will not be given. However, 2
In order to construct a dimensional filter, it is necessary to add circuit components, which will be explained below. Basically, a two-dimensional filter like special case 1 is needed to provide a 1-line delay circuit and a 2-line delay circuit. In FIG. 6, one line delay circuit is a 455 word delay circuit 70.
The 2-line delay circuit is a 911-word delay circuit 71. The output of circuit 70 is word latch 5
1 and the output of circuit 71 is sent to adder circuit 72 where it is added to the output of another word latch 73. The output of the adder circuit 72 is sent to another adder circuit 7
3, where it is added to the output of adder circuit 53 before being sent to scaling circuit 54.

[Brief explanation of drawings]

1 is a block diagram of a basic system for reducing the number of digital words and reconstructing the original number of words in a digital signal; FIG. 2 is an input filter for use in the apparatus of FIG. 1;
3 shows another part of the device of FIG. 1; FIG. 4 shows a further part of the device of FIG. 1; FIG. 5 shows an embodiment of a one-dimensional filter according to the invention; and FIG. 1 shows an embodiment of a two-dimensional filter according to the invention. Code in the figure, 1...Digital input filter, 2
...Selection circuit, 3...Circuit for replacing words with zeros alternately, 4...Interpolation filter, 10,
11...Word latch, 13, 14, 15...Multiplication circuit, 16...Addition circuit, 21...Input word latch, 22...Latch, 23...2 division circuit, 2
4...Latch, 30...Data selector switch, 31...Word latch, 47...Double circuit,
51, 52... Latch, 53... Addition circuit, 54
...Multiplication or scaling circuit, 55... Addition/subtraction circuit, 56... Scaling circuit, 57... Latch, 58... Data selector circuit, 59, 60,
61...Latch, 62...Comparison circuit, 63...1
Bit latch, 64... Gate circuit, 70...
455 word delay circuit, 71...911 word delay circuit, 72...addition circuit, 73...word latch.

Claims (1)

Claims: 1. Means for successively receiving input digital words; filtering means 1 for filtering the input digital words to form a series of filtered words; and filtering means 1 for filtering the input digital words to form a series of filtered words; reduction means 2 for reducing the number of words by applying a multiplication factor to the input digital word;
means 54, 56 for generating digital outputs, means 55 for synthesizing said digital outputs, and comparing selected outputs of said digital synthesis outputs of said synthesis means with a reference signal, said input digital word being a filtered word. monitoring means 62 are provided having means 62 for determining whether the input digital word has characteristics similar to that of the filtered word; bypass means 5 for allowing words to pass through said filtering means;
8. A digital signal processing device characterized in that a.8 is provided. 2. Said bypass means comprises a data selector circuit 58 which is arranged to receive as input both an input digital word and a filtered word and to output one of said inputs under the control of said monitoring means. A digital signal processing device according to claim 1. 3. Said filtering means is one in a group of coefficients separated by coefficients different by a number of words equal to the value obtained by dividing the initial number of words per unit time by the reduced number of words per unit time. The digital signal processing device according to claim 1 or 2, having a characteristic that only non-zero multiplication coefficients exist. 4 said reducing means 2, 21 to 24 are arranged to reduce the number of words by half, said filtering means reducing at least a number of words for said monitoring means when the output of said filtering means is not taken in by said reducing means; A digital signal processing device according to any one of claims 1 to 3, which is used to perform the filter processing. 5. The filtering means comprises means 54, 56 for applying a multiplication factor to an input digital word to generate a digital output, and means 55 for combining the digital outputs to generate the filtered word. The digital signal processing device according to scope 3. 6 said monitoring means utilizes a combining means 55 of said digital output generating means and said filtering means and further compares said combined digital output with a reference signal to determine whether said input digital word has similar characteristics to the filtered word; 6. The digital signal processing device according to claim 5, comprising means 62 for determining whether or not the signal is received. 7 Any one of claims 1 to 6 used for processing television signals
The digital signal processing device described in . 8 Any one of claims 1 to 6 used for recording television signals
The digital signal processing device described in . 9. Any one of claims 1 to 6, wherein the filter processing means is a one-dimensional filter.
The digital signal processing device described in . 10. The digital signal processing device according to any one of claims 1 to 6, wherein the filter processing means is a two-dimensional filter. 11 The number of non-zero terms in the filter is 2(n)+
1, where n is an integer. The digital signal processing device according to claim 8 or 10.