JPH05183312A - Delay line and its impedance adjusting method - Google Patents

Abstract

PURPOSE:To provide a delay line easily corresponding to an external circuit with a different impedance and adjusting easily the impedance and its impedance adjusting method. CONSTITUTION:Taper shaped conductor patterns 23, 24 are formed to the end of a conductive strip line 21 formed on a dielectric base 2 so as to be easily matched with the impedance of an external circuit. Furthermore, stepwise conductor patterns are adopted in place of the taper shaped conductor patterns 23, 24 and the impedance of the delay is easily matched with the impedance of an external circuit by eliminating the steps one by one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay line using a distributed constant line and an impedance adjusting method thereof.

[0002]

2. Description of the Related Art A delay line using a distributed constant line in a conventional example will be described with reference to FIGS. FIG. 6 is a diagram for explaining a low impedance delay line in a conventional example. FIG. 7 is a diagram for explaining a high impedance delay line in a conventional example. In FIG. 6, a dielectric substrate 61 is made of an insulating ceramic member, and one surface of the dielectric substrate 61 is coated with a conductive paste and then fired to form a conductive strip line 62. Similarly, the other surface and the recess 63
After the conductive paste is applied to, the conductive paste is baked to form the ground electrode 65 and the input / output electrode 64. On the other hand, on one surface of the dielectric substrate 66, as with the other surface of the dielectric substrate 61, the ground electrode 67 and the input / output electrode 6 are provided.
8 and 69 are formed. The delay line formed by superposing and coupling the dielectric substrates 61 and 66 having such a structure forms an inductor by the conductive strip line 62 and a capacitor by the conductive strip line 62 and the ground electrodes 65, 67 as an equivalent circuit. .. That is, the delay line has an LC ladder structure and constitutes a distributed constant circuit for high frequencies. When the delay line shown in FIG. 6 is used at a high frequency, since it is a distributed constant circuit, if the characteristic impedance of the transmission path and the receiving end impedance do not match, reflection occurs at this portion and the received signal is distorted. generate. Therefore, the delay line shown in FIG. 6 has a wide strip and is used for low impedance.

The difference in shape between the delay line shown in FIG. 7 and the delay line shown in FIG. 6 lies in that the width of the strip line 72 on the dielectric substrate 71 is thin and long, and the entire size is small. The numbers corresponding to the first digit in the seventies in FIG. 7 and the sixties in FIG. 6 represent the same part. The conductive strip line 72 of the delay line has a narrow width as shown in FIG. 7 and is used for high impedance.

[0004]

As described above, when the frequency of use of the delay line becomes high, the reflected wave becomes large and the characteristic deteriorates unless the impedance of the component and the characteristic impedance of the external circuit are matched. In order to avoid this, it is necessary to match the impedances of the external circuit and the delay line. However, the characteristic impedance of the delay line, which is a distributed constant line as shown in FIGS. 6 and 7, is the distance between the conductive strip line and the ground electrode, that is, the thickness of the dielectric substrate, the dielectric constant of the dielectric substrate, and the conductivity. Determined by the width of the sex stripline. Also, there are many types of delay lines depending on the circuit design, and if the thickness, dielectric constant, and conductive strip line width of the dielectric substrate are changed for each type of delay line, the cost becomes high. Therefore, the conventional distributed constant delay line in which the internal characteristic impedance from the input to the output is almost constant has the following problems.
That is, when the external impedance is high, the characteristic impedance of the conductive strip line inside the component is matched with the external impedance, so that the width thereof becomes narrow. In this case, the width of the conductive strip line becomes too narrow, and the resistance of the delay line increases, which causes a problem that the signal is attenuated. When the external impedance is low, the characteristic impedance is matched as in the above case, and the width of the conductive strip line becomes thick. In this case, it is good that the resistance of the delay line is reduced, but there is a problem that the shape becomes large. In addition, since the thick conductive strip line is not suitable for multi-layering, there is a problem that the shape cannot be made smaller if it is made a single layer. Further, when adjusting the impedance, the area of the conductive strip line removed by, for example, a laser differs depending on the type of the delay line. This work required a lot of work because the worker was adjusting the delay line while measuring it.

In order to solve the above problems, the present invention provides a delay line and an impedance adjusting method thereof which can easily perform matching with external circuits having different impedances and can easily adjust the impedance. With the goal.

[0006]

(First Invention) In order to achieve the above object, a delay line according to the present invention has a ground electrode (11 in FIGS. 1 to 5) and a conductive strip line (FIG. 1) on one surface. To one of the dielectric substrates (1, 3 and 5 of FIGS. 1 to 5) on which input / output electrodes (12 and 13 of FIGS. 1 to 5) communicating with (21 to 55 of FIG. 5) are formed. The input / output electrodes (27 in FIGS. 1 to 5) and the ground electrode (22 in FIGS. 1 to 5) leading to the conductive strip lines (21, 55) and the other surface are connected to the conductive strip lines (21, 55). , 54, 57) and another dielectric substrate (2, 4, 6 in FIGS. 1 to 5) on which the conductive strip lines (21, 5) are formed.
5) is formed to form a tapered conductive pattern (23, 24, 31, 56 in FIGS. 1 and 3 to 5) at the end.

(Second Invention) The conductive strip line (21) and the input / output electrodes (12, 12) in the above delay line.
13) between the stepwise conductive pattern (2 in FIG. 2).
8, 29).

(Third invention) In the impedance adjusting method for the delay line, the step-like conductive pattern (28, 29) formed between the conductive strip line (21) and the input / output electrodes (12, 13) is used. ) Adjust the impedance by removing at least one of the steps in.

[0009]

[Operation] (First invention) The tapered conductive pattern formed between the conductive strip line and the input / output electrode may be thicker toward the input / output electrode, or vice versa. It may be formed so as to narrow toward one side, or one side may be thicker and the other side may be thinner. The delay line of the above combination that matches the impedance of the external circuit is manufactured, and the final impedance adjustment is performed at the taper portion. Therefore, the characteristic impedance of the delay line can be designed without depending on the impedance of the external circuit.

(Second and Third Inventions) The staircase-shaped conductive pattern formed at the end of the conductive stripline in the delay line can be removed by, for example, a laser using each staircase as a guide. In other words, if the number of lines to be deleted in the staircase is determined according to the type of delay line, the adjustment work is simplified and does not require skill, and it is possible to use different types of conductive patterns from the one with the same shape. There is a delay line. In addition, since the stairs can be easily recognized by a camera or the like, impedance adjustment can be automated.

[0011]

EXAMPLE FIG. 1 is a diagram for explaining an example of a delay line connected to a low impedance circuit.
In FIG. 1, the dielectric substrate 1 has recesses 14 and 15 formed at both ends in the longitudinal direction thereof. Also, the dielectric substrate 1
On the upper surface of the conductive paste, a conductive paste is applied to substantially the entire area and a small area communicating with the recesses 14 and 15 separated from the area. After that, the dielectric substrate 1 coated with the conductive paste is fired to form the ground electrode 11, the conductive film of the recesses 14 and 15 and the input / output electrodes 12 and 13. The dielectric substrate 2 has recesses 2 at both ends in the longitudinal direction.
5, 26 are formed. The lower surface of the dielectric substrate 2 and the recesses 25 and 26 are coated with a conductive paste and then fired to form the ground electrode 22, the input / output electrode 27, and the recess 25 having the same shape as the upper surface of the dielectric substrate 1. , 26 are formed. In addition, on the upper surface of the dielectric substrate 2,
After the conductive paste is applied, the conductive paste is baked to form the concave portions 25, 2
6 has tapered taper portions 23 and 2 at both ends communicating with the conductive film 6.
4 and a zigzag-shaped conductive strip line 21 having a narrow width is formed between the thick tapered portions 23 and 24. The dielectric substrates 1 and 2 are made of, for example, ceramic having a good dielectric constant temperature coefficient, and the conductive paste is made of, for example, silver paste.

Then, the dielectric substrate 1 and the dielectric substrate 2
Means that the ground electrodes 11 and 22 are on the outside and the conductive strip line 21 is on the inside, and a glass frit or the like is applied between them, and they are bonded by heating. With such a configuration, the tapered tip portions 23 and 24 are formed thicker toward the input / output electrodes 12 and 13, so that the characteristic impedance of the conductive strip line 21 and the impedance of the external circuit having a lower value can be obtained. You can get a delay line that matches. It should be noted that the impedance is adjusted by measuring the impedance before joining the dielectric substrate 1 and the dielectric substrate 2 with each other, for example, by using the laser or the like to form the thick taper portion 2
This is done by deleting a part of 3 and 24.

FIG. 2 is a diagram for explaining another embodiment of the delay line connected to the low impedance circuit.
In the delay line in FIG. 2, the tapered portions 23 and 24 of the delay line in FIG.
The difference is that. That is, the stair parts 28 and 29 of the delay line shown in FIG.
2, 283 and 291, 292, 293. There are many types of delay lines because it is necessary to match different frequencies and impedances of external circuits. However, the staircase 28 as described above,
If 29 is provided, for example, steps 281, 282, 28
The impedance is matched by removing some of 3, and 291, 292, 293. That is, steps 281, 282, 283, and 291, 29
The numbers 2, 293 serve as a guide when deleting. Then, the step portions 28 and 29 can be removed by masking a part of the screen at the printing stage or when the characteristics of the dielectric filter are adjusted by laser. Further, when the characteristics of the dielectric filter are adjusted by a laser, the step portion 28 as described above,
Since 29 can be easily recognized by a camera or the like, automation can be easily performed.

FIG. 3 is an explanatory view of a delay line according to another embodiment of the present invention, the input and output terminals of which can accommodate different impedances. The delay line in FIG. 3 is the thick tapered portion 2 of the delay line in FIG.
The difference is that one of the points 3 and 24 is a tapered portion 31. That is, the delay line shown in FIG. 3 includes a tapered taper portion 23 having a low impedance on one side and a tapered taper portion 31 having a high impedance on the other side. By using a delay line with such a configuration,
It can cope with high impedance and low impedance in the external circuit.

FIG. 4 is a diagram for explaining a delay line connected to a high impedance circuit according to another embodiment of the present invention. The delay line in FIG. 4 is different in that the thick tapered portions 23 and 24 of the delay line in FIG. 1 are tapered tapered portions 31. That is, FIG.
The delay line shown in (1) is composed of tapered taper portions 31 having high impedance at both ends. With the delay line having such a configuration, it is possible to cope with a high impedance in an external circuit connected to both electrodes.

FIG. 5 is a diagram for explaining a delay line having a laminated structure in another embodiment of the present invention. 5, a dielectric substrate 3 is substantially the same as the dielectric substrate 1 shown in FIG. 1, and includes a ground electrode 11, a recess 14 in which a conductive film is formed together with the input / output electrode 12, and an input / output electrode 13 as well. And a concave portion 15 in which a conductive film is formed. The dielectric substrate 4 shown in FIG. 5 has a conductive strip line 41 similar to the conductive strip line 21 shown in FIG. 1 on one surface thereof, and a conductive film which is invisible in the drawing and communicates with the conductive strip line 41. And a recess 42 formed with a conductive film that communicates with the input / output electrodes 13 of the dielectric substrate 1, and a conductive strip line 4
1 and a through hole 44 provided in the first. The dielectric substrate 5 shown in FIG. 5 has a ground electrode 5 on one surface thereof.
1 and an opening 52 formed in a part of the earth electrode 51.
A through hole 53 formed in the opening 52, and recesses 55 and 56 in which a conductive film that is electrically isolated from the ground electrode 51 is formed. The dielectric substrate 6 shown in FIG. 5 has a conductive strip line 61 on one surface thereof and a conductive strip line 61 that communicates with the conductive strip line 61, and has a tapered tip portion 62 in the end direction and a tapered tip portion 62. Recessed portion 63 in which a communicating conductive film is formed
And a recess 64 in which a conductive film that is electrically isolated from the conductive strip line 61 is formed in a portion facing the recess 63, and an input / output electrode 65 (which communicates with the recesses 63, 64 on the other surface). One is not visible in the figure), and the other surface is also provided with an input / output electrode 65 and a ground electrode 66 electrically separated.

Then, the dielectric substrates 3 to 6 are stacked and then joined by, for example, a glass frit or the like. At the time of this bonding, the input / output electrode 12 communicates with the conductive strip line 41 via the conductive film of the recess 14.
In addition, the conductive strip line 41 is connected to the through hole 4
4 and 53 to the conductive strip line 61. Further, the conductive strip line 61 is connected to the input / output electrode 65 through the thick taper portion 62 and the concave portion 63 in which the conductive film is formed. In addition, the input / output electrode 13 has recesses 15, 43, 5 in which a conductive film is formed.
6 to the conductive strip line 61, and further to the conductive strip line 41 via the through holes 53 and 44, and the recess 14 in which the conductive film is formed.
Is connected to the input / output electrode 12. At the same time, the input / output electrode 12 has recesses 14, 42, 5 in which conductive films are formed.
The other input / output electrodes (not shown) are connected via 5, 64. With such a configuration, the delay line is configured by the inductor formed of the conductive strip line, the conductive strip line, and the capacitor formed of the ground electrode.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments. And
Various design changes can be made without departing from the invention as set forth in the claims. For example, the shape of the tapered portion may be a triangle, or the shape of the staircase portion may be a rectangle in addition to the square shape as in the embodiment.
It goes without saying that various modifications such as a triangle and a shape with rounded corners are included unless the gist of the present invention is changed.

[0019]

As described in detail above, according to the present invention,
By providing a tapered portion at the end of the conductive strip line, it is possible to make it compatible with either an external circuit with high impedance or an external circuit with low impedance.
When the conductive strip line is provided with a step portion, the step portion serves as a guide, and a delay line having a different impedance can be obtained by a simple operation. With the configuration according to the present invention, it is possible to obtain a small delay line with well-balanced insertion loss.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of a delay line connected to a low impedance circuit.

FIG. 2 is a diagram for explaining another embodiment of a delay line connected to a low impedance circuit.

FIG. 3 is an explanatory diagram of a delay line whose input and output ends can cope with different impedances.

FIG. 4 is a diagram for explaining a delay line connected to a high impedance circuit according to another embodiment of the present invention.

FIG. 5 is a diagram for explaining a delay line having a laminated structure in another embodiment of the present invention.

FIG. 6 is a diagram for explaining a low impedance delay line in a conventional example.

FIG. 7 is a diagram for explaining a high impedance delay line in a conventional example.

[Explanation of symbols]

1 to 6 ... Dielectric substrate 11, 22, 51, 54, 57, 66 ... Ground electrode 12, 13, 27, 65 ... Input / output electrode 14, 15, 25, 26, 42, 43, 63, 64 ...
・ Concave portions 21, 41, 55, 61 ... Conductive strip lines 23. 24, 62 ... Tapered tapered portions 28, 29 ... Step portions 31, 62 ... Tapered tapered portions 44, 53 ...・ Through hole 52 ・ ・ ・ Opening

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Imaizumi 6-16-20 Ueno, Taito-ku, Tokyo Taiyo Induction Co., Ltd.

Claims (3)

[Claims] 1. A dielectric substrate having a ground electrode and an input / output electrode connected to a conductive strip line formed on one surface, and the conductive strip line formed on one surface and the conductive strip line formed on another surface. A delay line in which a taper-shaped conductive pattern is formed at an end of a conductive strip line in a delay line in which another dielectric substrate having an output electrode and a ground electrode is overlapped and coupled. 2. A dielectric substrate having a ground electrode and an input / output electrode communicating with a conductive strip line formed on one surface, and the conductive strip line formed on one surface and the conductive strip line formed on the other surface. A delay line in which a stepwise conductive pattern is formed at an end of a conductive strip line in a delay line in which another dielectric substrate having an output electrode and a ground electrode formed thereon is superposed and coupled. 3. The impedance of the delay line, wherein the delay line is adjusted to have different impedances by deleting at least one of the steps in the stepwise conductive pattern formed at the end of the conductive strip line. Adjustment method.