JPH05183119A - Sram equipped with step-down circuit - Google Patents

Sram equipped with step-down circuit

Info

Publication number
JPH05183119A
JPH05183119A JP3347314A JP34731491A JPH05183119A JP H05183119 A JPH05183119 A JP H05183119A JP 3347314 A JP3347314 A JP 3347314A JP 34731491 A JP34731491 A JP 34731491A JP H05183119 A JPH05183119 A JP H05183119A
Authority
JP
Japan
Prior art keywords
circuit
step
sram
voltage
down
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3347314A
Other languages
Japanese (ja)
Inventor
Tokuo Inoue
徳夫 井上
Original Assignee
Sharp Corp
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp, シャープ株式会社 filed Critical Sharp Corp
Priority to JP3347314A priority Critical patent/JPH05183119A/en
Publication of JPH05183119A publication Critical patent/JPH05183119A/en
Application status is Withdrawn legal-status Critical

Links

Abstract

PURPOSE: To realized SRAM equipped with a step-down circuit which can reduce a consumed current by a compact circuit constitution and can also decrease the consumed current at a stand-by time markedly.
CONSTITUTION: A reference voltage Vref generated in a reference-voltage generation circuit 2 is received by a source follower circuit formed of NMOS transistor M1 and the output of the source follower circuit is supplied as drive current to a peripheral circuit 3 and memory cell 4. The reference-voltage generation circuit 2 generates Vref+Vth as reference voltage for the purpose of compensating for the voltage drop Vth of the NMOS transistor M1.
COPYRIGHT: (C)1993,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体装置のSRAM BACKGROUND OF THE INVENTION This invention is, SRAM of the semiconductor device
に関し、より詳しくは外部電源を内部で降圧する降圧回路を備えたSRAMに関する。 Relates, more particularly SRAM having a step-down circuit for stepping down the external power internally.

【0002】 [0002]

【従来の技術】図2に従来の降圧回路を備えたSRAM BACKGROUND OF THE INVENTION SRAM having a conventional step-down circuit in FIG. 2
を示す。 It is shown. 基準電圧発生回路2により発生した基準電圧V Reference voltage V generated by the reference voltage generating circuit 2
refをオペアンプOP1で形成されるボルテージホロワ回路により電流駆動能力を持たせており、この基準電圧V refを周辺回路3およびメモリセル4に供給する回路構成をとる。 ref and to have a current driving capability by the voltage follower circuit formed by the operational amplifier OP1, taking a circuit configuration for supplying the reference voltage V ref to the peripheral circuit 3 and memory cell 4.

【0003】 [0003]

【発明が解決しようとする課題】ところで、上記従来の降圧回路は、電流駆動能力を有する必要上、オペアンプOP1を用いているため、消費電力は10μA程度は流す必要がある。 [SUMMARY OF THE INVENTION Incidentally, the conventional step-down circuit, the need to have a current driving capability, the use of the operational amplifier OP1, the power consumption has to 10μA about the flow. このため、超低消費電流を目指すSRA For this reason, SRA aimed at ultra-low current consumption
Mの降圧回路として使用するには、消費電力が多すぎるという問題点がある。 To use as a step-down circuit M has a problem that power consumption is too much.

【0004】又、ボルテージホロワ回路を設計する際に、発振余裕やオフセット電圧の問題等、設計上注意すべき点が多く、回路構成の簡潔化を図る上で難点があった。 [0004] Also, when designing a voltage follower circuit, problems such as an oscillation margin and an offset voltage, many caveats design, there is a difficulty in achieving simplicity of the circuit configuration.

【0005】本発明は、このような従来技術の問題点を解決するものであり、簡潔な回路構成で消費電流を低減できる降圧回路を備えたSRAMを提供することを目的とする。 [0005] The present invention is intended to solve the problems of the prior art, and an object thereof is to provide a SRAM with a step-down circuit that can reduce current consumption in a simplified circuit configuration.

【0006】 [0006]

【課題を解決するための手段】本発明の降圧回路を備えたSRAMは、外部電源を内部で降圧する降圧回路を備えたSRAMにおいて、該外部電源よりV CCレベルが印加されると、基準電圧回路でNMOSトランジスタをドライブし、かつドライブのための基準電圧を該NMOS SRAM having a step-down circuit of the present invention, in order to solve the problems], in SRAM having a step-down circuit for stepping down the external power source internally, the V CC level is applied from the external source, the reference voltage It drives the NMOS transistor in the circuit, and the NMOS a reference voltage for the drive
トランジスタによる電圧降圧分を補償したレベルに設定してなり、そのことにより上記目的が達成される。 Be set to a level to compensate for the voltage step-down caused by the transistor, the objects can be achieved.

【0007】 [0007]

【作用】上記構成によれば、NMOSトランジスタでソースホロワ回路が形成されるので、従来必要であったオペアンプが不要になる。 According to the above arrangement, since the source follower circuit is formed by NMOS transistors, conventionally required operational amplifier is not required. 従って、消費電流の低減が図れる。 Therefore, consumption can be reduced current. また、回路構成を簡潔にできる。 Also, possible circuit structure briefly.

【0008】更には、NMOSトランジスタによる電圧降下が補償されるので、メモリセル等に規定の電圧レベルが印加される。 [0008] Furthermore, since the voltage drop due to the NMOS transistor is compensated, the voltage level of the defined memory cell or the like is applied.

【0009】 [0009]

【実施例】以下に本発明の実施例を説明する。 The embodiment of the present invention PREFERRED EMBODIMENTS Hereinafter will be described.

【0010】図1は本発明降圧回路を備えたSRAMの回路構成を示す。 [0010] Figure 1 shows a circuit structure of the SRAM having the present invention step-down circuit. 以下にその構成を動作と共に説明する。 It will be described together with the operation of the structure below.

【0011】このSRAM1は、基準電圧発生回路2で発生した基準電圧V refをNMOSトランジスタM1で形成されるソースホロワ回路で受け、該ソースホロワ回路に電流駆動能力を持たせている。 [0011] The SRAM1 receives a reference voltage V ref generated by the reference voltage generating circuit 2 in source follower circuit formed by the NMOS transistors M1, is to have a current driving capability to the source follower circuit. すなわち、該ソースホロワ回路の出力を周辺回路3およびメモリセル4に駆動電流として供給している。 That, is supplied as the driving current output of the source follower circuits in the peripheral circuit 3 and memory cell 4.

【0012】この場合、NMOSトランジスタM1でV [0012] In this case, V in the NMOS transistor M1
thの電圧降下があるが、この電圧降下V thは次のようにして補償される。 Although voltage drop th is, the voltage drop V th is compensated in the following manner. すなわち、外部電源V CCよりV CCレベルが印加されると、基準電圧発生回路2でV ref +V th That is, if V CC level is applied from an external power source V CC, V ref + V th in the reference voltage generating circuit 2
を発生させる。 The cause. つまり、本実施例では、基準電圧発生回路2でV thの電圧降下分に見合った基準電圧を発生させるのである。 That is, in this embodiment, is to generate a reference voltage by the reference voltage generating circuit 2 commensurate with the voltage drop of V th.

【0013】これにより、本実施例においては、周辺回路3およびメモリセル4にV OUT ≒V refの規定レベルの出力を供給することができる。 [0013] Thus, in this embodiment, it is possible to supply the output of the specified level of V OUT ≒ V ref in the peripheral circuit 3 and memory cell 4.

【0014】上記の回路構成によれば、従来回路で必要であったボルテージホロワ回路を形成するオペアンプO According to the above circuit configuration, the operational amplifier O to form a voltage follower circuit was required in the conventional circuit
P1を省略することができる。 It is possible to omit the P1. 従って、降圧回路の消費電流を小さくでき、SRAM1のスタンバス時の消費電流を節約できる。 Therefore, it is possible to reduce the consumption current of the step-down circuit can conserve current during Sutanbasu the SRAM 1.

【0015】また、発振余裕やオフセット電圧の問題等を考慮する必要がないので、回路構成の簡潔化が図れる。 Further, since there is no need to consider the problems and the like of the oscillation margin and an offset voltage, thereby the simplification of the circuit configuration.

【0016】 [0016]

【発明の効果】以上の本発明降圧回路を備えたSRAM SRAM having the above present invention step-down circuit according to the present invention
によれば、NMOSトランジスタでソースホロワ回路が形成されるので、従来必要であったオペアンプが不要になる。 According to, the source follower circuit is formed by NMOS transistors, conventionally required operational amplifier is not required. 従って、消費電流の低減が図れ、SRAMのスタンバイ時における消費電流を節約できる。 Thus, a reduction in current consumption Hakare, saving current consumption in the standby SRAM. また、回路構成を簡潔にできる。 Also, possible circuit structure briefly.

【0017】更には、NMOSトランジスタによる電圧降下が補償されるので、メモリセル等に規定の電圧レベルを印加できる。 [0017] Furthermore, since the voltage drop due to the NMOS transistor is compensated, a voltage can be applied a prescribed level in the memory cell or the like.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明降圧回路を備えたSRAMの回路構成図。 [1] The present invention circuit diagram of a SRAM having a step-down circuit.

【図2】降圧回路を備えたSRAMの一従来例を示す回路構成図。 Figure 2 is a circuit diagram showing an example of a conventional SRAM having a step-down circuit.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 SRAM 2 基準電圧発生回路 3 周辺回路 4 メモリセル M1 NMOSトランジスタ 1 SRAM 2 reference voltage generating circuit 3 peripheral circuit 4 memory cell M1 NMOS transistor

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】外部電源を内部で降圧する降圧回路を備えたSRAMにおいて、 該外部電源よりV CCレベルが印加されると、基準電圧回路でNMOSトランジスタをドライブし、かつドライブのための基準電圧を該NMOSトランジスタによる電圧降圧分を補償したレベルに設定した降圧回路を備えたS 1. A SRAM having a step-down circuit for stepping down the external power source internally, the V CC level than external power is applied, the drive and the NMOS transistors in the reference voltage circuit and a reference voltage for the drive It was provided with a step-down circuit is set to a level which compensates for the voltage step-down caused by the NMOS transistors S
    RAM。 RAM.
JP3347314A 1991-12-27 1991-12-27 Sram equipped with step-down circuit Withdrawn JPH05183119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3347314A JPH05183119A (en) 1991-12-27 1991-12-27 Sram equipped with step-down circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3347314A JPH05183119A (en) 1991-12-27 1991-12-27 Sram equipped with step-down circuit

Publications (1)

Publication Number Publication Date
JPH05183119A true JPH05183119A (en) 1993-07-23

Family

ID=18389385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3347314A Withdrawn JPH05183119A (en) 1991-12-27 1991-12-27 Sram equipped with step-down circuit

Country Status (1)

Country Link
JP (1) JPH05183119A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292424B1 (en) 1995-01-20 2001-09-18 Kabushiki Kaisha Toshiba DRAM having a power supply voltage lowering circuit
US6351426B1 (en) 1995-01-20 2002-02-26 Kabushiki Kaisha Toshiba DRAM having a power supply voltage lowering circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292424B1 (en) 1995-01-20 2001-09-18 Kabushiki Kaisha Toshiba DRAM having a power supply voltage lowering circuit
US6351426B1 (en) 1995-01-20 2002-02-26 Kabushiki Kaisha Toshiba DRAM having a power supply voltage lowering circuit

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A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990311