JPH05183119A - Sram equipped with step-down circuit - Google Patents
Sram equipped with step-down circuitInfo
- Publication number
- JPH05183119A JPH05183119A JP3347314A JP34731491A JPH05183119A JP H05183119 A JPH05183119 A JP H05183119A JP 3347314 A JP3347314 A JP 3347314A JP 34731491 A JP34731491 A JP 34731491A JP H05183119 A JPH05183119 A JP H05183119A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- sram
- nmos transistor
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置のＳＲＡＭ
に関し、より詳しくは外部電源を内部で降圧する降圧回
路を備えたＳＲＡＭに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device SRAM.
More specifically, the present invention relates to an SRAM including a step-down circuit that steps down an external power supply internally.
【０００２】[0002]
【従来の技術】図２に従来の降圧回路を備えたＳＲＡＭ
を示す。基準電圧発生回路２により発生した基準電圧Ｖ
refをオペアンプＯＰ１で形成されるボルテージホロワ
回路により電流駆動能力を持たせており、この基準電圧
Ｖrefを周辺回路３およびメモリセル４に供給する回路
構成をとる。2. Description of the Related Art FIG. 2 shows an SRAM having a conventional step-down circuit.
Indicates. Reference voltage V generated by the reference voltage generation circuit 2
ref and to have a current driving capability by the voltage follower circuit formed by the operational amplifier OP1, taking a circuit configuration for supplying the reference voltage V ref to the peripheral circuit 3 and memory cell 4.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記従来の
降圧回路は、電流駆動能力を有する必要上、オペアンプ
ＯＰ１を用いているため、消費電力は１０μＡ程度は流
す必要がある。このため、超低消費電流を目指すＳＲＡ
Ｍの降圧回路として使用するには、消費電力が多すぎる
という問題点がある。By the way, since the above-mentioned conventional step-down circuit needs to have a current driving capability and uses the operational amplifier OP1, the power consumption needs to be about 10 μA. For this reason, SRA aiming at ultra-low current consumption
There is a problem that the power consumption is too large to be used as a step-down circuit for M.
【０００４】又、ボルテージホロワ回路を設計する際
に、発振余裕やオフセット電圧の問題等、設計上注意す
べき点が多く、回路構成の簡潔化を図る上で難点があっ
た。Further, when designing a voltage follower circuit, there are many points to be noted in the design, such as problems of oscillation margin and offset voltage, which is a problem in simplifying the circuit configuration.
【０００５】本発明は、このような従来技術の問題点を
解決するものであり、簡潔な回路構成で消費電流を低減
できる降圧回路を備えたＳＲＡＭを提供することを目的
とする。An object of the present invention is to solve the above problems of the prior art, and to provide an SRAM having a step-down circuit capable of reducing current consumption with a simple circuit configuration.
【０００６】[0006]
【課題を解決するための手段】本発明の降圧回路を備え
たＳＲＡＭは、外部電源を内部で降圧する降圧回路を備
えたＳＲＡＭにおいて、該外部電源よりＶCCレベルが印
加されると、基準電圧回路でＮＭＯＳトランジスタをド
ライブし、かつドライブのための基準電圧を該ＮＭＯＳ
トランジスタによる電圧降圧分を補償したレベルに設定
してなり、そのことにより上記目的が達成される。An SRAM provided with a step-down circuit according to the present invention is an SRAM provided with a step-down circuit for internally stepping down an external power supply, and when a V CC level is applied from the external power supply, a reference voltage is applied. The circuit drives an NMOS transistor, and a reference voltage for driving is supplied to the NMOS transistor.
The level is set so as to compensate for the voltage step-down by the transistor, whereby the above object is achieved.
【０００７】[0007]
【作用】上記構成によれば、ＮＭＯＳトランジスタでソ
ースホロワ回路が形成されるので、従来必要であったオ
ペアンプが不要になる。従って、消費電流の低減が図れ
る。また、回路構成を簡潔にできる。According to the above structure, since the source follower circuit is formed by the NMOS transistor, the operational amplifier, which has been necessary in the past, becomes unnecessary. Therefore, current consumption can be reduced. Also, the circuit configuration can be simplified.
【０００８】更には、ＮＭＯＳトランジスタによる電圧
降下が補償されるので、メモリセル等に規定の電圧レベ
ルが印加される。Furthermore, since the voltage drop due to the NMOS transistor is compensated, a prescribed voltage level is applied to the memory cell or the like.
【０００９】[0009]
【実施例】以下に本発明の実施例を説明する。EXAMPLES Examples of the present invention will be described below.
【００１０】図１は本発明降圧回路を備えたＳＲＡＭの
回路構成を示す。以下にその構成を動作と共に説明す
る。FIG. 1 shows a circuit configuration of an SRAM having a step-down circuit according to the present invention. The configuration will be described below together with the operation.
【００１１】このＳＲＡＭ１は、基準電圧発生回路２で
発生した基準電圧ＶrefをＮＭＯＳトランジスタＭ１で
形成されるソースホロワ回路で受け、該ソースホロワ回
路に電流駆動能力を持たせている。すなわち、該ソース
ホロワ回路の出力を周辺回路３およびメモリセル４に駆
動電流として供給している。In this SRAM 1, the source follower circuit formed by the NMOS transistor M1 receives the reference voltage V ref generated by the reference voltage generating circuit 2, and the source follower circuit is provided with a current driving capability. That is, the output of the source follower circuit is supplied to the peripheral circuit 3 and the memory cell 4 as a drive current.
【００１２】この場合、ＮＭＯＳトランジスタＭ１でＶ
thの電圧降下があるが、この電圧降下Ｖthは次のように
して補償される。すなわち、外部電源ＶCCよりＶCCレベ
ルが印加されると、基準電圧発生回路２でＶref＋Ｖth
を発生させる。つまり、本実施例では、基準電圧発生回
路２でＶthの電圧降下分に見合った基準電圧を発生させ
るのである。In this case, V is applied to the NMOS transistor M1.
Although there is a voltage drop of th , this voltage drop V th is compensated as follows. That is, when the V CC level is applied from the external power supply V CC , V ref + V th is generated in the reference voltage generating circuit 2.
Generate. That is, in this embodiment, the reference voltage generating circuit 2 generates a reference voltage commensurate with the voltage drop of V th .
【００１３】これにより、本実施例においては、周辺回
路３およびメモリセル４にＶOUT≒Ｖrefの規定レベルの
出力を供給することができる。As a result, in this embodiment, it is possible to supply the peripheral circuit 3 and the memory cell 4 with an output of a prescribed level of V OUT ≈V ref .
【００１４】上記の回路構成によれば、従来回路で必要
であったボルテージホロワ回路を形成するオペアンプＯ
Ｐ１を省略することができる。従って、降圧回路の消費
電流を小さくでき、ＳＲＡＭ１のスタンバス時の消費電
流を節約できる。According to the above circuit configuration, the operational amplifier O forming the voltage follower circuit required in the conventional circuit is formed.
P1 can be omitted. Therefore, the current consumption of the step-down circuit can be reduced, and the current consumption of the SRAM 1 at the time of the stanbus can be saved.
【００１５】また、発振余裕やオフセット電圧の問題等
を考慮する必要がないので、回路構成の簡潔化が図れ
る。Since it is not necessary to consider the problems of oscillation margin and offset voltage, the circuit structure can be simplified.
【００１６】[0016]
【発明の効果】以上の本発明降圧回路を備えたＳＲＡＭ
によれば、ＮＭＯＳトランジスタでソースホロワ回路が
形成されるので、従来必要であったオペアンプが不要に
なる。従って、消費電流の低減が図れ、ＳＲＡＭのスタ
ンバイ時における消費電流を節約できる。また、回路構
成を簡潔にできる。The SRAM provided with the above step-down circuit of the present invention.
According to this, since the source follower circuit is formed by the NMOS transistor, the operational amplifier which has been necessary in the past becomes unnecessary. Therefore, the current consumption can be reduced, and the current consumption during the standby of the SRAM can be saved. Also, the circuit configuration can be simplified.
【００１７】更には、ＮＭＯＳトランジスタによる電圧
降下が補償されるので、メモリセル等に規定の電圧レベ
ルを印加できる。Furthermore, since the voltage drop due to the NMOS transistor is compensated, a prescribed voltage level can be applied to the memory cell or the like.
【図１】本発明降圧回路を備えたＳＲＡＭの回路構成
図。FIG. 1 is a circuit configuration diagram of an SRAM including a step-down circuit of the present invention.
【図２】降圧回路を備えたＳＲＡＭの一従来例を示す回
路構成図。FIG. 2 is a circuit configuration diagram showing an example of a conventional SRAM having a step-down circuit.
１ ＳＲＡＭ ２ 基準電圧発生回路 ３ 周辺回路 ４ メモリセル Ｍ１ ＮＭＯＳトランジスタ 1 SRAM 2 Reference voltage generation circuit 3 Peripheral circuit 4 Memory cell M1 NMOS transistor
Claims (1)
たＳＲＡＭにおいて、 該外部電源よりＶCCレベルが印加されると、基準電圧回
路でＮＭＯＳトランジスタをドライブし、かつドライブ
のための基準電圧を該ＮＭＯＳトランジスタによる電圧
降圧分を補償したレベルに設定した降圧回路を備えたＳ
ＲＡＭ。1. An SRAM having a step-down circuit for internally stepping down an external power supply, wherein when a V CC level is applied from the external power supply, a reference voltage circuit drives an NMOS transistor, and a reference voltage for driving. S equipped with a step-down circuit that sets the voltage to a level that compensates for the step-down of the voltage by the NMOS transistor.
RAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3347314A JPH05183119A (en) | 1991-12-27 | 1991-12-27 | Sram equipped with step-down circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3347314A JPH05183119A (en) | 1991-12-27 | 1991-12-27 | Sram equipped with step-down circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05183119A true JPH05183119A (en) | 1993-07-23 |
Family
ID=18389385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3347314A Withdrawn JPH05183119A (en) | 1991-12-27 | 1991-12-27 | Sram equipped with step-down circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05183119A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07334256A (en) * | 1994-06-13 | 1995-12-22 | Nippondenso Co Ltd | Power source circuit |
| US6292424B1 (en) | 1995-01-20 | 2001-09-18 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
| US6351426B1 (en) | 1995-01-20 | 2002-02-26 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
-
1991
- 1991-12-27 JP JP3347314A patent/JPH05183119A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07334256A (en) * | 1994-06-13 | 1995-12-22 | Nippondenso Co Ltd | Power source circuit |
| US6292424B1 (en) | 1995-01-20 | 2001-09-18 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
| US6351426B1 (en) | 1995-01-20 | 2002-02-26 | Kabushiki Kaisha Toshiba | DRAM having a power supply voltage lowering circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |