JPH05183016A - Tab tape carrier - Google Patents

Tab tape carrier

Info

Publication number
JPH05183016A
JPH05183016A JP35793291A JP35793291A JPH05183016A JP H05183016 A JPH05183016 A JP H05183016A JP 35793291 A JP35793291 A JP 35793291A JP 35793291 A JP35793291 A JP 35793291A JP H05183016 A JPH05183016 A JP H05183016A
Authority
JP
Japan
Prior art keywords
copper
plating
tape carrier
lead
copper lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35793291A
Other languages
Japanese (ja)
Inventor
Makoto Goto
誠 後藤
Osamu Yoshioka
修 吉岡
Norio Okabe
則夫 岡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP35793291A priority Critical patent/JPH05183016A/en
Publication of JPH05183016A publication Critical patent/JPH05183016A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern

Abstract

PURPOSE:To improve the resistance to whisker and make it possible to enhance the reliability of a semiconductor device by providing a specific thin copper plating interstitially between a copper lead and tin plating. CONSTITUTION:A tin plating 4 is applied to the surface of a copper lead 2 having a given pattern which is bonded on an insulating film 1. In such a TAB tape carrier, a thin copper plating 5 having the glossiness of 200 (measured by densitometer) or more, and grain size of 3mum or less is interstitially provided between the copper lead 2 and tin plating 4. A copper foil is laminated on the surface of the film tape 1 through an adhesive agent 3, and the copper lead 2 is formed by photoetching, for example. By a pulse plating method, an electric copper thin plating (in the thickness of 0.3 to 0.5mum) is provided for the copper lead 2 thereby to form the copper plating 5 having the glossiness of 200 or more and grain size 3mu or less on the surface of the copper lead 2. Then, by an electroless plating (temperature of plating solution: 60+ or -1 deg.C), the tin plating 4 of 0.5 to 1.0mum thick is formed on the surface of the copper plating 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、IC,LSI等の半導
体素子の実装方式の1つであるTAB(TapeAutomated
Boding)方式に使用されるTAB用テープキャリアに関
し、特に、耐ウィスカ性を大幅に向上させたTAB用テ
ープキャリアに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a TAB (Tape Automated) which is one of mounting methods for semiconductor elements such as IC and LSI.
The present invention relates to a TAB tape carrier used in the Boding method, and particularly to a TAB tape carrier having a significantly improved whisker resistance.

【0002】[0002]

【従来の技術】近年、半導体素子の実装技術の自動化,
及び高速化を図るため、長尺状のテープキャリアにワイ
ヤレスボンディングによりICやLSI等の半導体素子
を組み込んでゆくTAB(Tape Automated Bonding)方
式が採用されている。
2. Description of the Related Art In recent years, automation of semiconductor element mounting technology has been
Further, in order to increase the speed, a TAB (Tape Automated Bonding) method is adopted in which semiconductor elements such as ICs and LSIs are incorporated into a long tape carrier by wireless bonding.

【0003】図3には、従来のTAB用テープキャリア
の構成が示されている。テープキャリア10はポリイミ
ド,ポリエステル等からなる可撓性の絶縁性フィルムテ
ープ1の上に銅箔を接着し、フォトエッチングによって
アウターリード14,及びインナーリード15を有する
銅リード2を形成して成る。
FIG. 3 shows the structure of a conventional TAB tape carrier. The tape carrier 10 is formed by bonding a copper foil onto a flexible insulating film tape 1 made of polyimide, polyester or the like, and forming a copper lead 2 having an outer lead 14 and an inner lead 15 by photoetching.

【0004】フィルムテープ1は、IC,LSI等の半
導体素子(図示せず)を収容するためのデバイスホール
11と、フィルム搬送や位置決めを行うためのスプロケ
ットホール12と、電気信号を取り出すためのアウター
ホール13をパンチング加工によって形成することによ
り構成される。
The film tape 1 has a device hole 11 for accommodating semiconductor elements (not shown) such as IC and LSI, a sprocket hole 12 for carrying and positioning a film, and an outer for taking out electric signals. The hole 13 is formed by punching.

【0005】銅リード2は、フィルムテープ1の表面に
銅箔をラミネートし、この銅箔に感光性レジストを塗布
し、乾燥させた後所定のパターンのフォトマスクを通し
て露光し、更に、現像して所定のパターン形状のフォト
レジスト層を形成した後このフォトレジスト層をマスク
としてエッチングを行って形成される。
The copper lead 2 is obtained by laminating a copper foil on the surface of the film tape 1, applying a photosensitive resist to the copper foil, drying the copper foil, exposing it through a photomask having a predetermined pattern, and further developing it. It is formed by forming a photoresist layer having a predetermined pattern and then etching the photoresist layer as a mask.

【0006】このようにして銅リード2が形成される
と、デバイスホール11に半導体装置(ICチップ)を
配置し、ICチップ上に形成された微小の電極とテープ
上の対応するインナーリード15を、加熱したボンディ
ングツールにより熱圧着する。このとき、比較的低温で
接合できるようにするため、銅リードの表面に錫めっき
を施すようにしている。図4はこのような構成をもつテ
ープキャリア10の断面構造を示し、フィルムテープ1
に接着剤3を介して接着された銅リード2の表面に錫め
っき4が施されており、この錫めっき4とICチップの
電極に設けられたAuバンプが共晶接合されるようにな
っている。
When the copper lead 2 is formed in this manner, a semiconductor device (IC chip) is placed in the device hole 11, and the minute electrodes formed on the IC chip and the corresponding inner lead 15 on the tape are placed. , Thermocompression bonding with a heated bonding tool. At this time, tin plating is applied to the surface of the copper lead in order to enable bonding at a relatively low temperature. FIG. 4 shows a cross-sectional structure of the tape carrier 10 having such a structure, and the film tape 1
A tin lead 4 is applied to the surface of the copper lead 2 adhered to the via via an adhesive 3, and the tin plating 4 and the Au bump provided on the electrode of the IC chip are eutectic bonded. There is.

【0007】[0007]

【発明が解決しようとする課題】しかし、従来のTAB
用テープキャリアによると、銅リードの表面に施された
錫めっきからウィスカ(「ヒゲ」と称する針状結晶)が
発生し易い。この原因の一つとして、下地銅箔結晶粒の
サイズと錫めっき粒子のサイズの相違によって生じる界
面ゆがみ応力が考えられる。ウィスカは一度発生する
と、急速に成長する(室温放置で30〜40μm長/
月)ため、リード間の短絡不良事故を招く恐れがあり、
半導体装置としての信頼性を低下させる原因となってい
る。
However, the conventional TAB
According to the tape carrier for whiskers, whiskers (needle-shaped crystals called "beard") are easily generated from the tin plating applied to the surface of the copper lead. As one of the causes of this, the interface distortion stress caused by the difference in the size of the underlying copper foil crystal grains and the size of the tin-plated grains is considered. Once generated, whiskers grow rapidly (30-40 μm length /
Therefore, there is a risk of short-circuit failure between leads.
This causes a decrease in reliability as a semiconductor device.

【0008】従って、本発明の目的は耐ウィスカ性を向
上させ、半導体装置の信頼性を高めることができるTA
B用テープキャリアを提供することである。
Therefore, the object of the present invention is to improve the whisker resistance and the reliability of the semiconductor device TA.
A tape carrier for B is provided.

【0009】[0009]

【課題を解決するための手段】本発明は上記問題点に鑑
み、耐ウィスカ性を向上させて半導体装置の信頼性を高
めるため、銅リードと錫めっきの間に、光沢度200
(デジシトメーター測定)以上,粒形3μm以下の薄厚
の銅めっきを介在させたTAB用テープキャリアを提供
するものである。
In view of the above problems, the present invention has a gloss level of 200 between the copper lead and the tin plating in order to improve the whisker resistance and the reliability of the semiconductor device.
(Digisitometer measurement) As described above, the present invention provides a TAB tape carrier in which a thin copper plating having a grain shape of 3 μm or less is interposed.

【0010】前記銅リードは電解箔,或いは圧延箔より
構成される。銅リードの表面に施される銅めっきは、例
えば、パルスめっき方式により酸性銅めっき浴で厚さ
0.3〜0.5μmに形成され、このときの条件は平均
電流密度5A/dm2 ,周波数100Hz,デュティー
サークル10%とする。また、銅めっきの表面に施され
る錫めっきは、無電解めっき方式により酸性錫めっき浴
で厚さ0.5〜1.0μmに形成され、このときの条件
は液温60±1℃,浸漬時間4〜6分とする。
The copper lead is composed of electrolytic foil or rolled foil. The copper plating applied to the surface of the copper lead is formed by, for example, a pulse plating method in an acidic copper plating bath to a thickness of 0.3 to 0.5 μm. The conditions at this time are an average current density of 5 A / dm 2 and a frequency. 100Hz, 10% duty circle. Further, the tin plating applied to the surface of the copper plating is formed in a thickness of 0.5 to 1.0 μm in an acidic tin plating bath by an electroless plating method, and the conditions at this time are liquid temperature 60 ± 1 ° C. and immersion. The time is 4 to 6 minutes.

【0011】[0011]

【作用】上記構成を有する本発明のTAB用テープキャ
リアは、下地銅箔表面に薄く緻密な銅めっきを施してい
るため、錫めっき粒子との整合性を良好にすることがで
き、界面ゆがみ応力を低減し、導体パターンからのウィ
スカの発生を抑制することができる。
In the TAB tape carrier of the present invention having the above-mentioned structure, since the surface of the underlying copper foil is thinly and densely copper-plated, the compatibility with the tin-plated particles can be improved and the interface distortion stress can be improved. And the generation of whiskers from the conductor pattern can be suppressed.

【0012】[0012]

【実施例】以下、本発明のTAB用テープキャリアにつ
いて添付図面を参照しつつ詳細に説明する。
The tape carrier for TAB of the present invention will be described in detail below with reference to the accompanying drawings.

【0013】図1には、本発明の一実施例に係るTAB
用テープキャリア20の断面構造が示されており、図3
に示されるテープキャリア10と基本的構成とほぼ同一
のため重複する説明は省略する。このテープキャリア2
0は、フィルムテープ1の表面に接着剤3を介してラミ
ネートされた銅リード2と錫めっき4の間に、光沢度2
00(デジシトメーター測定)以上,粒形3μm以下の
薄厚の銅めっき5が介在させた構成を有している。
FIG. 1 shows a TAB according to an embodiment of the present invention.
The cross-sectional structure of the tape carrier 20 is shown in FIG.
Since the tape carrier 10 shown in FIG. 6 has substantially the same basic structure as that of FIG. This tape carrier 2
0 indicates a glossiness of 2 between the copper lead 2 and the tin plating 4 which are laminated on the surface of the film tape 1 via the adhesive 3.
It has a configuration in which a thin copper plating 5 having a grain shape of 3 μm or less is interposed between 00 (measured by a digital cytometer).

【0014】上記テープキャリア10は、フィルムテー
プ1の表面に接着剤3を介して銅箔をラミネートし、こ
の銅箔に前述したフォトエッチング(感光性レジストの
塗布し、露光,現像等によってパターンを焼付後、エッ
チングする)を行って、フィルムテープ1の表面に銅リ
ード2を形成し、パルスめっき方式により銅リード2に
電気銅薄めっき(厚さ0.3〜0.5μm)を行い、銅
リード2の表面に光沢度200(デジシトメーター測
定)以上,粒形3μm以下の銅めっき5を形成し、無電
解めっき(めっき液温60±1℃)によって銅めっき5
の表面に厚さ0.5〜1.0μmの錫めっき4を形成す
るという各工程を経て製造される。
In the tape carrier 10, a copper foil is laminated on the surface of the film tape 1 via an adhesive 3, and the copper foil is subjected to the above-mentioned photo-etching (application of a photosensitive resist, exposure and development to form a pattern). After baking, etching is performed) to form the copper leads 2 on the surface of the film tape 1, and thin copper electroplating (thickness 0.3 to 0.5 μm) is performed on the copper leads 2 by the pulse plating method. On the surface of the lead 2, a copper plating 5 with a gloss of 200 (measured by a digisisitometer) or more and a grain shape of 3 μm or less is formed, and the copper plating 5 is applied by electroless plating (plating solution temperature 60 ± 1 ° C.)
It is manufactured through each step of forming a tin plating 4 having a thickness of 0.5 to 1.0 μm on the surface of.

【0015】次に、このようにして得られたテープキャ
リア20と、従来のテープキャリア10を、室温,40
℃,及び65℃/95%湿度雰囲気下で保管して錫ウィ
スカの発生,及びその成長についてそれぞれ観察した。
なお、40℃,65℃/95%湿度の条件は、過去の実
験,文献,及び半導体実装品の信頼度の内容を考慮し、
ウィスカの発生,成長を促進させる条件として選択し
た。
Next, the tape carrier 20 thus obtained and the conventional tape carrier 10 are placed at room temperature and 40
Generation of tin whiskers and growth thereof were observed after storage in an atmosphere of 65 ° C. and a humidity of 65 ° C./95%.
Note that the conditions of 40 ° C. and 65 ° C./95% humidity are set in consideration of past experiments, literatures, and reliability of semiconductor mounted products.
It was selected as a condition to promote the generation and growth of whiskers.

【0016】図2は上記実験結果を示し、本発明のテー
プキャリア20の室温保管における1ヶ月経過後のウィ
スカ長は10μm以下であり、従来のテープキャリア1
0に比べて1/3〜1/4に低減することが判る。ま
た、40℃,及び65℃/95%湿度の条件についても
本発明のテープキャリア20は、従来のテープキャリア
10に比してウィスカの成長が確実に低減されている判
る。
FIG. 2 shows the above experimental results. The whisker length of the tape carrier 20 of the present invention after storage for one month in room temperature storage is 10 μm or less.
It can be seen that it is reduced to 1/3 to 1/4 as compared with 0. Also, under the conditions of 40 ° C. and 65 ° C./95% humidity, it is found that the tape carrier 20 of the present invention surely reduces the growth of whiskers as compared with the conventional tape carrier 10.

【0017】このように本発明は、銅リード2と錫めっ
き4の間に銅めっき5を介在させることにより、導体パ
ターンの耐ウィスカ性を向上させることができる。これ
は、銅リード2の表面に薄く緻密な銅めっき5を設けて
錫めっき5の粒子との整合性を良好にすることによって
界面ゆがみ応力を低減したことに起因している。
As described above, according to the present invention, by interposing the copper plating 5 between the copper lead 2 and the tin plating 4, the whisker resistance of the conductor pattern can be improved. This is because the thin and dense copper plating 5 is provided on the surface of the copper lead 2 to improve the compatibility with the particles of the tin plating 5 to reduce the interface distortion stress.

【0018】[0018]

【発明の効果】以上説明したように、本発明のTAB用
テープキャリアによると、銅リードと錫めっきの間に、
光沢度200(デジシトメーター測定)以上,粒形3μ
m以下の薄厚の銅めっきを介在させたため、導体パター
ンの耐ウィスカ性を向上させることができ、リード間の
短絡不良事故を防いで半導体装置の信頼性を高めること
ができる。
As described above, according to the TAB tape carrier of the present invention, between the copper lead and the tin plating,
Gloss level 200 (measured by digisistometer) or more, grain shape 3μ
Since the thin copper plating having a thickness of m or less is interposed, the whisker resistance of the conductor pattern can be improved, a short-circuit failure between leads can be prevented, and the reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すテープキャリアの断面
図。
FIG. 1 is a sectional view of a tape carrier showing an embodiment of the present invention.

【図2】錫ウィスカの成長を表すグラフ。FIG. 2 is a graph showing the growth of tin whiskers.

【図3】従来のテープキャリアを示す説明図。FIG. 3 is an explanatory view showing a conventional tape carrier.

【図4】従来のテープキャリアを示す断面図。FIG. 4 is a sectional view showing a conventional tape carrier.

【符号の説明】[Explanation of symbols]

1 フィルムテープ 2
銅リード 3 接着剤 4
錫めっき 5 銅めっき 10
テープキャリア 11 デバイスホール 12
スプロケットホール 13 アウターホール 14
アウターリード 15 インナーリード
1 film tape 2
Copper lead 3 Adhesive 4
Tin plating 5 Copper plating 10
Tape carrier 11 Device hole 12
Sprocket hole 13 Outer hole 14
Outer lead 15 Inner lead

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁フィルム上に接着された所定パター
ンの銅リードの表面に、錫めっきを施して成るTAB用
テープキャリアにおいて、 前記銅リードと前記錫めっきの間に、光沢度200(デ
ジシトメーター測定)以上,粒形3μm以下の薄厚の銅
めっきを介在させたことを特徴とするTAB用テープキ
ャリア。
1. A tape carrier for TAB, which is obtained by applying tin plating to the surface of a copper lead having a predetermined pattern adhered on an insulating film, wherein a gloss level of 200 (digitisite) is provided between the copper lead and the tin plating. A tape carrier for TAB, characterized in that a thin copper plating having a grain shape of 3 μm or less is interposed.
JP35793291A 1991-12-26 1991-12-26 Tab tape carrier Pending JPH05183016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35793291A JPH05183016A (en) 1991-12-26 1991-12-26 Tab tape carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35793291A JPH05183016A (en) 1991-12-26 1991-12-26 Tab tape carrier

Publications (1)

Publication Number Publication Date
JPH05183016A true JPH05183016A (en) 1993-07-23

Family

ID=18456681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35793291A Pending JPH05183016A (en) 1991-12-26 1991-12-26 Tab tape carrier

Country Status (1)

Country Link
JP (1) JPH05183016A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004339605A (en) * 2003-05-12 2004-12-02 Rohm & Haas Electronic Materials Llc Improved tin-plating method
CN100373568C (en) * 2003-12-29 2008-03-05 三星电机株式会社 Method of forming bump pad of flip chip and structure thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004339605A (en) * 2003-05-12 2004-12-02 Rohm & Haas Electronic Materials Llc Improved tin-plating method
JP4603812B2 (en) * 2003-05-12 2010-12-22 ローム・アンド・ハース・エレクトロニック・マテリアルズ,エル.エル.シー. Improved tin plating method
CN100373568C (en) * 2003-12-29 2008-03-05 三星电机株式会社 Method of forming bump pad of flip chip and structure thereof

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