JPH05182581A - Field emission type electron emission source element - Google Patents

Field emission type electron emission source element

Info

Publication number
JPH05182581A
JPH05182581A JP34720291A JP34720291A JPH05182581A JP H05182581 A JPH05182581 A JP H05182581A JP 34720291 A JP34720291 A JP 34720291A JP 34720291 A JP34720291 A JP 34720291A JP H05182581 A JPH05182581 A JP H05182581A
Authority
JP
Japan
Prior art keywords
electrode layer
insulating layer
layer
insulating
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34720291A
Other languages
Japanese (ja)
Other versions
JP2846988B2 (en
Inventor
Masao Urayama
雅夫 浦山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP34720291A priority Critical patent/JP2846988B2/en
Publication of JPH05182581A publication Critical patent/JPH05182581A/en
Application granted granted Critical
Publication of JP2846988B2 publication Critical patent/JP2846988B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Cold Cathode And The Manufacture (AREA)

Abstract

PURPOSE:To reduce dispersion of characteristics of a field emission type electron emission source element and reduce the operating voltage of the element by laying a first insulating layer, a first electrode layer, a second insulating layer and a second electrode layer in sequence on a substrate, and providing a groove which passes through the layers from the first insulating layer to the second electrode layer. CONSTITUTION:A first insulating layer 11, a first field application electrode layer 12, a second insulating layer 13, an electron emitting electrode layer 14, a third insulating layer 15, a second field application electrode layer 16 and an insulating portion 17 are laid on a silicon substrate 10 in that order. Each of the insulating layers is formed of silicon dioxide and each of the electrode layers is formed of tungsten. Further, a groove passing through all of the layers separates two multilayer portions from each other. The insulating portion 17 is so formed to cover the first insulating layer 11, the first field application electrode layer 12, the second insulating layer 13, the electron emitting electrode layer 14, the third insulating layer 15 and the second field application electrode layer 16 except portions of the layers which face the groove 18. Therefore, the thin film of each of the layers can be uniformly formed with good reproducibility while film thickness is ontrolled. Since the distance between the first and second electrode layers can be controlled by the film thickness of the second insulating layer, operating voltage can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電界放出の原理により
電子を放出する電界放出型電子放出源素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission type electron emission source device which emits electrons according to the principle of field emission.

【0002】[0002]

【従来の技術】電界放出型の陰極構造を有する集積型真
空管は、例えば、シー.エー.スピント(C.A.Spindt)
等の米国特許第3、789、471号によって公知であ
る。これらのデバイスの素子構成は、電子放出部である
陰極と、陰極に電界を印加し陰極より電子を放出させる
役割を有するゲート電極とを基本としている。電界放出
型陰極において、その動作電圧を低下させる一つの手段
としては、陰極に印加される実効的な電界強度を大きく
するために陰極、ゲート電極間の距離を小さくすること
が挙げられる。現在、広く知られている素子は、シー.
エー.スピント(C.A.Spindt)等の米国特許第3、78
9、471号や、エイチ.エフ.グレイ(H. F. Gray)
等の米国特許第4、307、507号に見られる構造を
採用している。
2. Description of the Related Art An integrated vacuum tube having a field emission type cathode structure is disclosed in, for example, C.I. A. Spinto (CASpindt)
U.S. Pat. No. 3,789,471. The element structure of these devices is basically based on a cathode which is an electron emitting portion and a gate electrode which has a role of applying an electric field to the cathode to emit electrons from the cathode. In the field emission type cathode, one means for reducing the operating voltage is to reduce the distance between the cathode and the gate electrode in order to increase the effective electric field strength applied to the cathode. At present, a widely known element is C.I.
A. US Patent 3,783 to CASpindt et al.
9, 471 and H. F. Gray (HF Gray)
Employs the structure found in U.S. Pat. No. 4,307,507.

【0003】図7に、シー.エー.スピント(C.A.Spin
dt)等によって提案された基本的な電界放出型電子放出
源素子の構成図を示す。
Referring to FIG. A. Spinto (CASpin
FIG. 3 is a block diagram of a basic field emission type electron emission source device proposed by dt) and the like.

【0004】この電界放出型電子放出源素子は、円錐形
状の電子放出部である陰極33が、金属又は半導体材料
で形成された基板電極30の上に形成され、陰極33の
周辺の基板電極30の上には絶縁層31を挟んでゲート
電極32が積層されている。このような構成において、
陰極33とゲート電極32との間に電圧を印加すると、
その間に高電界が発生し、電界放出の原理によって陰極
33の先端より電子が放出される。
In this field emission type electron emission source device, a cathode 33 which is a cone-shaped electron emission portion is formed on a substrate electrode 30 formed of a metal or a semiconductor material, and the substrate electrode 30 around the cathode 33 is formed. A gate electrode 32 is stacked on top of the insulating layer 31. In such a configuration,
When a voltage is applied between the cathode 33 and the gate electrode 32,
During that time, a high electric field is generated, and electrons are emitted from the tip of the cathode 33 according to the principle of field emission.

【0005】次に、この素子の製造工程について図8を
参照して説明する。
Next, the manufacturing process of this element will be described with reference to FIG.

【0006】同図(A)に示すように、半導体(例えば
シリコン)基板30の表面に絶縁層31a(例えば二酸
化シリコンSiO2 )、ゲート電極層32aを順次形成
する。次に、図8(B)に示すようにゲート電極層32
a上にレジストを塗布し、そのレジスト膜に所望するパ
ターンを焼き付け、現像処理を行い、レジストパターン
を設け、所定の領域のみゲート電極層を露出させる。こ
の後、表面に露出したゲート電極層32aと絶縁層31
aとを順次エッチング等の手段によって除去すると、図
8(C)に示す微小のアパーチャ35が半導体基板上に
形成される。そしてアパーチャ35に対して垂直に金属
材料を蒸着することによって、図8(D)に示すように
アパーチャ径の縮小とともに電子放出部である円錐形状
の陰極33が半導体基板30の上に形成される。ゲート
電極32の面上に残留している金属層33aをリフトオ
フ法によって除去し、また、レジスト層34を除去する
ことによって図8(E)に示す電界放出型電子放出源素
子が得られる。通常、この電界放出型電子放出源素子
は、アレイ状に複数個同一基板上に形成される。
As shown in FIG. 1A, an insulating layer 31a (eg, silicon dioxide SiO 2 ) and a gate electrode layer 32a are sequentially formed on the surface of a semiconductor (eg, silicon) substrate 30. Next, as shown in FIG. 8B, the gate electrode layer 32
A resist is applied on a, a desired pattern is baked on the resist film, a developing process is performed, a resist pattern is provided, and the gate electrode layer is exposed only in a predetermined region. Then, the gate electrode layer 32a and the insulating layer 31 exposed on the surface are formed.
When a and a are sequentially removed by means such as etching, the minute apertures 35 shown in FIG. 8C are formed on the semiconductor substrate. Then, by evaporating a metal material perpendicularly to the apertures 35, a conical cathode 33 serving as an electron emitting portion is formed on the semiconductor substrate 30 as the aperture diameter is reduced, as shown in FIG. .. By removing the metal layer 33a remaining on the surface of the gate electrode 32 by the lift-off method and removing the resist layer 34, the field emission type electron emission source device shown in FIG. 8E is obtained. Usually, a plurality of field emission type electron emission source elements are formed in an array on the same substrate.

【0007】[0007]

【発明が解決しようとする課題】この種の構造におい
て、陰極とゲート電極との距離は、初期のレジストパタ
ーンに設けられた穴の大きさにより決定される。このた
め、複数個の電子放出源素子を再現性良く、均一に作製
するには、リソグラフィ工程、エッチング工程の精度を
上げる必要がある。しかし、これらの技術は装置性能に
大きく左右される上に、その制御は容易ではない。即
ち、微細化に伴う陰極形状や陰極とゲート電極間距離の
ばらつきによる各素子毎の電子放出特性のばらつきは製
造上避けることができないという問題点がある。また、
現状技術の範囲内においてアパーチャの直径及び陰極の
高さは最小で1μm程度が製造上の限界であるため、陰
極とゲート電極間距離は容易に縮めることができないの
で、動作電圧(陰極とゲート電極間の電圧)の低減化は
困難である。
In this type of structure, the distance between the cathode and the gate electrode is determined by the size of the holes formed in the initial resist pattern. Therefore, in order to manufacture a plurality of electron emission source elements with good reproducibility and uniformly, it is necessary to improve the accuracy of the lithography process and the etching process. However, these techniques are greatly influenced by the device performance, and their control is not easy. That is, there is a problem that variations in the electron emission characteristics of each element due to variations in the cathode shape and the distance between the cathode and the gate electrode due to miniaturization cannot be avoided in manufacturing. Also,
Within the scope of the state of the art, the minimum diameter of the aperture and the height of the cathode are about 1 μm at the manufacturing limit. Therefore, the distance between the cathode and the gate electrode cannot be easily shortened. It is difficult to reduce the voltage).

【0008】従って、本発明は、特性のばらつきが小さ
く、動作電圧が小さい電界放出型電子放出源素子を提供
するものである。
Therefore, the present invention provides a field emission type electron emission source device having a small variation in characteristics and a small operating voltage.

【0009】[0009]

【課題を解決するための手段】本発明によれば、基板
と、該基板上に積層された第1の絶縁層と、該第1の絶
縁層の上に積層された第1の電極層と、該第1の電極層
の上に積層された第2の絶縁層と、該第2の絶縁層の上
に積層された第2の電極層と、第1の絶縁層と第1の電
極層と第2の絶縁層と第2の電極層とを貫通しており、
電子放出空間としての溝とを備えた電界放出型電子放出
源素子が提供される。
According to the present invention, a substrate, a first insulating layer laminated on the substrate, and a first electrode layer laminated on the first insulating layer are provided. A second insulating layer laminated on the first electrode layer, a second electrode layer laminated on the second insulating layer, a first insulating layer and a first electrode layer And penetrating the second insulating layer and the second electrode layer,
A field emission type electron emission source device having a groove as an electron emission space is provided.

【0010】[0010]

【作用】例えば、第1の電極層に電圧V1、第2の電極
層に電圧V2を、V1>V2になるように印加すると、
電界放出の原理に基づいて第2の電極層から電子が放出
される。また、例えば、溝によって分割された第1の絶
縁層と第1の電極層と第2の絶縁層と第2の電極層とか
ら成る2つの積層部のうちの一つの積層部の第1の電極
層に電圧V1、第2の電極層に電圧V2を、溝を隔てた
もう一つの積層部の第2の電極層に電圧V3を、V1>
V2、V3>V2となるように印加すると、電界放出の
原理に基づいて第2の電極層から電子が放出され、電圧
V3を印加した第2の電極層が陽極として動作する三極
管となる。
For example, when voltage V1 is applied to the first electrode layer and voltage V2 is applied to the second electrode layer so that V1> V2,
Electrons are emitted from the second electrode layer based on the principle of field emission. Further, for example, the first laminated layer of one of the two laminated layers composed of the first insulating layer, the first electrode layer, the second insulating layer, and the second electrode layer divided by the groove The voltage V1 is applied to the electrode layer, the voltage V2 is applied to the second electrode layer, and the voltage V3 is applied to the second electrode layer of the other laminated portion separated by the groove, V1>
When applied so that V2 and V3> V2, electrons are emitted from the second electrode layer based on the principle of field emission, and the second electrode layer to which the voltage V3 is applied becomes a triode that operates as an anode.

【0011】[0011]

【実施例】本発明による電界放出型電子放出源素子の実
施例について図面を参照して説明する。
Embodiments of the field emission type electron emission source device according to the present invention will be described with reference to the drawings.

【0012】図1は本発明に係る電界放出型電子放出源
素子の一実施例の断面図、図2は図1の素子の平面図、
図3は図2のB−B線の素子断面図である。尚、図1は
図2のA−A線の断面図である。
FIG. 1 is a sectional view of an embodiment of a field emission type electron emission source device according to the present invention, FIG. 2 is a plan view of the device of FIG.
FIG. 3 is a sectional view of the element taken along the line BB in FIG. 1 is a sectional view taken along the line AA of FIG.

【0013】図1に示すように、シリコン基板10上に
は二酸化シリコンから成る第1の絶縁層11、タングス
テン(W)で形成された第1の電界印加用電極層12、
二酸化シリコンから成る第2の絶縁層13、タングステ
ンで形成された電子放出用電極層14、二酸化シリコン
から成る第3の絶縁層15、タングステンで形成された
第2の電界印加用電極層16、及び絶縁部17がこの順
番で積層されている。さらに、第1の絶縁層11、第1
の電界印加用電極層12、第2の絶縁層13、電子放出
用電極層14、第3の絶縁層15、第2の電界印加用電
極層16、及び絶縁部17を貫通する溝が、第1の絶縁
層11、第1の電界印加用電極層12、第2の絶縁層1
3、電子放出用電極層14、第3の絶縁層15、第2の
電界印加用電極層16、及び絶縁部17から成る2つの
積層部を隔てている。また、絶縁部17は、第1の絶縁
層11、第1の電界印加用電極層12、第2の絶縁層1
3、電子放出用電極層14、第3の絶縁層15及び第2
の電界印加用電極層16から成る部分を図2及び図3に
示すように溝18に面する部分を除いて覆うように形成
されている。
As shown in FIG. 1, on a silicon substrate 10, a first insulating layer 11 made of silicon dioxide, a first electric field applying electrode layer 12 made of tungsten (W),
A second insulating layer 13 made of silicon dioxide, an electron emission electrode layer 14 made of tungsten, a third insulating layer 15 made of silicon dioxide, a second electric field applying electrode layer 16 made of tungsten, and The insulating portion 17 is laminated in this order. Further, the first insulating layer 11, the first
The groove penetrating the electric field applying electrode layer 12, the second insulating layer 13, the electron emitting electrode layer 14, the third insulating layer 15, the second electric field applying electrode layer 16, and the insulating portion 17 of First insulating layer 11, first electric field applying electrode layer 12, second insulating layer 1
3, two layered portions including the electron emission electrode layer 14, the third insulating layer 15, the second electric field applying electrode layer 16, and the insulating portion 17 are separated from each other. The insulating portion 17 includes the first insulating layer 11, the first electric field applying electrode layer 12, and the second insulating layer 1.
3, the electrode layer 14 for electron emission, the third insulating layer 15, and the second
2 is formed so as to cover the part formed of the electric field applying electrode layer 16 except the part facing the groove 18 as shown in FIGS.

【0014】このような、微小間隔の溝18を隔てて対
向した積層構造において、電子放出部である電子放出用
電極層14に電圧V1、電界印加用電極である第1の電
界印加用電極層12及び第2の電界印加用電極層16に
電圧V2を、V1<V2になるように印加すると、電界
放出の原理に基づき電子放出用電極層14の先端部から
電子放出が起こる。また、電子放出部である電子放出用
電極層14に電圧V1、電界印加用電極である第1の電
界印加用電極層12及び第2の電界印加用電極層16に
電圧V2、溝18を隔てた電子放出用電極層14と対向
する電子放出用電極層14と同一の材料を有する積層で
ある電極層14bに電圧V3を、V1<V2、V1<V
3となるように印加すると、電子放出用電極層14は陰
極、第1の電界印加用電極層12及び第2の電界印加用
電極層16はゲート電極、電極層14bは陽極として動
作するため、三極管としての機能を付加することができ
る。尚、この場合、溝18によって隔てられた電極層1
2b及び16bには電圧を印加しない。しかし、電極層
14bと同様に、電極層12b及び16bに電圧V3程
度の電圧を印加することによって陽極として動作させる
ことも可能である。
In such a laminated structure facing each other with the grooves 18 having a minute interval, a voltage V1 is applied to the electron emitting electrode layer 14 which is an electron emitting portion, and a first electric field applying electrode layer which is an electric field applying electrode. When the voltage V2 is applied to 12 and the second electric field applying electrode layer 16 so that V1 <V2, electrons are emitted from the tip of the electron emitting electrode layer 14 based on the principle of field emission. Further, the voltage V1 is applied to the electron emission electrode layer 14 which is the electron emission portion, the voltage V2 is applied to the first electric field application electrode layer 12 and the second electric field application electrode layer 16 which are the electric field application electrodes, and the groove 18 is separated. The voltage V3 is applied to the electrode layer 14b, which is a laminate made of the same material as the electron emission electrode layer 14 facing the electron emission electrode layer 14, and V1 <V2, V1 <V.
When applied so as to be 3, the electron emitting electrode layer 14 operates as a cathode, the first electric field applying electrode layer 12 and the second electric field applying electrode layer 16 operate as gate electrodes, and the electrode layer 14b operates as an anode. A function as a triode can be added. In this case, the electrode layer 1 separated by the groove 18
No voltage is applied to 2b and 16b. However, like the electrode layer 14b, it is also possible to operate as an anode by applying a voltage of about voltage V3 to the electrode layers 12b and 16b.

【0015】次に、図を参照して上記実施例の電界放出
型電子放出源素子の製造方法について説明する。
Next, a method of manufacturing the field emission type electron emission source device of the above embodiment will be described with reference to the drawings.

【0016】図4は、図1に示した本実施例による電界
放出型電子放出源素子の側面断面図を用いて示す電界放
出型電子放出源素子の製造工程図であり、図5は、図3
に示した本実施例による電界放出型電子放出源素子の側
面断面図を用いて示す電界放出型電子放出源素子の製造
工程であり、図6は、本実施例による電界放出型電子放
出源素子の製造工程を示す平面図である。尚、図4から
図6の各図はそれぞれ対応している。
FIG. 4 is a manufacturing process drawing of the field emission type electron emission source device shown by using a side sectional view of the field emission type electron emission source device according to this embodiment shown in FIG. 1, and FIG. Three
FIG. 6 is a manufacturing process of the field emission type electron emission source device shown in the side sectional view of the field emission type electron emission source device according to the present example shown in FIG. FIG. 6 is a plan view showing a manufacturing process of. The drawings in FIGS. 4 to 6 correspond to each other.

【0017】シリコン(Si)基板10上に、第1の絶
縁層となる二酸化シリコン層11a、第1の電界印加用
電極層となるタングステン層12a、第2の絶縁層とな
る二酸化シリコン層13a、電子放出用電極層となるタ
ングステン層14a、第3の絶縁層となる二酸化シリコ
ン層15a、第2の電界印加用電極層となるタングステ
ン層16aを、この順番でスパッタリング装置によって
堆積し、タングステン層16a表面にレジスト膜19を
スピンナによって塗布する。これによって製造された積
層構造を図4(A)、図5(A)及び図6(A)に示
す。この際、絶縁層となる二酸化シリコン層11a、1
3a及び15aの厚さは0.3〜0.5μm程度,電極
層となるタングステン層12a、14a及び16aの厚
さは0.2〜0.4μm程度の範囲で堆積する。この
後、レジスト膜にパターンの焼き付けを行い、図5
(B)及び図6(B)に示すようなレジストパターン1
9aを得る。
On a silicon (Si) substrate 10, a silicon dioxide layer 11a which becomes a first insulating layer, a tungsten layer 12a which becomes a first electric field applying electrode layer, a silicon dioxide layer 13a which becomes a second insulating layer, A tungsten layer 14a that serves as an electron emission electrode layer, a silicon dioxide layer 15a that serves as a third insulating layer, and a tungsten layer 16a that serves as a second electric field applying electrode layer are deposited in this order by a sputtering apparatus to form the tungsten layer 16a. A resist film 19 is applied on the surface by a spinner. The laminated structure manufactured by this is shown in FIG. 4 (A), FIG. 5 (A) and FIG. 6 (A). At this time, the silicon dioxide layers 11a and 1 to be the insulating layers
The thickness of 3a and 15a is about 0.3 to 0.5 .mu.m, and the thickness of the tungsten layers 12a, 14a and 16a to be electrode layers is about 0.2 to 0.4 .mu.m. After that, a pattern is printed on the resist film, and the pattern shown in FIG.
A resist pattern 1 as shown in FIGS. 6B and 6B.
9a is obtained.

【0018】レジストパターン作製後露出した積層した
各層から成るエッジ部分をドライエッチング法によって
エッチングしたものが図5(C)及び図6(C)であ
る。エッチング処理を施した後、スパッタリング装置に
よって二酸化シリコン膜17aを0.3〜0.5μm程
度の厚さで、タングステン層16a及び基板10の表面
全体に形成した。これを示したものが図4(D),図5
(D)及び図6(D)である。以上の工程は、素子動作
時エッジ部分での電気的絶縁性を保持するために行う。
これらの工程が終了した後、電子放出部分作製のための
工程に移る。まず、図4(E),図5(E)及び図6
(E)に示すようにレジストを用いて所望するレジスト
パターン20を二酸化シリコン膜17a表面に形成す
る。次に、露出させた部分をドライエッチング法によっ
て順次基板面までエッチングを行い、図4(F)及び図
6(F)に示すような溝18が形成された構造を得る。
この後、表面に残っているレジストパターン20をアッ
シングで除去して図4(G),図5(G)及び図6
(G)に示す電界放出型電子放出源素子を得る。
FIG. 5C and FIG. 6C are views in which the edge portion formed of the laminated layers exposed after the formation of the resist pattern is etched by the dry etching method. After performing the etching process, a silicon dioxide film 17a having a thickness of about 0.3 to 0.5 μm was formed on the entire surface of the tungsten layer 16a and the substrate 10 by a sputtering device. This is shown in FIG. 4 (D) and FIG.
6D and FIG. 6D. The above steps are performed in order to maintain the electrical insulation at the edge portion during the operation of the device.
After these steps are completed, the step for producing an electron emitting portion is started. First, FIG. 4 (E), FIG. 5 (E) and FIG.
As shown in (E), a desired resist pattern 20 is formed on the surface of the silicon dioxide film 17a using a resist. Next, the exposed portion is sequentially etched to the surface of the substrate by a dry etching method to obtain a structure in which the groove 18 is formed as shown in FIGS. 4 (F) and 6 (F).
After that, the resist pattern 20 remaining on the surface is removed by ashing to remove the resist pattern 20 shown in FIGS.
A field emission type electron emission source element shown in (G) is obtained.

【0019】このように、上記した製造方法によって本
実施例による電界放出型電子放出源素子は製造されるの
で、膜厚を制御しながら電極層及び絶縁層の薄膜を均一
にかつ再現性良く形成することができる。また、本素子
の構造では、第1の電極層と第2の電極層との距離が中
間層である第2の絶縁層の膜厚で制御可能であるので、
動作電圧の低減化を達成することも可能である。
As described above, since the field emission type electron emission source device according to the present embodiment is manufactured by the above manufacturing method, the thin films of the electrode layer and the insulating layer are uniformly and reproducibly formed while controlling the film thickness. can do. Further, in the structure of this element, since the distance between the first electrode layer and the second electrode layer can be controlled by the film thickness of the second insulating layer which is the intermediate layer,
It is also possible to achieve a reduction in operating voltage.

【0020】本実施例では、1つの素子のみを示した
が、通常、この電界放出型電子放出源素子は、アレイ状
に複数個同一基板上に形成される。また、電極材料にタ
ングステンを用いたがこれに限られるものではなく、モ
リブデン(Mo)等の他の金属を使用しても同様な構造
の電極を実現できる。
In this embodiment, only one element is shown, but normally, a plurality of field emission type electron emission source elements are formed in an array on the same substrate. Further, although tungsten is used as the electrode material, the present invention is not limited to this, and an electrode having a similar structure can be realized by using another metal such as molybdenum (Mo).

【0021】[0021]

【発明の効果】以上説明したように、本発明による電界
放出型電子放出源素子は、基板と、該基板上に積層され
た第1の絶縁層と、該第1の絶縁層の上に積層された第
1の電極層と、該第1の電極層の上に積層された第2の
絶縁層と、該第2の絶縁層の上に積層された第2の電極
層と、第1の絶縁層と第1の電極層と第2の絶縁層と第
2の電極層とを貫通しており、電子放出空間としての溝
とを備えたので、膜厚を制御しながら各層の薄膜を均一
にかつ再現性良く形成することができる。また、本素子
の構造では、第1の電極層と第2の電極層との距離が中
間層である第2の絶縁層の膜厚で制御可能であるので、
動作電圧の低減化を達成することも可能である。
As described above, the field emission type electron emission source device according to the present invention includes a substrate, a first insulating layer laminated on the substrate, and a first insulating layer laminated on the first insulating layer. A first electrode layer, a second insulating layer laminated on the first electrode layer, a second electrode layer laminated on the second insulating layer, a first insulating layer Since the insulating layer, the first electrode layer, the second insulating layer, and the second electrode layer are penetrated, and the groove as the electron emission space is provided, the thin film of each layer is made uniform while controlling the film thickness. And can be formed with good reproducibility. Further, in the structure of this element, since the distance between the first electrode layer and the second electrode layer can be controlled by the film thickness of the second insulating layer which is the intermediate layer,
It is also possible to achieve a reduction in operating voltage.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る電界放出型電子放出源素子の一実
施例の要部断面図である。
FIG. 1 is a sectional view of an essential part of an embodiment of a field emission type electron emission source device according to the present invention.

【図2】本発明に係る電界放出型電子放出源素子の一実
施例の要部平面図である。
FIG. 2 is a plan view of an essential part of an embodiment of a field emission type electron emission source device according to the present invention.

【図3】図2のB−B線の断面図である。3 is a sectional view taken along line BB of FIG.

【図4】図1に示した本実施例による電界放出型電子放
出源素子の側面断面図を用いて示す電界放出型電子放出
源素子の製造工程図である。
FIG. 4 is a manufacturing process diagram of the field emission type electron emission source element shown by using the side sectional view of the field emission type electron emission source element according to the present embodiment shown in FIG.

【図5】図3に示した本実施例による電界放出型電子放
出源素子の側面断面図を用いて示す電界放出型電子放出
源素子の製造工程図である。
5A and 5B are manufacturing process diagrams of the field emission type electron emission source device shown by using a side sectional view of the field emission type electron emission source device according to the present embodiment shown in FIG.

【図6】図2に示した本実施例による電界放出型電子放
出源素子の平面図を用いて示す電界放出型電子放出源素
子の製造工程図である。
FIG. 6 is a manufacturing process diagram of the field-emission electron emission source device shown by using the plan view of the field-emission electron emission source device according to the present embodiment shown in FIG. 2;

【図7】従来の縦型電界放出型電子放出源素子の要部断
面図である。
FIG. 7 is a cross-sectional view of a main part of a conventional vertical field emission type electron emission source device.

【図8】従来の縦型電界放出型電子放出源素子の製造工
程図である。
FIG. 8 is a manufacturing process diagram of a conventional vertical field emission electron emission source device.

【符号の説明】[Explanation of symbols]

10 シリコン基板 11 第1絶縁層 12 第1電界印加用電極層 13 第2絶縁層 14 電子放出用電極層 15 第3絶縁層 16 第2電界印加用電極層 17 絶縁部 18 溝 10 Silicon Substrate 11 First Insulating Layer 12 First Electric Field Applying Electrode Layer 13 Second Insulating Layer 14 Electron Emitting Electrode Layer 15 Third Insulating Layer 16 Second Electric Field Applying Electrode Layer 17 Insulating Part 18 Groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板と、該基板上に積層された第1の絶
縁層と、該第1の絶縁層の上に積層された第1の電極層
と、該第1の電極層の上に積層された第2の絶縁層と、
該第2の絶縁層の上に積層された第2の電極層と、前記
第1の絶縁層と前記第1の電極層と前記第2の絶縁層と
前記第2の電極層とを貫通しており、電子放出空間とし
ての溝とを備えたことを特徴とする電界放出型電子放出
源素子。
1. A substrate, a first insulating layer laminated on the substrate, a first electrode layer laminated on the first insulating layer, and a first electrode layer on the first electrode layer. A laminated second insulating layer,
A second electrode layer laminated on the second insulating layer, the first insulating layer, the first electrode layer, the second insulating layer, and the second electrode layer are penetrated. And a field-emission electron emission source element having a groove as an electron emission space.
JP34720291A 1991-12-27 1991-12-27 Field emission type electron emission element Expired - Lifetime JP2846988B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34720291A JP2846988B2 (en) 1991-12-27 1991-12-27 Field emission type electron emission element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34720291A JP2846988B2 (en) 1991-12-27 1991-12-27 Field emission type electron emission element

Publications (2)

Publication Number Publication Date
JPH05182581A true JPH05182581A (en) 1993-07-23
JP2846988B2 JP2846988B2 (en) 1999-01-13

Family

ID=18388615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34720291A Expired - Lifetime JP2846988B2 (en) 1991-12-27 1991-12-27 Field emission type electron emission element

Country Status (1)

Country Link
JP (1) JP2846988B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591345B1 (en) * 1998-02-17 2006-06-19 소니 가부시끼 가이샤 Electron Emission Device and Production Method Of the Same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01300558A (en) * 1988-05-27 1989-12-05 Agency Of Ind Science & Technol Cold electron emission type active element and manufacture thereof
JPH0340332A (en) * 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd Electric field emitting type switching element and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01300558A (en) * 1988-05-27 1989-12-05 Agency Of Ind Science & Technol Cold electron emission type active element and manufacture thereof
JPH0340332A (en) * 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd Electric field emitting type switching element and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591345B1 (en) * 1998-02-17 2006-06-19 소니 가부시끼 가이샤 Electron Emission Device and Production Method Of the Same

Also Published As

Publication number Publication date
JP2846988B2 (en) 1999-01-13

Similar Documents

Publication Publication Date Title
CA2034481C (en) Self-aligned gate process for fabricating field emitter arrays
US5821132A (en) Method for fabricating a field emission device having reduced row-to-column leakage
JP3060928B2 (en) Field emission cathode and method of manufacturing the same
JPH06162919A (en) Field emission cold cathode element
JPH05182581A (en) Field emission type electron emission source element
JPH03295131A (en) Electric field emission element and manufacture thereof
JPH0612974A (en) Electron emitting element
JPH04206123A (en) Electron emission element and its manufacture
JP2000243240A (en) Manufacture of field emission type cathode equipped with focusing electrode
JPH0652788A (en) Field emission type electron source device and its manufacture
JPH0785779A (en) Manufacture of field emitting element array
JPH05242797A (en) Manufacture of electron emission element
JP2737675B2 (en) Manufacturing method of vertical micro cold cathode
KR100569264B1 (en) Method of manufacturing field emission display device
JP2636630B2 (en) Field emission device and method of manufacturing the same
JPH07282720A (en) Manufacture of electron emission source
JPH03295130A (en) Electron emission device
JPH11162326A (en) Field electron-emission element
JPH1031956A (en) Manufacture of field emission cathode with convergence electrode
KR100278502B1 (en) Manufacturing method of volcanic metal FEA with double gate
JP2001143602A (en) Field emission type cold cathode and method of fabricating the same
JPH0794083A (en) Field emitting cathode and its manufacture
KR100279749B1 (en) Manufacturing method of field emission array superimposed gate and emitter
JPH10149762A (en) Manufacture of field emission type element
KR100286479B1 (en) Method for manufacturing diamond triple electrode field emitter

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071030

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081030

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081030

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091030

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091030

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101030

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111030

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121030

Year of fee payment: 14

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121030

Year of fee payment: 14