JPH05182464A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide an inexpensive semiconductor storage device with little hard quantity on the semiconductor storage device having plural writing and reading ports. CONSTITUTION:This device has a multi-port for executing in parallel write and read processing by plural writing and reading ports. This device is provided with a first data latch part 11 capable of accessing directly by inputting an address from the outside and second data latch parts 12-1k of at least one or more providing communication means 41-4k communicating with the first data latch part 11, and is constituted so as to access an optional one of the first data latch part 11 and the second data latch part 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a semiconductor memory device having a plurality of write and read ports. 2. Description of the Related Art In recent years, as semiconductor technology has advanced, the speed of data processing devices has increased, and arithmetic processing devices (processors) capable of parallel arithmetic processing have also been provided. Along with that, a semiconductor memory device (for example, a multi-port SRAM) having a plurality of write ports and read ports has been developed, but the amount of hardware is large and the cost is high. Therefore, it is desired to provide a low-cost semiconductor memory device with a small amount of hardware.

[0002]

2. Description of the Related Art A recent processor is generally equipped with an instruction fetch unit, an instruction decode unit, an operation execution unit (ALU), a register file, etc., and executes an instruction by a pipeline operation. Conventionally, only one arithmetic execution unit is provided in the processor, and in that case, the register file is composed of a semiconductor memory device (for example, SRAM) having two read / one write ports. The semiconductor memory device having the two read / one write ports can efficiently perform a three address format operation such as an addition instruction.

In recent years, processors have been adopting parallel processing formats such as VLIW (Very Long Instruction Word) and Superscalar in order to enable high-speed processing. A processor using these formats includes a plurality of arithmetic units, and further a semiconductor memory device having a large number of read / write ports for exchanging data with the plurality of arithmetic units (for example, It has a multi-port SRAM). Generally, 2n read ports and n write ports are required for n arithmetic units.

By the way, a processor architecture having a plurality of local register files is known in order to perform a subroutine call at a high speed. In this method, a large number of local register files are assigned to each subroutine. A register file is needed. The register file of this format is configured by using a plurality of 2-read / 1-write semiconductor memory devices, for example.

FIG. 10 is a block diagram showing an example of a conventional semiconductor memory device. As shown in FIG. 10A, a conventional semiconductor memory device having a plurality of read / write ports (n read / m write ports) has m data ports for one data latch unit (memory cell) 311. Write selection switch means (write control transfer gate) 321-
32 m are provided, and n lead selection switch means (read control transfer gates) 331 to 33 n are provided.

Then, as shown in FIG. 10B, the register file has k storage devices (n read / m write memory) 301 to 30k, and is configured to be selected by the selector 305. There is. As described above, the register file of the processor adopting the conventional parallel processing format and the local register format (the number of local registers is generally k) has m write ports (write ports) and n write ports.
It is configured to include k n read / m write memories having book read ports (read ports).

FIG. 11 is a circuit diagram showing a part of an SRAM having 4 read / 2 write ports in the conventional semiconductor memory device having n read / m write ports shown in FIG. 10A. is there. As shown in FIG. 11, the SRAM having 4 read / 2 write ports has one SRA.
Two write control transfer gates 321 and 322 and four read control transfer gates 331 to 334 are provided for the M cell 311. here,
The gates of the write control transfer gates 321 and 322 are connected to the write word lines WL ₀ and WL _{1 and} are source (drain).
Is connected to the write bit lines BL ₀ and BL ₁ , the drain (source) is commonly connected to the SRAM cell 311, and the write selected according to the level of the write word lines WL ₀ and WL _1. Write ports WP ₀ , WP supplied via the bit lines BL ₀ , BL ₁ for
The data of ₁ is supplied to the SRAM cell 311. In addition, the transfer control transfer gates 331 to 33
The gate of 4 is connected to the read word lines WL _{2 to} WL ₅ , and the source (drain) is commonly connected to the SRAM cell 311.
The drain (source) is connected to the read bit lines BL _{2 to} BL ₅ , and the read bit lines BL _{2 to} BL which select the data of the SRAM cell 311 according to the level of the read word lines WL _{2 to} WL _5. It is designed to output to predetermined read ports RP ₀ to RP ₃ via ₅ .

[0008]

As described above, FIG.
The conventional semiconductor memory device (register file) having a plurality of read / write ports shown in 0 is a local register (n having n write ports and n read ports).
Read / m write memory) is provided, and the amount of hardware is ((n read / m write memory) × k +
Selector) capacity is required. Therefore, a multi-port semiconductor memory device or a processor having the semiconductor memory device is expensive.

That is, as shown in FIG. 11, in the conventional SRAM having four read / two write ports, one memory cell 311 is provided with two write control transfer gates 321 and 322. Input ports are connected, and four input ports are connected via four read control transfer gates 331 to 334. Therefore, in this case, one memory cell 311
6 transistors (transfer gate 32
1,322; 331,332,333,334), and the amount of hardware required for a large number of memory cells 311 is large.

In view of the problems of the conventional semiconductor memory device described above, an object of the present invention is to provide a low-cost semiconductor memory device with a small amount of hardware.

[0011]

According to the present invention, a semiconductor having a multiport for executing write and read processes in parallel by a plurality of write and read ports WP ₀ , WP ₁ ; RP _{0 to} RP _5. A first data latch unit which is a memory device and can be directly accessed by inputting an address from the outside.
11; 111; 211 and at least one second data latch including communication means 41-4k, 5; 41-44, 51-54; 221a, 221b, 222, 223 for communicating with the first data latch unit. Part 12-
1k; 112 to 11k; 212, 213, wherein any one of the first data latch unit and the second data latch unit is accessed. ..

[0012]

According to the semiconductor memory device of the present invention, the first memory can be directly accessed by inputting an address from the outside.
The data latch unit 11; 111; 211 to the communication means 41 to
4k, 5; 41-44, 51-54; 221a, 221b, 222, 223, at least one or more second data latch portions 12-1k; 112-11
k; 212,213 are connected. The first data latch unit 11; 111; 211 and the second data latch unit 12-1k; 1
Any one of 12 to 11k; 212, 213 is to be accessed.

As a result, it is possible to provide a low-priced semiconductor memory device by reducing the amount of hardware with respect to the memory capacity.

[0014]

Embodiments of the semiconductor memory device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. As shown in the figure, in the semiconductor memory device of the present embodiment having a plurality of read / write ports (n read / m write ports), m is set for a plurality of data latch units (memory cells) 11 to 1k. The write selection switch means (write control transfer gates) 21 to 2m are provided, and the n read selection switch means (readout control transfer gates) 31 to 3n are provided.

In the semiconductor memory device of this embodiment, a first data latch unit 11 that can be directly accessed by inputting an address from the outside, and a plurality of data latch units arranged in parallel to the first data latch unit 11 are provided. Second data latch units 12 to 1k. Each of the first and second data latch sections 11 to 1k is provided with switch means (data latch section selecting transfer gate) 41 to 4k and a selector 5, respectively. A selection signal SS is supplied to each of the switch means 41 to 4k and the selector 5 so that any one of the first and second data latch sections 11 to 1k is selected and accessed.

Here, in the semiconductor memory device of this embodiment, any one can be selected from the first and second data latch sections 11 to 1k by the selection signal SS.
The contents of memory cells that can be directly accessed by inputting an address from the outside can be replaced according to the specification of the local register file. That is, the local register file is assigned to each data latch unit 11 to 1k, and the switch means 41 to
By the 4k and the selector 5, a plurality of data latch units 11-
Only one target data latch unit can be selected from 1k.

FIG. 2 is a block diagram of the semiconductor memory device of FIG.
FIG. 3 is a circuit diagram showing a part of SRAM having a read / 2 write port, and FIG. 3 is a circuit diagram showing a configuration in which four memory cells of FIG. 2 are connected. As shown in FIG. 2, in the SRAM of this embodiment, four SRAM cells 11 ...
Two transfer gates 2 for 14 write control
Transfer gate 3 for 1,22 and 4 read controls
1 to 34 are provided and configured. Where each SRA
The M cells 11 to 14 are respectively provided with transfer gates 41 to 44 for selecting a data latch portion on the write side, and transfer gates 51 to 51 for selecting a data latch portion on the read side.
54 is provided. Then, the transfer gates 41 to 44 and 51 to 54 for selecting the data latch section are controlled by the selection signal SS, whereby the SRAM cell
Any one of 11 to 14 is selected.
The circuit of FIG. 3 shows a configuration in which four memory cells having the four SRAM cells (data latch units) 11 to 14 shown in FIG. 2 are arranged in a matrix form. The cells are arranged in a matrix. Further, in FIG. 3, reference numeral SL ₀ to SL _3, the transfer gates 41 to 44 and data latch unit selection
These are signal lines for supplying selection signals SS _{1 to} SS ₄ to 51 to 54.

In the semiconductor memory device shown in FIG. 2, the gates of the write control transfer gates 21 and 22 are connected to the write word lines WL ₀ and WL ₁ , and the source (drain) is the write bit line BL _0. , BL ₁ , and the drains (sources) are commonly connected to the sources (drains) of the transfer gates 41 to 44 for selecting the data latch unit. Then, write ports WP ₀ , WP supplied via the write bit lines BL ₀ , BL ₁ selected according to the levels of the write word lines WL ₀ , WL _1.
The data of ₁ is supplied to the SRAM cells 11 to 14 selected by the transfer gates 41 to 44 for selecting the data latch section controlled by the selection signals SS _{1 to} SS ₄ . The gates of the read control transfer gates 31 to 34 are connected to the read word lines WL _{2 to} WL ₅ , and the sources (drains) thereof are commonly connected to the drains of the data latch selection transfer gates 51 to 54. , The drain (source) is connected to the read bit lines BL _{2 to} BL ₅ . Then, the data of the SRAM cells 11 to 14 selected by the transfer gates 51 to 54 for selecting the data latch section controlled by the selection signals SS _{1 to} SS ₄ are transferred in accordance with the levels of the read word lines WL _{2 to} WL _5. Selected read bit line
It outputs data to predetermined read ports RP ₀ to RP ₃ via BL _{2 to} BL ₅ .

Comparing the SRAM shown in FIG. 2 described above with that of FIG. 11 described above, in the conventional SRAM having 4 read / 2 write ports, one memory cell 311 is provided.
6 transistors (transfer gate 32
1,322; 331,332,333,334) are required, in the case of this embodiment, four memory cells 11,12,13,1
14 transistors for 4 (transfer gate
21,22; 31,32,33,34; 41,42,43,44; 51,52,53,54) are required. Therefore, in the case of the present embodiment, in the data latch section (memory cell section),
Since 3.5 (14/4) transistors will suffice, the amount of hardware of an SRAM having the same capacity of SRAM can be reduced.

FIG. 4 is a block diagram showing the overall structure of the semiconductor memory device of the present invention. In the figure, reference numerals
Reference numeral 100 is a selection register, 200 is a row address decoder, and 300 is a column address decoder and a sense amplifier. As shown in FIG. 4, the address signal is supplied to the row address decoder 200 and the column address decoder and sense amplifier 300,
Also, the selection data is supplied to the selection register 100,
Write word lines WL ₀ and WL ₁ and read word lines WL _{2 to} WL
_The transfer gates 21, 22; 31 to 34 are controlled by ₅ and the transfer gates 41 to 44; 51 to 54 for selecting the data latch section are controlled by the selection signals SS (SS _{1 to} SS ₄ ).
Data is exchanged between the write ports WP ₀ and WP ₁ and the read ports RP ₀ to RP ₃ .

FIG. 5 is a block diagram showing an example of a selection signal generating circuit used in the semiconductor memory device of the present invention. In the figure, reference numerals 621 to 624 are selectors, 631 to 634 are registers, and 61 is an AND gate. In the selection signal generating circuit shown in FIG. 5, the shift enable signal SE is supplied to one input of the AND gate 61, and the clock signal CLK is inverted and supplied to the other input of the AND gate 61. Further, the output of the AND gate 61 is supplied to the clock terminals (CLK) of the registers 631 to 634, and the shift control signal SCS is supplied to the selectors 621 to 624.
Is being supplied to. The output of each selector 621 to 624 is the data input terminal (D) of the corresponding register 631 to 634.
Is also supplied to the output of registers 631,632,633,634
(Q) is used as the selection signals SS _{1 to} SS _{4 to} select transfer gates 41 to 44; 51 to 54 (FIGS. 2 and 3).
Reference selector) 621, 622,
623,624 one input (S1) and the next stage selector 622,62
It is supplied to the other input (S2) of 3,624,621. Here, the selectors 621 to 624 are two AND gates 6211 and 62.
12 and an OR gate 6213.

The selection signal generating circuit shown in FIG.
When the enable signal SE is high level "H", the selection signal SS₁
~ SS_FourAre sequentially shifted, and SRAM cells 11 to 14 are sequentially selected
It is supposed to be done. That is, shift enable
Signal SE is high level "H" and shift control signal SCS
Is high level "H", for example, the selection signal SS₁~ SS _Four
Are sequentially shifted, and the SRAM cells are rotated clockwise (11 → 12 →
13 → 14 → 11 →…) Selected. Also, shift enable
Signal SE is high level "H" and shift control signal SCS
Is low level "L", for example, the selection signal SS₁~ SS_Four
Sequentially shifts and the SRAM cell moves counterclockwise (11 → 14
→ 13 → 12 → 11 →…) It is designed to be selected. one
On the other hand, when the shift enable signal SE is at low level "L",
Selection signal SS₁~ SS_FourWill not shift.

FIG. 6 is a block diagram showing another example of the selection signal generating circuit used in the semiconductor memory device of the present invention. In the figure, reference numeral 400 indicates a selection signal decoder,
Select signal SS ₁ by decoding the specified bit of the address signal
~ It is designed to generate SS ₄ . In the example shown in FIG. 6, of the address signals ADO to ADj, 2-bit address signals (AD0, AD1) are used to generate the selection signals SS _{1 to} SS ₄ , and the remaining address signals AD3 to ADj are normally used. The address signal is supplied to the register file 1.

FIG. 7 is a block diagram showing a main part of an example of an arithmetic processing device using the semiconductor memory device having the configuration of FIG. In the figure, reference numeral 1 is a register file, 2 and 3 are ALUs (arithmetic units), 100 is a selection register, 101 is an instruction decoding unit, and 102 is an instruction fetch unit. Here, register file 1 is 4
It is configured as a read / 2 write memory (SRAM) and is used as a register file of the arithmetic processing unit.

As shown in FIG. 7, two data read from the register file 1 are stored in the ALU 2 via the read bit lines (BL ₂ , BL ₃ ) and the read ports (RP ₀ , RP ₁ ). The two data supplied to the ALU 3 and read from the register file 1 are also read bit lines (BL ₄ , B
L ₅ ) and read ports (RP ₂ , RP ₃ ). Furthermore, the output of ALU2 is supplied to the register file 1 via the write port (WP ₀ ) and the write bit line (BL ₀ ), and the output of ALU3 is used for the write port (WP ₁ ) and write. It is supplied to the register file 1 via the bit line (BL ₁ ). That is, the two data read from the register file 1 are supplied to the ALUs 2 and 3, respectively, and the results calculated by the ALUs 2 and 3 are stored again in the register file 1.

FIG. 8 is a block diagram showing another embodiment of the semiconductor memory device of the present invention. Here, in the above-described embodiment (see FIG. 2), the plurality of data latch units 11 to 1k are connected in parallel, and any one data latch unit is randomly selected by the selection signal SS. However, as shown in FIG. 8, in the semiconductor memory device of the present embodiment, the first data latch unit 111 which can be directly accessed by inputting an address from the outside and the first data latch unit 111 are connected in parallel to each other. A plurality of second provided in
The data latch units 112 to 11k are connected in series by a communication means (not shown), for example, the clock signal CL.
Data is sequentially shifted by K (for example, shifted counterclockwise) to access any one of the first and second data latch units 111 to 11k. Specifically, when reading the data stored in the data latch unit 113, the data stored in the data latch unit 113 is shifted to the data latch unit 111 via the data latch unit 112 by the two clock signals CLK, Then, the shifted data is read out to the data latch unit 111. When writing data, the data latch unit 111
After writing predetermined data in, the data is sequentially shifted.

FIG. 9 is a block diagram showing a specific example of the semiconductor memory device of FIG. As shown in Fig. 9 (a), multiple read / write ports (n read / m write ports)
In the semiconductor memory device having the above, two data latch units 2 are provided for one data latch unit (memory cell) 211.
12 and 213 are provided, and the data latch unit 211,
Switch means (shift control transfer gates) 221a, 221b, 222, 223 for serially connecting the 212, 213 are provided. Here, in this embodiment, the data stored in the data latch units 211, 212, 213 can be shifted in both clockwise and counterclockwise directions. Further, each of the data latch units 211 to 213 is, for example, D
Type flip-flops, and the transfer control transfer gates 221a, 221b, 222, 223.
Can be composed of, for example, an N-type MOS transistor. In this embodiment, a 3-bit memory cell (data latch unit) is provided, but a k-bit memory cell may be provided as necessary to sequentially shift data. Further, controlling the data shift is not limited to the clock signal CLK.

Then, as shown in FIG. 9B, the register file has n read / read cells having k memory cells.
It will consist of only m light x k memory 500.
That is, by applying this embodiment, a semiconductor memory device (n lead / m 2 having the same capacity as that of FIG.
The write memory 301 to 30k) can be configured only with n read / m write xk memory 500, and the amount of hardware can be significantly reduced. Here, the semiconductor memory device can be divided into two parts, a memory cell array part and a peripheral part (decoder, buffer, selector, sense amplifier, etc.). By applying the present invention, the number of local register files (k ), Only the memory cell array part depends on the number of local register files, so the increase in the amount of hardware with respect to the number of local register files is reduced compared to the conventional example (for example, 50% or less of the increase in the amount of hardware in the conventional example. ) Is possible.

As described above, according to the semiconductor memory device of the present embodiment, it is possible to reduce the hardware amount of the register file of the processor which employs the parallel processing format and the local register format, which is a specific target of use. In particular, the increase in the amount of hardware when a plurality of local register files are provided can be significantly reduced.

[0030]

As described above in detail, according to the semiconductor memory device of the present invention, the first data latch unit and at least one second data latch unit having the communication means are provided. By accessing any one of the first data latch unit and the second data latch unit, the hardware amount of the register file of the processor adopting the parallel processing format and the local register format can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is 4 leads / 2 to which the semiconductor memory device of FIG. 1 is applied.
It is a circuit diagram which shows a part of SRAM which has a write port.

FIG. 3 is a circuit diagram showing a configuration in which four memory cells of FIG. 2 are connected.

FIG. 4 is a block diagram showing an overall configuration of a semiconductor memory device of the present invention.

FIG. 5 is a block diagram showing an example of a selection signal generating circuit used in the semiconductor memory device of the present invention.

FIG. 6 is a block diagram showing another example of a selection signal generating circuit used in the semiconductor memory device of the present invention.

7 is a block diagram showing a main part of an example of an arithmetic processing device using the semiconductor memory device having the configuration of FIG. 2;

FIG. 8 is a block diagram showing another embodiment of the semiconductor memory device of the present invention.

9 is a block diagram showing a specific example of the semiconductor memory device of FIG.

FIG. 10 is a block diagram showing an example of a conventional semiconductor memory device.

11 is a circuit diagram showing a part of SRAM having 4 read / 2 write ports to which the semiconductor memory device of FIG. 10 is applied.

[Explanation of symbols]

1 ... Register file (memory) 2, 3 ... ALU (arithmetic unit) 11; 111; 211 ... First data latch unit 12-1k; 112-11k; 212,213 ... Second data latch unit 41-4k, 5; 41 ~ 44, 51 ~ 54; 221, 222a, 222b, 223 ... communication means

Claims (5)

[Claims] 1. A plurality of write and read ports (WP ₀ , WP ₁ ;
A semiconductor memory device having a multi-port that executes writing and reading processes in parallel by RP _{0 to} RP ₅ ) and is directly accessible by inputting an address from the outside. 211) and communication means for communicating with the first data latch unit (41-4k, 5; 41-4
4, 51-54; 221a, 221b, 222, 223) at least 1
One or more second data latch units (12 to 1k; 112 to 11k; 212,
213) and the first data latch unit and the second data latch unit.
2. A semiconductor memory device, characterized in that any one of the data latch units is accessed. 2. The write and read ports are write control transfer gates (21 to 2 m; 21,22; 121, respectively).
~ 12m) and transfer control transfer gate (31 ~ 3
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is adapted to be connected to the first data latch section (11; 111) via n; 31-34; 131-13n). 3. The communication means comprises a shift control transfer gate (221a, 221b, 222, 223) for connecting the first and second data latch sections (211; 212, 213) in series, and a clock supplied from the outside. 2. The semiconductor memory device according to claim 1, wherein data is sequentially shifted according to a signal (CLK) to access any one of the first and second data latch units. 4. The first communication means is connected in parallel.
And a plurality of transfer gates (41-44; 51-54) for selecting the data latch section provided on the write side and the read side for the second data latch section (11; 12-14), respectively. The selection signals (SS; SS _{1 to} SS ₄ ) are supplied to the plurality of transfer gates for selecting the data latch unit and the _first signal is supplied.
2. An arbitrary one of the second data latch section and the second data latch section are selected and accessed.
Semiconductor memory device. 5. An arithmetic processing device comprising a register file (1) and a plurality of arithmetic execution units (2, 3) for executing arithmetic operations in parallel, wherein the register file receives an address from the outside. First data latch unit that can be directly accessed by
(11; 111; 211) and communication means for communicating with the first data latch unit (41-4k, 5; 41-44, 51-54; 221a, 221b, 222, 22)
3) at least one or more second data latch section having
(12 to 1k; 112 to 11k; 212, 213), wherein any one of the first data latch unit and the second data latch unit is accessed. ..