JPH05181779A - External storage control device - Google Patents

Abstract

PURPOSE:To determine the transfer starting time of transfer between a channel equipment and a buffer memory so that the held time of transfer data in the buffer memory is set up to minimum time required by forecasting time required for data transfer between the channel equipment and the buffer memory to which a command chaining time (CCT) is added in the data transfer control of an external storage control device. CONSTITUTION:When data transfer constitutes a command chain consisting of plural channel commands, a timer 44 counts up a command chaining time from a specific channel command obtained before the start of data transfer to the succeeding channel command and a transfer starting time determining part 45 regards the counted command chaining time as an individual command chaining time, forecasts the total of the command chaining times and adds the forecasted time to the time required for the data transfer between the channel equipment 3 and the buffer memory 5 to determine the data transfer starting time between the equipment 3 and the memory 5. Thereby the using rate of the memory 5 can be suppressed to a minimum rate required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention minimizes the time that transfer data stays in an internal buffer memory.
The present invention relates to an external storage control device capable of improving total throughput.

[0002]

2. Description of the Related Art In data transfer between a channel device and an external storage device, a buffer memory is generally incorporated in an external storage control device for controlling the external storage device, and data transfer is generally performed through this buffer memory. Target.

There are various purposes for using the buffer memory, but the most basic purpose is to absorb a constant or temporary difference in data transfer capacity between the channel device and the external storage device. .. The buffer memory for this purpose literally plays a role as a buffer mechanism in data transfer. That is, for example, in the data output process, the data transferred from the channel device is temporarily stored in the buffer memory and then transferred from the buffer memory to the external storage device. The storage of data in the buffer memory is performed prior to the transfer to the external storage device by an amount necessary to absorb the difference in the data transfer capability between the channel device and the external storage device. Then, after the transfer to the external storage device is completed, the buffer memory is released and the data stored in the buffer memory is not reused.

In particular, when the difference in the data transfer capability between the channel device and the external storage device is constant, the external storage control device determines the time during which the transfer data stays in the buffer memory, that is, the buffer memory. The time from the start of use to the release should be controlled to the minimum required. This is because a plurality of external storage devices are usually connected under the external storage control device, and in such a connection configuration, the buffer memory is shared and used in data transfer to the plurality of external storage devices. Is realistic. Therefore, the usage rate of the buffer memory is
This is because there is a high possibility of becoming a bottleneck for the total throughput in such a connection configuration.
In particular, when the external storage device is a disk device, it is usual that a plurality of disk devices are accessed almost simultaneously and frequently. Therefore, the above control is particularly important.

An ideal form of the above control will be described below with reference to FIG.

Here, the processing capability of the data transfer source (the channel device in the data output process, the external storage device in the data input process) is lower than the processing capability of the data transfer destination, that is, the data to the buffer memory. It is assumed that the time Ts required for the transfer is longer than the time Tf required for the data transfer from the buffer memory. The ideal form in this case is to control so that the end times of Ts and Tf are almost the same, as shown in FIG.

A method of realizing the above control is disclosed in, for example, Japanese Patent Laid-Open No.
2-92022 and JP-A-2-109121. The former is a data input process in the configuration where the processing capacity of the external storage device is low, and the latter is
In the data output processing in the configuration in which the processing capacity of the channel device is low, the above control is achieved by calculating Ts and Tf in advance and advancing the start timing of Ts by the time T (= Ts-Tf). Is disclosed.

Now, consider a case where a plurality of records continuously recorded in the external storage device should be input / output by one input / output instruction. On the storage medium of the external storage device, individual records are recorded with a gap of a length peculiar to the device. If the external storage device is a CKD (count key data) type disk device that is widely used in large-scale computer systems, a channel command for instructing the data transfer is consecutive for each individual record. Is issued from the channel device to the disk control device (called a command chain).

That is, as shown in FIG.
And Tf are not only the times Tsx and Tfx required to actually transfer the data of the individual records, but also the time Tsg required for the data head of the disk device to pass through the gap on the storage medium and the external storage control. It includes the time (command chaining time) Tfg from when the device reports the processing end status for one channel command until the next channel command is issued to the external storage controller. In addition, in FIG. 4, R1, R
It illustrates the case where three consecutive records of 2 and R3 are to be transferred.

[0010]

The techniques disclosed in the above-mentioned two publications are all related to the above-mentioned Tsg and Tfg,
In particular, it does not mention the existence of command chaining time. This is because the ratio of command chaining time to Ts and Tf was relatively small in a typical computer system configuration at that time.

However, as the performance of the channel device and the external storage device is improved year by year, the time required for the data transfer itself tends to decrease, while the command chaining time tends to increase. For example, for the purpose of making it relatively easy to secure the installation place of the computer system, the interface means between the channel device and the control device is controlled by using an optical signal instead of a conventional electric signal. It has been devised to dramatically increase the distance to the device.

Since the command chaining time includes a signal propagation time on the interface, that is, a time element proportional to the distance between the channel device and the control device, it increases with the distance extension. Therefore, the ratio of the command chaining time to Ts and Tf increases exponentially. That is, the techniques disclosed in the above two publications have a problem that the original purpose cannot be achieved in such a situation.

In view of the above problems, an object of the present invention is to add the command chaining time to the data transfer time to the buffer memory, so that the command chaining time is added even under the above-mentioned circumstances.
An object of the present invention is to provide an external storage control device that can achieve the original purpose.

[0014]

In order to achieve the above object, the present invention intervenes between a channel device and an external storage device to temporarily transfer data transferred between the channel device and the external storage device. Has a buffer memory for storing, the time required for data transfer between the channel device and the buffer memory,
And, by predicting the time required to transfer data between the external storage device and the buffer memory, the transfer data stays in the buffer memory for a minimum time,
In an external storage control device having a deciding means for deciding a data transfer start time between a channel device and a buffer memory, when the data transfer forms a command chain consisting of a plurality of channel commands, between individual channel commands Is provided with a predicting unit for predicting the total command chaining time of
Start the data transfer between the channel device and the buffer memory by adding the total command chaining time predicted by the prediction means to the time required for the data transfer between the channel device and the buffer memory. I try to decide when.

The predicting means is provided with a measuring means for measuring the command chaining time from a specific channel command before the start of data transfer to the next channel command, and the command chaining time measured by the measuring means is calculated. The total command chaining time can be predicted by regarding each command chaining time and multiplying the command chaining time by the number obtained by subtracting 1 from the number of channel commands.

The predicting means calculates the command chaining time by referring to the setting means for externally setting the interface cable length with the channel device and the interface cable length set by the setting means. By calculating the command chaining time calculated by the calculating means as an individual command chaining time, and multiplying the command chaining time by a number obtained by subtracting 1 from the number of channel commands. , The total command chaining time can be predicted.

[0017]

The command chain used for data input / output includes at least two specific channel commands before the channel command for initiating the data transfer. For example, in a disk device, Japanese Unexamined Patent Publication No. 62-92022.
DEFINE EXT
The ENT command and the LOCATE command are sequentially included. On the other hand, the command chaining time depends on the interface cable length and the processing capability of the channel device, but hardly on the channel commands before and after the command chaining.

Therefore, the command chaining time from the DEFINE EXTENT command to the LOCATE command can be measured, and the measured command chaining time can be regarded as individual command chaining time.

Also, in many installations, the interface cable length between the channel device and the external storage controller is laid out in a planned manner. Further, in command chaining, the number of signals traveling through the interface cable and the propagation time of the signals are always constant.

Therefore, the interface cable length is used as preset information at the time of installation, for example,
It can be set by the laying operator, and the command chaining time can be calculated from the set interface cable length, and the calculated command chaining time can be regarded as individual command chaining time.

Then, the time obtained by multiplying each command chaining time by "the number of commands-1" is added to the result of predicting the time required for the data transfer between the channel device and the buffer memory as in the conventional case. This makes it possible to easily predict the time required for data transfer including the command chaining time.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a computer system using an external storage controller according to an embodiment of the present invention. In this embodiment, since the disk device 6 is used as the external storage device, the external storage control device is the disk control device 4.

In FIG. 2, the computer system comprises a processing device 1, a main storage device 2, a channel device 3, a disk control device 4, and a disk device 6. The channel device 3 and the disk control device 4 are connected by an interface cable 7. Further, the disk control device 4 has a buffer memory 5 built therein.

FIG. 1 is a block diagram of the disk controller 4.

1, in addition to the buffer memory 5 shown in FIG. 1, the disk controller 4 includes a command decoding section 40, a DEFINE EXTENT processing section 41, and a LOC.
It is composed of an ATE processing unit 42, a data transfer command processing unit 43, a timer 44, a transfer start timing determination unit 45, a channel reconnection requesting unit 46, and a disk device positioning unit 47.

Command decoding unit 40, DEFINE EX
TENT processing unit 41, LOCATE processing unit 42, data transfer command processing unit 43, transfer start timing determination unit 45, channel reconnection request unit 46, disk device positioning unit 47
Is a functional block realized by a micro program executed by a microprocessor (not shown) incorporated in the disk control device 4, and the timer 44 is a hardware counter that advances in fixed cycles.

The above-mentioned measuring means corresponds to the timer 44,
The determining means corresponds to the transfer start timing determining unit 45.

In the following, data output processing in the disk controller 4 when the processing capacity of the channel device 3 is lower than that of the disk device 6, that is, data transfer from the channel device 3 to the buffer memory 5 is buffered. For data transfer from the memory 5 to the disk device 6,
The operation in the process that should be started earlier by the time T will be described. In the following description, as shown in FIG. 4, the process of continuously outputting the records R1 to R3 is taken as an example.

Prior to issuing the input / output instruction, the processing unit 1
Creates a command chain 20 and a command parameter 21 in the main storage device 2 using a known technique, as shown in FIG. The command chain 20 and the command parameter 21 are taken out from the main storage device 2 by the channel device 3 and sequentially sent to the disk control device 4.

The disk control unit 4 discriminates the command sent from the channel unit 3 by the command decoding unit 40 and determines the DEFINE EXTEN corresponding to the command.
The T processing unit 41, the LOCATE processing unit 42, and the data transfer command processing unit 43 are activated.

Here, since the first command sent is the DEFINE EXTENT command, the DEFINE EXTENT processing section 41 is first activated. The DEFINE EXTENT processing unit 41 performs predetermined command processing (omitted because it is not related to the present invention).
Then, the timer 44 is reset to zero, and at the same time, the completion status of the command is reported to the channel device 3.

When the channel device 3 receives the end status, it sends the next channel command, LOCATE.
The command chaining is performed on the command, and the LOCATE command is sent to the disk controller 4, and the command decoding unit 4
0 starts the LOCATE processing unit 42 in the same manner as above.

The LOCATE processing unit 42 first reads and stores the current contents of the timer 44. The timer 44 is
As described above, the DEFINE EXTENT processing unit 4
Since it was reset at the time of reporting the end status by 1, the current contents of the timer 44 is DEFINE EX.
The command chaining time from the TENT command to the LOCATE command is shown. Although the command chaining time depends on the cable length of the interface cable 7 and the processing capability of the channel device 3, it hardly depends on the channel commands before and after the command chaining. Therefore, in the present embodiment, the DEFINE EXTENT command is used. The command chaining time to the LOCATE command is regarded as the individual command chaining time Tsg.

The LOCATE processing unit 42 subsequently receives the command parameter 21 from the channel device 3. The command parameter 21 is, as shown in FIG. 5, the position of R1 (specified by the track address and record number on the storage medium of the disk device 6), the number N of records to be output (in this case, "3"). )), R1 to R3
The average record length L is included. After that, LOC
The ATE processing unit 42 activates the transfer start time determination unit 45. At this time, the LOCATE processing unit 42 determines the number of records N, the average record length L, and the command chaining time Ts.
g is transferred to the transfer start time determination unit 45.

The transfer start timing determining unit 45 calculates the time Ts required to transfer R1 to R3 from the channel device 3 to the buffer memory 5 and the time required to transfer R1 to R3 from the buffer memory 5 to the disk device 6 according to the following equations. Predict Tf.

Ts = NL / Vc + (N-1) Tsg Tf = NL / Vd + (N-1) Tfg where Vc is the data transfer rate of the channel device 3, and Vd
Is the data transfer rate of the disk device 6, Tfg is the gap time between records in the disk controller 6, and
In any case, the transfer start time determination unit 45
Can be obtained as a known value.

From the above equation, the transfer start timing determining unit 45
Can easily calculate the time T (= Ts−Tf) at which the data transfer from the channel device 3 to the buffer memory 5 should be started prior to the data transfer from the buffer memory 5 to the disk device 6.

The disk controller 4 disconnects the logical connection with the channel device 5 until the data transfer start time, and when the data transfer start time is reached, logically reconnects with the channel device 3. Then, the operation of starting the data transfer (receiving the data output command) is generally performed. The channel reconnection request unit 46 executes the reconnection with the channel device 3.

Therefore, by activating the channel reconnection request unit 46 at a time T minutes before the completion time of the positioning of the disk device 6 to R1 (data head seek and rotation wait), the channel is reconnected for the time T. It is possible to realize the operation of starting data transfer from the device 3 to the buffer memory 5 in advance.

At the above time, the channel reconnection request unit 4
The operation of activating 6 can be realized by using some known techniques, and is not particularly specified in this embodiment.
For example, in the case of using the SET SECTOR operation of the disk device 6 as disclosed in Japanese Patent Laid-Open No. 62-92022, the transfer start timing determination unit 45 positions the SET SECTOR operation such that it is completed at the above time. Command to the disk device 6 via the unit 47,
The channel reconnection request unit 46 is activated upon the completion report of the SET SECTOR operation from the disk device 6. Further, the channel reconnection request unit 46 may be configured to be activated at the above time by a known programming technique that activates a desired process at a desired time.

In the above embodiment, the data output processing in the case where the processing capacity of the channel device 3 is lower than the processing capacity of the disk device 6 has been described.
The present invention can be easily applied to the data input processing in which the processing capacity of is lower than the processing capacity of the channel device 3. The difference from the above description is that first, the data transfer from the disk device 6 to the buffer memory 5 is started, and the time T
It only activates the channel reconnection request unit 46 later. It should be noted that the data output process or the data input process is specified by the command parameter 21, so that the LOCATE processing unit 42 can easily identify it.

In the above embodiment, the command chaining time Tsg is measured by using the timer 44, but as another embodiment, the cable length Lc of the interface cable 7 between the channel device 3 and the disk controller 4 is measured. It is also possible to use a setting means for externally setting as the preset information. In this case, the transfer start time determination unit 45
Can be the same operation as the above embodiment except that Tsg is calculated by the following formula.

Tsg = nCLc where n is the number of interface signals transmitted and received between the channel device 3 and the disk controller 4 in command chaining, and C is the propagation time of the interface signal per unit length of the interface cable 7. Is. The means for setting Lc and the means for the transfer start timing determination unit 45 to obtain the value of Lc may be the same as, for example, a known technique for setting the device address of the disk control device 4. Also, in this case, obviously, the timer 44 and the DEF
The operation of the timer 44 of the INE EXTENT processing unit 41 and the LOCATE processing unit 42 becomes unnecessary.

[0045]

As described above, according to the present invention,
In the data transfer process between the channel device and the external storage device, the time required for the data transfer between the channel device and the buffer memory to which the command chaining time is added, and the data between the external storage device and the buffer memory Predict the time required for transfer, and based on the prediction result,
By determining the start time of the data transfer between the channel device and the buffer memory so that the transfer data stays in the buffer memory for the minimum time, the utilization rate of the buffer memory is minimized. It is possible to suppress the possibility that the usage rate becomes a bottleneck to the total throughput.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a disk control device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a computer system using a disk control device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an ideal form of data transfer to and from a buffer memory memory.

FIG. 4 is an explanatory diagram showing an ideal form of data transfer to and from a buffer memory memory.

FIG. 5 is an explanatory diagram showing a command chain and command parameters created in the main storage device in the embodiment of the present invention.

[Explanation of symbols]

1 ... Processing device, 2 ... Main memory device, 3 ... Channel device, 4
... disk control device, 5 ... buffer memory, 6 ... disk device, 20 ... command chain, 21 ... command parameter, 40 ... command decoding unit, 41 ... DEFINE
EXTENT processing unit, 42 ... LOCATE processing unit, 4
3 ... Data transfer command processing unit, 44 ... Timer, 45 ...
Transfer start time determination unit, 46 ... Channel reconnection request unit, 4
7 ... Disk device positioning section.

Claims (3)

[Claims] 1. A buffer memory interposed between a channel device and an external storage device for temporarily storing transfer data between the channel device and the external storage device, the channel device and the buffer. By predicting the time required to transfer data to and from the memory and the time required to transfer data between the external storage device and the buffer memory, the transfer data stays in the buffer memory for the minimum time. As described above, in the external storage control device having the determining means for determining the data transfer start time between the channel device and the buffer memory, when the data transfer is a command chain consisting of a plurality of channel commands, Providing a predicting means for predicting a total command chaining time between individual channel commands, said determining The stage adds the sum of the command chaining times predicted by the predicting means to the time required for data transfer between the channel device and the buffer memory, and the step between the channel device and the buffer memory. An external storage control device characterized by determining a data transfer start time. 2. The external storage control device according to claim 1, wherein the predicting means comprises a measuring means for measuring a command chaining time from a specific channel command before the start of data transfer to the next channel command, The command chaining time measured by the measuring means is regarded as an individual command chaining time, and the command chaining time is multiplied by a number obtained by subtracting 1 from the number of channel commands to predict the total command chaining time. An external storage control device characterized by the above. 3. The external storage control device according to claim 1, wherein the predicting means externally sets an interface cable length with the channel device, and the interface cable length set by the setting means. And the command chaining time calculated by the above-mentioned calculating means is regarded as an individual command chaining time, and the command chaining time is calculated from the number of channel commands. An external storage control device for predicting the total command chaining time by multiplying by a number obtained by subtracting 1.