JPH05176013A - Transmission speed variable demodulator - Google Patents

Transmission speed variable demodulator

Info

Publication number
JPH05176013A
JPH05176013A JP3354343A JP35434391A JPH05176013A JP H05176013 A JPH05176013 A JP H05176013A JP 3354343 A JP3354343 A JP 3354343A JP 35434391 A JP35434391 A JP 35434391A JP H05176013 A JPH05176013 A JP H05176013A
Authority
JP
Japan
Prior art keywords
transmission rate
transmission speed
signal
demodulator
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3354343A
Other languages
Japanese (ja)
Inventor
Katsushi Yoshihara
勝志 吉原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP3354343A priority Critical patent/JPH05176013A/en
Publication of JPH05176013A publication Critical patent/JPH05176013A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To automatically alter transmission speed in a demodulator to appropriate transmission speed matched with the speed of reception speed. CONSTITUTION:This demodulator is provided with means 3-8 converting the reception signal into a base band signal, means (a both waves detectors 20, an A/D converter 21 and a high speed Fourier transformer 22) extracting a transmission speed component from the converted base band signal and recognizing transmission speed and a means (controller 13) for outputting a parameter alteration control signal for varying transmission speed in accordance with the transmission speed. A parameter for outputting the parameter alteration control signal based on recognized transmission speed and altering transmission speed is controlled and transmission speed is automatically altered in accordance with the reception signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は伝送速度可変復調装置に
関し、特に伝送速度を受信信号に応じて自動的に変化す
るようにした復調装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable transmission rate demodulator, and more particularly to a demodulator which automatically changes its transmission rate according to a received signal.

【0002】[0002]

【従来の技術】図2に従来の伝送速度可変復調装置の一
例を示す。4相位相変調された受信信号1は、分配器2
により2分岐され夫々ミキサ3,4に入力される。一
方、受信信号の搬送波周波数と近似している周波数信号
を発振器6から出力させ、この周波数信号をそのまま及
び90°位相偏移器5で偏移させた信号を夫々ミキサ3,
4に入力させる。これにより、受信信号1はミキサ3,
4によってベースバンド帯信号に準同期検波される。
2. Description of the Related Art FIG. 2 shows an example of a conventional variable transmission rate demodulator. The received signal 1 that has been subjected to the four-phase modulation is distributed to the distributor 2
Is branched into two and input to mixers 3 and 4, respectively. On the other hand, a frequency signal that is close to the carrier frequency of the received signal is output from the oscillator 6, and this frequency signal is used as it is and the signal that is shifted by the 90 ° phase shifter 5 is input to the mixer 3, respectively.
Input to 4. As a result, the received signal 1 becomes the mixer 3,
Quasi-synchronous detection is performed on the baseband signal by 4.

【0003】この準同期検波された信号は、可変低域通
過ろ波器7,8で雑音圧縮が行われる。このろ波器7,
8の出力はアナログ−ディジタル(A/D)変換器9,
10により任意ビットのディジタル信号に変換され、更
にディジタル復調器11により同期検波されて復調デー
タ15a,15bとされる。又、A/D変換器9,10
へのサンプリングクロックはクロック抽出器12から供
給される。
The quasi-coherently detected signal is noise-compressed by the variable low-pass filters 7 and 8. This filter 7,
The output of 8 is an analog-digital (A / D) converter 9,
A digital signal of arbitrary bits is converted by 10 and further synchronously detected by a digital demodulator 11 to obtain demodulated data 15a and 15b. Also, the A / D converters 9 and 10
The sampling clock for is supplied from the clock extractor 12.

【0004】ここで、伝送速度を変化する場合には、可
変低域通過ろ波器7,8の帯域を変更することと、ディ
ジタル復調器11内のパラメータを変更すること、及び
クロック抽出器12のループフィルタの時定数を変更す
ることが必要となる。これらの変更は、手操作される伝
送速度切替器14により制御器13を通して各パラメー
タ変更用制御信号16a,16b,16cを出力するこ
とで行われる。
Here, when changing the transmission rate, the bands of the variable low-pass filters 7 and 8 are changed, the parameters in the digital demodulator 11 are changed, and the clock extractor 12 is used. It is necessary to change the time constant of the loop filter of. These changes are performed by outputting the control signals 16a, 16b, 16c for changing each parameter through the controller 13 by the transmission rate switching device 14 that is manually operated.

【0005】[0005]

【発明が解決しようとする課題】このような従来の伝送
速度可変復調装置では、伝送速度を変化させる際には、
手操作によって伝送速度切替器14を切替え操作する必
要がある。このため、伝送速度の変更が面倒になるとと
もに、好適な復調を行うために受信信号の速度に見合っ
た適正な伝送速度に設定することが難しいという問題が
ある。本発明の目的は、受信信号の速度に見合った適正
な伝送速度に自動的に変更することを可能にした伝送速
度可変復調装置を提供することにある。
In such a conventional variable transmission rate demodulator, when changing the transmission rate,
It is necessary to manually switch the transmission rate switch 14. Therefore, there is a problem that the change of the transmission rate becomes troublesome and it is difficult to set an appropriate transmission rate corresponding to the rate of the received signal in order to perform suitable demodulation. It is an object of the present invention to provide a variable transmission rate demodulator capable of automatically changing to an appropriate transmission rate suitable for the speed of a received signal.

【0006】[0006]

【課題を解決するための手段】本発明は、受信信号をベ
ースバンドに変換する手段と、変換されたベースバンド
信号から伝送速度成分を抽出して伝送速度を認識する手
段と、この伝送速度に応じて伝送速度を可変するための
パラメータの変更用制御信号を出力する手段とを備え
る。ここでは、ベースバンド信号から伝送速度成分を抽
出して伝送速度を認識する手段を、ベースバンド信号を
両波検波する両波検波器と、検波された出力をアナログ
−ディジタル変換するA/D変換器と、変換されたディ
ジタル信号をフーリエ変換する高速フーリエ変換器とで
構成する。
According to the present invention, there is provided means for converting a received signal into a baseband, means for recognizing a transmission rate by extracting a transmission rate component from the converted baseband signal, and the transmission rate. And means for outputting a control signal for changing the parameter for varying the transmission rate accordingly. Here, a means for extracting the transmission rate component from the baseband signal and recognizing the transmission rate is a dual-wave detector for detecting both waves of the baseband signal and an A / D conversion for performing analog-digital conversion on the detected output. And a fast Fourier transformer for Fourier transforming the converted digital signal.

【0007】[0007]

【作用】ベースバンド信号を両波検波器で検波すること
で、その出力スペクトラムに速度成分(クロック成分)
が現れるため、この検波出力をA/D変換して任意ビッ
トのディジタル信号とし、このディジタル信号をフーリ
エ変換することでクロック成分を検出し、このクロック
成分から受信信号の伝送速度に一致するクロック周波数
を解読し、伝送速度を認識する。この伝送速度に基づい
て伝送速度を設定するパラメータの変更用制御信号を出
力させる。
[Function] By detecting the baseband signal with the double-wave detector, the output spectrum has a velocity component (clock component).
Therefore, the detected output is A / D converted into a digital signal of arbitrary bits, and the clock component is detected by Fourier transforming this digital signal, and the clock frequency that matches the transmission speed of the received signal from this clock component. Decode and recognize the transmission speed. A control signal for changing the parameter for setting the transmission rate based on the transmission rate is output.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例のブロック回路図であり、
図2に示した従来構成と同一部分には同一符号を付して
ある。即ち、4相位相変調された受信信号1は、分配器
2により2分岐され夫々ミキサ3,4に入力される。一
方、受信信号の搬送波周波数と近似している周波数信号
を発振器6から出力させ、この周波数信号をそのまま及
び90°位相偏移器5で偏移させた信号を夫々ミキサ3,
4に入力させる。これにより、受信信号1はミキサ3,
4によってベースバンド帯信号に準同期検波される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram of an embodiment of the present invention.
The same parts as those of the conventional configuration shown in FIG. 2 are designated by the same reference numerals. That is, the reception signal 1 that has been subjected to the four-phase modulation is split into two by the distributor 2 and input to the mixers 3 and 4, respectively. On the other hand, a frequency signal that is close to the carrier frequency of the received signal is output from the oscillator 6, and this frequency signal is used as it is and the signal that is shifted by the 90 ° phase shifter 5 is input to the mixer 3, respectively.
Input to 4. As a result, the received signal 1 becomes the mixer 3,
Quasi-synchronous detection is performed on the baseband signal by 4.

【0009】この準同期検波された信号は、可変低域通
過ろ波器7,8で雑音圧縮が行われる。このろ波器7,
8の出力はアナログ−ディジタル(A/D)変換器9,
10により任意ビットのディジタル信号に変換され、更
にディジタル復調器11により同期検波されて復調デー
タ15a,15bとされる。又、A/D変換器9,10
へのサンプリングクロックはクロック抽出器12から供
給される。
The quasi-coherently detected signal is noise-compressed by the variable low-pass filters 7 and 8. This filter 7,
The output of 8 is an analog-digital (A / D) converter 9,
A digital signal of arbitrary bits is converted by 10 and further synchronously detected by a digital demodulator 11 to obtain demodulated data 15a and 15b. Also, the A / D converters 9 and 10
The sampling clock for is supplied from the clock extractor 12.

【0010】更に、前記可変低域通過ろ波器8の出力を
両波整流器20へ入力し、両波整流する。この両波整流
器20では、図3に示すように、その出力スペクトラム
にクロック成分が現れ、しかもこのクロック周波数は伝
送速度(シンボルレート)周波数に一致している。この
整流された出力はA/D変換器21により任意ビットの
ディジタル信号に変換され、高速フーリエ変換器22に
入力される。この高速フーリエ変換器22では、クロッ
ク成分を検出し、かつそのクロック周波数を解読し、こ
れを制御器13へ出力する。制御器13では、解読され
たクロック周波数から受信信号の伝送速度を認識し、可
変低域通過ろ波器7,8、ディジタル復調器11、及び
クロック抽出器12の各パラメータ変更用制御信号16
a,16b,16cを出力する。
Further, the output of the variable low-pass filter 8 is input to a double-wave rectifier 20 and double-wave rectified. In this double-wave rectifier 20, as shown in FIG. 3, a clock component appears in its output spectrum, and this clock frequency matches the transmission rate (symbol rate) frequency. The rectified output is converted into a digital signal of arbitrary bits by the A / D converter 21, and is input to the fast Fourier transformer 22. The fast Fourier transformer 22 detects the clock component, decodes the clock frequency, and outputs it to the controller 13. The controller 13 recognizes the transmission rate of the received signal from the decoded clock frequency, and changes the parameter control signals 16 of the variable low-pass filters 7 and 8, the digital demodulator 11 and the clock extractor 12.
a, 16b, 16c are output.

【0011】したがって、この構成では、両波整流器2
0、A/D変換器21及び高速フーリエ変換器22によ
って受信信号中のクロック周波数が自動的に解読され、
このクロック周波数に基づいて制御器13から可変低域
通過ろ波器7,8、ディジタル復調器11、及びクロッ
ク抽出器12の各パラメータ信号16a,16b,16
cが出力され、伝送速度の変更が行われるので、手操作
による伝送速度の変更操作が不要となり、受信信号に対
応した適正な伝送速度に自動的に変換されることにな
る。
Therefore, in this configuration, the double-wave rectifier 2
0, the A / D converter 21 and the fast Fourier transformer 22 automatically decode the clock frequency in the received signal,
Based on this clock frequency, the controller 13 sends the parameter signals 16a, 16b, 16 of the variable low-pass filters 7, 8, the digital demodulator 11, and the clock extractor 12, respectively.
Since "c" is output and the transmission rate is changed, it is not necessary to manually change the transmission rate, and the transmission rate is automatically converted to an appropriate transmission rate corresponding to the received signal.

【0012】[0012]

【発明の効果】以上説明したように本発明は、ベースバ
ンド信号から伝送速度成分を検出し、これに基づいて伝
送速度を設定するパラメータの変更用制御信号を出力さ
せるので、人手を介して伝送速度を変更しなくとも、受
信信号に対応した適正な伝送速度に自動変換され、正常
にディジタル復調が行われるという効果がある。
As described above, according to the present invention, the transmission rate component is detected from the baseband signal and the control signal for changing the parameter for setting the transmission rate is output based on the detected transmission rate component, so that the transmission is performed manually. Even if the speed is not changed, there is an effect that it is automatically converted into an appropriate transmission speed corresponding to the received signal and normal digital demodulation is performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の伝送速度可変復調装置の一実施例のブ
ロック回路図である。
FIG. 1 is a block circuit diagram of an embodiment of a variable transmission rate demodulator of the present invention.

【図2】従来の伝送速度可変復調装置の一例のブロック
回路図である。
FIG. 2 is a block circuit diagram of an example of a conventional variable transmission rate demodulator.

【図3】両波検波器の出力のスペクトラム図である。FIG. 3 is a spectrum diagram of an output of a double-wave detector.

【符号の説明】[Explanation of symbols]

1 受信信号 3,4 ミキサ 6 発振器 7,8 可変低域通過ろ波器 11 ディジタル復調器 12 クロック抽出器 13 制御器 20 両波検波器 21 A/D変換器 22 高速フーリエ変換器 1 Received Signal 3,4 Mixer 6 Oscillator 7,8 Variable Low Pass Filter 11 Digital Demodulator 12 Clock Extractor 13 Controller 20 Double Wave Detector 21 A / D Converter 22 Fast Fourier Transformer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 受信信号をベースバンド信号に変換する
手段と、変換されたベースバンド信号から伝送速度成分
を抽出して伝送速度を認識する手段と、この伝送速度に
応じて伝送速度を可変するためのパラメータの変更用制
御信号を出力する手段とを備えることを特徴とする伝送
速度可変復調装置。
1. A means for converting a received signal into a baseband signal, a means for recognizing a transmission rate by extracting a transmission rate component from the converted baseband signal, and a transmission rate variable according to the transmission rate. And a means for outputting a control signal for changing parameters for the transmission rate variable demodulation device.
【請求項2】 ベースバンド信号から伝送速度成分を抽
出して伝送速度を認識する手段を、ベースバンド信号を
両波検波する両波検波器と、検波された出力をアナログ
−ディジタル変換するA/D変換器と、変換されたディ
ジタル信号をフーリエ変換する高速フーリエ変換器とで
構成する請求項1の伝送速度可変復調装置。
2. A means for extracting a transmission rate component from a baseband signal and recognizing the transmission rate, a dual wave detector for detecting both waves of the baseband signal, and an A / A for performing analog-digital conversion on the detected output. 2. The variable transmission rate demodulator according to claim 1, comprising a D converter and a fast Fourier transformer for Fourier transforming the converted digital signal.
JP3354343A 1991-12-20 1991-12-20 Transmission speed variable demodulator Pending JPH05176013A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3354343A JPH05176013A (en) 1991-12-20 1991-12-20 Transmission speed variable demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3354343A JPH05176013A (en) 1991-12-20 1991-12-20 Transmission speed variable demodulator

Publications (1)

Publication Number Publication Date
JPH05176013A true JPH05176013A (en) 1993-07-13

Family

ID=18436915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3354343A Pending JPH05176013A (en) 1991-12-20 1991-12-20 Transmission speed variable demodulator

Country Status (1)

Country Link
JP (1) JPH05176013A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007507118A (en) * 2003-06-30 2007-03-22 ヴィア テクノロジーズ インコーポレイテッド Wireless receiver supporting multiple modulation formats with a single pair of ADCs
US7672596B2 (en) 2005-06-14 2010-03-02 Sumitomo Electric Industries Ltd. Optical receiver circuit applicable to multiple transmission rates
JP2010154055A (en) * 2008-12-24 2010-07-08 Mitsubishi Electric Corp Symbol clock detecting circuit, analog/digital discriminating circuit, and modulation mode discriminator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007507118A (en) * 2003-06-30 2007-03-22 ヴィア テクノロジーズ インコーポレイテッド Wireless receiver supporting multiple modulation formats with a single pair of ADCs
US7672596B2 (en) 2005-06-14 2010-03-02 Sumitomo Electric Industries Ltd. Optical receiver circuit applicable to multiple transmission rates
JP2010154055A (en) * 2008-12-24 2010-07-08 Mitsubishi Electric Corp Symbol clock detecting circuit, analog/digital discriminating circuit, and modulation mode discriminator

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