JPH05175448A - Mis type semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the yield and reliability of a 1-transistor type memory cell while the capacitance of its capacitance part is increased. CONSTITUTION:A trench 1a is formed in the capacitance part of a 1-transistor type memory cell. A charge storing electrode 4 which has fine semi-spherical protrusions and recesses is formed on the side surfaces and the bottom of the trench 1a. The trench 1a is filled with a capacitance electrode 6 with a capacitance insulating film 5 provided on the surface of the electrode 4 therebetween. For instance, the charge storing electrode 4 is composed of a polycrystalline silicon film which has semi-spherical grains made to grow on its surface. Thus, by providing fine unevenness on the charge storing electrode 4, its surface area is increased, the capacitance of the memory cell is increased, the capacitance part composed of the trench, the electrodes, etc., can be formed easily and the yield and reliability can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor memory device having a one-transistor type memory cell.

[0002]

2. Description of the Related Art A MIS type semiconductor memory device is widely used in which a one-transistor type memory cell composed of one transistor and a capacitance provided adjacent to it is used as an information unit. In a memory device, if a transistor and a capacitor are formed on the same plane, the area occupied by one memory cell becomes large, which is disadvantageous for high integration.
Therefore, a so-called "groove capacitance type" memory cell is proposed, in which a groove is formed in the semiconductor substrate of the capacitor portion, and a conductive material is embedded in the groove through an insulating film provided on the inner surface of the groove to form a capacitor. Has been done. In addition, a so-called "multilayer capacitance type" memory cell in which two or more conductive layers are stacked in the capacitance section via an insulating film to form a capacitance for charge storage is also used.

[0003]

[Problems to be Solved by the Invention] The above-mentioned "groove capacity type"
In the above memory cell, the depth of the groove is increased or the thickness of the insulating film is decreased in order to avoid miniaturization of the memory cell, that is, reduction of the capacity of the memory cell due to the decrease of the area of the capacity. .. As a result, the variation of the groove depth is increased with the increase of the etching time for forming the groove, the pinhole density is increased with the thinning of the insulating film, and the yield and reliability are decreased due to the decrease of withstand voltage. There was a problem that caused.

Further, in the "multilayer capacitance type" memory cell, in order to secure the capacity of the memory cell due to the miniaturization of the plane dimension, the thickness of the charge storage electrode is increased or the capacity insulating film is formed. The film thickness was thin. As a result, it becomes difficult to process the charge storage electrode, or "groove capacitance type"
As in the case of the memory cell, there is a problem that the yield decreases due to the increase of pinholes in the insulating film. An object of the present invention is to provide a semiconductor memory device with improved yield and reliability in memory cells.

[0005]

A semiconductor memory device according to the present invention is for storing charges in which a groove is formed in a capacitor portion of a one-transistor type memory cell and hemispherical minute irregularities are formed on the side surface and the bottom surface of the groove. An electrode is formed, and a capacitor electrode is embedded in the groove via a capacitor insulating film provided on the surface of the electrode. The charge storage electrode is composed of a polycrystalline silicon film having hemispherical grains grown on its surface.

[0006]

[Function] By providing minute irregularities on the charge storage electrode, the surface area thereof is increased, the capacity of the memory cell is increased and the formation of a capacitor portion such as a groove or an electrode is facilitated, and the yield and reliability are improved. To do.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a vertical sectional view showing a first embodiment of the present invention,
A "groove capacitance" memory cell is shown. In the figure, a field oxide film 2 having a thickness of about 0.5 μm is formed in the inter-element region of the p-type silicon substrate 1, and a deep groove 1a is formed in the capacitor portion. An n-type diffusion layer 3 is formed on the side surface and the bottom surface of the groove 1a on the surface of the silicon substrate 1. Furthermore,
On the surface of the silicon substrate on the side surface of the groove, a polycrystalline silicon film 4 as a capacitance storage electrode having fine hemispherical grains (granular particles) is deposited, and the capacitance deposited on the polycrystalline silicon film 4 is deposited. A capacitor electrode 6 made of polycrystalline silicon is buried in the groove via an insulating film 5. Further, a gate electrode (word line) 8 made of polycrystalline silicon is formed on the gate oxide film 7 of the silicon substrate 1 adjacent to the capacitor portion in a direction perpendicular to the paper surface. An n-type diffusion layer 9 is formed on the silicon substrate 1 so as to sandwich the gate power 8 and is connected to the n-type diffusion layer 3. A bit line 10 is connected to the n-type diffusion layer 9 through a contact hole formed in the interlayer film 23.

Next, a method of manufacturing the semiconductor memory device of FIG. 1 will be described in the order of steps with reference to FIGS. First, as shown in FIG. 2, a field oxide film 2 having a thickness of about 3000 to 5000 Å is formed in an inter-device insulating region on a p-type silicon substrate 1, and a thickness of 300 to about 300 is formed on a silicon substrate in an active device region. Five
An oxide film 11 of about 00Å is formed. Next, as shown in FIG. 3, a portion other than the capacitance portion is covered with a photoresist 12, and n-type impurity ions 13 are implanted into the surface of the silicon substrate 1 in the capacitance portion to form an n-type diffusion layer 14. Arsenic is suitable as an impurity, and an appropriate dose is about 10 ¹² to 10 ¹⁴ / cm ² .

Next, as shown in FIG. 4, a groove 1a having an opening diameter of 0.5 to 1 .mu.m and a depth of 3 to 5 .mu.m is formed in the silicon substrate 1 by a photolithography process using a photoresist 15 which is newly formed. To do. Then, the n-type impurity ions 16 are implanted into the side wall and the bottom of the formed groove 1a. The injection method is as follows:
The wafer is tilted with respect to the ion beam, and implantation is performed while rotating the wafer. Arsenic is suitable as the impurity ion and a concentration of about 10 ¹⁷ to 10 ¹⁹ / cm ³ is suitable. As a result, the n-type diffusion layer 3 is formed on the side surface and the bottom of the groove 1a.

Next, as shown in FIG. 5, polycrystalline silicon 17 is deposited on the entire surface. Formed polycrystalline silicon film 1
A suitable thickness of 7 is 1000Å to 3000Å. The polycrystalline silicon film 17 may be doped with n-type impurities in advance, or may be doped with n-type impurities after the growth of polycrystalline silicon. Phosphorus is suitable as the n-type impurity, but arsenic may be used.

Further, as shown in FIG. 6, polycrystalline silicon 18 is deposited on the polycrystalline silicon film 17. The deposition of the formed polycrystalline silicon film 18 is performed by a vapor phase growth method. The growth gas is S diluted with He gas to about 20%.
By maintaining the growth temperature around 550 ° C. using iH ₄ gas, polycrystalline silicon having hemispherical grains with a diameter of about 500 to 3000 Å grows. Alternatively, once the amorphous silicon is grown at a temperature of about 500 ° C or less, 500 to 700
It is also possible to cause grain size growth and hemispherical grain growth by applying heat treatment at a temperature of ° C.

Then, as shown in FIG. 7, the entire surface is etched back by reactive ion etching to remove the polycrystalline silicon films 18 and 17 on the surface of the silicon substrate 1 to form the electrode 4 for charge storage. It At this time, the oxide film 11 on the surface of the silicon substrate 1 serves as a stopper for etching back, and the surface of the silicon substrate 1 is not damaged. Further, at the groove bottom, after etching back, the shape of the hemispherical grains is transferred to the underlying silicon substrate 1 to form convex and concave portions. Further, the polycrystalline silicon on the side wall of the groove remains after the etching back. By performing appropriate heat treatment before or after etching back,
Impurities are doped into the hemispherical grains from the underlying polycrystalline silicon 1 to impart conductivity.

Next, as shown in FIG. 8, a capacitive insulating film 5 is formed on the side surface and the bottom surface of the groove 1a. As a capacitive insulation film, a thickness of 5 to 100 Å on a silicon nitride film
A two-layer film composed of an oxide film of about 30 Å is suitable. Then, grow polycrystalline silicon 6 on the entire surface,
After completely filling the groove, impurities such as phosphorus are diffused to make it conductive. Alternatively, once polycrystalline silicon having a thickness that does not completely fill the groove is deposited and phosphorus is diffused,
After forming an oxide film on the surface by oxidation, polycrystalline silicon may be grown again to fill the inside of the groove. This oxide film functions as a stopper when etching back the polycrystalline silicon.

Next, as shown in FIG. 9, the entire surface is etched back by reactive ion etching or an etching solution to make the thickness of the polycrystalline silicon film 6 on the surface of the silicon substrate about 2000 to 5000Å. Further, as shown in FIG. 10, the polycrystalline silicon film 6 is selectively etched by a photolithography process using a photoresist 20 to form a capacitor electrode.

Next, as shown in FIG.
After forming the gate oxide film 7 of about 00Å, the thickness 20
A polycrystalline silicon of 00 to 3000 Å is grown and a gate electrode 8 to be a word line is formed by a photolithography process. Further, arsenic ions 21 are implanted by about 10 ¹⁵ to 10 ¹⁶ / cm ² by a self-alignment method using the gate electrode 8 to form an n-type diffusion layer 9 as a source / drain region. Then, as shown in FIG. 1, an interlayer film 22 is deposited on the entire surface, and a contact hole is opened in the interlayer film 22 on the n-type diffusion layer 9. Then, after depositing metal on the entire surface, the bit line 10 is formed by a photolithography process using a photoresist. As the metal, aluminum having a thickness of about 3000 to 10000Å or metal silicide having a thickness of about 1000 to 5000Å, for example, tungsten silicide is used.

Therefore, according to the memory cell of this structure, since the side surface and the bottom surface of the groove are formed as hemispherical concavities and convexities, the areas of the capacitance storage electrode 4 and the n-type diffusion layer 3 are increased, and at the same time. Accordingly, the area of the capacitance insulating film 5 and the capacitance electrode 6 in contact with the capacitance insulating film 5 is increased, and the capacitance can be increased. Therefore, even if a groove having the same size as the conventional one is used, the capacity thereof can be increased, and the semiconductor memory device can be miniaturized,
High integration can be promoted.

FIG. 12 shows a second embodiment of the present invention, which is a "multilayer capacitance type" memory cell. The same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, a groove 1a is formed in the silicon substrate 1 of the capacitor portion, and an n-type diffusion layer 3 is formed by doping an n-type impurity in the silicon substrate on the side and bottom surfaces of the groove. On the side surface and bottom surface of the silicon substrate inside the trench, a polycrystalline silicon film 4 having hemispherical grains serving as an electrode for charge storage is deposited, and the field oxide film 2 and the interlayer film 22 on the gate electrode 8 are formed. Has been extended to. A capacitive electrode 6 is formed on the charge storage polycrystalline silicon film 4 with a capacitive insulating film 5 interposed therebetween. Furthermore,
A bit line 10 is formed on the interlayer film 23 formed thereover, and is connected to the n-type diffusion layer 9 via a contact hole.

Next, referring to FIGS. 13 to 18, FIG.
The method of manufacturing the storage device will be described in the order of steps. In FIG. 13, a field oxide film 2 is formed in an inter-element region on a p-type silicon substrate 1, and a word line made of polycrystalline silicon having a thickness of 2000 to 3000 Å is formed through a gate oxide film 7 having a thickness of 100 to 200 Å. (Gate electrode) 8 is formed. In addition, the depth in the silicon substrate of the connection part with the bit line and the capacitor part
An n-type diffusion layer 9 in which arsenic of about 0.05 to 0.2 μm is diffused is formed. A diffusion layer made of phosphorus may be used instead of arsenic.

Next, as shown in FIG. 14, after forming the interlayer film 22, an opening diameter of 0.5 to 1 μm is formed in the silicon substrate of the capacitor portion.
A groove 1a having a depth of about 1 to 3 μm is formed. Then, FIG.
As shown in FIG. 5, after depositing polycrystalline silicon having a thickness of about 500 to 2000 Å on the entire surface, phosphorus or arsenic is doped and a polycrystalline silicon film 4A is formed by a photolithography process. Further, as shown in FIG. 16, polycrystalline silicon 4B having hemispherical grains is deposited on the entire surface. The forming method is similar to that of the first embodiment.

Next, as shown in FIG. 17, the entire surface is etched back to form a polycrystalline silicon film 4B having hemispherical grains only around the polycrystalline silicon film 4A.
And the charge storage electrode 4 can be formed with these. Then, as shown in FIG. 18, the capacitive electrode 6 is formed via the capacitive insulating film 5. Further, as shown in FIG. 12, after depositing the interlayer film 23, the contact hole is opened and the bit line 10 is connected to complete the device.

[0021]

As described above, according to the present invention, the groove is formed in the silicon substrate of the capacitor portion and the polycrystalline silicon charge storage electrode having hemispherical grains is embedded in the groove. The irregularities due to the grain shape increase the surface area of the charge storage electrode and increase the capacity of the memory cell. Therefore, in the groove capacitance type memory cell, it is not necessary to increase the groove depth or the groove size more than necessary, and in the stacked type capacitor, the thickness of the charge storage electrode is more than necessary. It is not necessary to increase the thickness, and the film thickness of the capacitive insulating film can be set to a value that can ensure a sufficient breakdown voltage, and the yield and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

[Figure 2]

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor memory device of FIG. 1 in order of steps.

FIG. 12 is a sectional view of a second embodiment of the present invention.

FIG. 13

FIG. 18 is a cross-sectional view showing the method of manufacturing the semiconductor memory device in FIG. 12 in order of steps.

[Explanation of symbols]

 1 Silicon Substrate 1a Groove 3 n-type Diffusion Layer 4 Capacitance Storage Electrode 5 Capacitance Insulation Film 6 Capacitance Electrode 8 Word Line 9 n-type Diffusion Layer 10 Bit Line

Claims (2)

[Claims] 1. In a MIS type semiconductor memory device including a one-transistor type memory cell composed of one insulated gate field effect transistor and one capacitance, a groove is formed in a semiconductor substrate of a capacitance part, and A charge storage electrode having hemispherical minute irregularities is formed on the sidewall and bottom of the groove, and the capacitor electrode is embedded in the groove via a capacitor insulating film provided on the electrode surface. MIS semiconductor memory device. 2. The MIS type semiconductor memory device according to claim 1, wherein the charge storage electrode is composed of a polycrystalline silicon film having hemispherical grains grown on the surface thereof.