JPH05174206A - Integrated circuit storage device - Google Patents

Abstract

PURPOSE:To install the device in both electronic apparatuses of an electronic apparatus for executing a parallel transfer and an electronic apparatus such as a wrist watch, etc., for executing a serial transfer. CONSTITUTION:The integrated circuit storage device 200 is provided with an EEPROM 520, a serial/parallel converting part 540 for converting serial data to parallel data and outputting it, an up/down counter 560 for counting +1 each at the time of serial transfer and outputting it as address data, an address selector 570 for selecting and outputting an address, a parallel/serial converting part 580 for converting the parallel data into serial data and outputting it to an input/output terminal D1, and a control part 590 for outputting a control signal to each part and executing the control, and switches a parallel transfer and a serial transfer in accordance with a data transfer system of electronic apparatuses 100, 400 in which the integrated circuit storage device 200 is installed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit memory device having a plurality of data input / output terminals, and more particularly to an integrated circuit memory device installed in a housing portion of a small electronic device body.

[0002]

2. Description of the Related Art IC cards are used by enclosing an LSI chip in a conventional card, and various methods have been realized according to the application. The IC card refers to all cards including an integrated circuit in a broad sense, but in general, a microprocessor and a memory (electrically erasable / electrically writable EEPROM or ultraviolet erasable / electrically writable EPROM as a memory are used. Often included), IS
Often referred to as O-compliant. Further, when the integrated circuit includes only a memory, it is called a memory card (more specifically, a RAM card, a ROM card, a ROM cartridge, etc.) in order to avoid confusion. A conventionally known integrated circuit memory device such as an IC card has a large size of, for example, 54 × 85 mm and cannot be applied to a small electronic device such as a wrist watch. Therefore, a small thin disk integrated circuit memory device (IC memory device) is used. ) Can be developed and applied to small electronic devices.

[0003]

However, since the small-sized thin disk-shaped integrated circuit memory device is configured to be installed in the housing portion of the specific small electronic device body, the interface of the electronic device to be installed is If they are different, the problem that they cannot be connected occurs. For example, a thin disk integrated circuit that inputs and outputs data by parallel transfer cannot be connected to a small electronic device that performs serial transfer. The present invention has been made to solve the above problems, and an object of the present invention is to provide an integrated circuit memory device that can be electrically connected to an electronic device body regardless of the type of the electronic device to be installed. To do.

[0004]

In order to achieve the above object, an integrated circuit memory device according to the present invention is a parallel circuit for converting parallel data into serial data in an integrated circuit memory device having a plurality of data input / output terminals. Serial conversion means and a parallel / serial switching terminal for inputting a signal for controlling the parallel / serial conversion means,
The configuration is such that both parallel transfer and serial transfer are possible. Further, the signal input to the parallel / serial switching terminal matches the parallel / serial conversion by the parallel / serial conversion means with the data transfer method of the electronic device when the integrated circuit storage device is housed in a predetermined electric device. It may be a switching signal for switching so as to perform. Further, the integrated circuit storage device may be housed and installed in an integrated circuit storage device housing portion of an electronic device main body, and data may be transferred to and from the electronic device via the data input / output terminal. .. Further, the integrated circuit memory device is an IC
The data input / output terminal is connected to an external terminal of the IC card and is transferred to and from an electronic device to which the IC card is attached via the external terminal. It may be configured to do so.

[0005]

According to the first aspect of the present invention, since the integrated circuit memory device is provided with the parallel / serial conversion means and the parallel / serial switching terminal, data input / output can be performed by switching between parallel transfer and serial transfer. It can be installed in any electronic device such as an electronic device (for example, an electronic notebook) that performs the above and an electronic device such as a wristwatch that performs serial transfer. According to the second aspect of the invention, when the predetermined switching signal is input to the parallel / serial switching terminal when the integrated circuit storage device is housed in the electronic device,
The data transfer method of the integrated circuit storage device can be automatically matched with the data transfer method of the electronic device body. Further, in the inventions according to claims 3 and 4, the integrated circuit memory device can be installed in, for example, the wristwatch main body for serial transfer, or can be installed in an IC card for parallel transfer.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. 1 is an open perspective view of an electronic device according to an embodiment of the present invention, and FIG. 2 is a vertical side view of an integrated circuit memory device. The electronic device 1 includes an electronic device main body 100 and an integrated circuit storage device 200 housed in a main body case 110 of the electronic device main body 100, and is configured as a wrist watch in this embodiment. Then, the storage data of the integrated circuit storage device 200 is taken into the electronic device main body 100 by serial transfer and is displayed on a display unit (described later) of the electronic device 100.

The electronic device main body 100 includes a main body case 1
10 and a lid 120 which is attached to the body case 110 via a support shaft 121 so as to be openable and closable, and a wristband 130 is attached to the body case 110. A concave portion 111 into which the lid 120 is fitted is formed on the upper side of the main body case 110, and an integrated circuit device accommodating portion 112 is formed at the center of the concave portion 111.

The integrated circuit device accommodating portion 112 is formed, for example, in a circular shape, and radial input / output terminals 113, 113, ... And parallel serial (P) are formed on the circular outer periphery of the bottom portion thereof.
/ S) switching terminal 114 is provided. Further, a locking projection 115 is formed on the inner peripheral wall of the storage section 112 as a positioning section for positioning the integrated circuit storage device 200.

On the other hand, the lid 120 is constructed as, for example, a timepiece having a liquid crystal display portion DP on its front side, and inside the lid body 120, the front side display portion DP is provided with a clock display or the integrated circuit memory. An electronic circuit (not shown) including a microcomputer or the like for displaying various information based on stored data transferred by serial transfer from the device 200 is installed.

As shown in FIG. 2, the integrated circuit memory device 200 includes a circuit board 210, electrodes 220 disposed on the circuit board 210, and electrodes 220 on the circuit board 210 bonded to each other via bumps 230. The integrated circuit memory chip 240, the protective resin 250 for protecting the joint portion, and the integrated circuit memory chip 240 joined on the circuit board 210.
And a cap 260 that hermetically seals.

In more detail, the circuit board 21
0 is an insulating plate as a base, and electrodes 220, 220, ... Are provided radially toward the outer peripheral edge thereof.
An electrode 220b, which penetrates the circuit board 210 to reach the outside and serves as an input / output terminal for data transfer, is formed. Then, the electrode 22 in the integrated circuit memory device 200
0a has the integrated circuit memory chip 240 installed thereon. The circuit configuration of the integrated circuit memory chip 240 will be described later with reference to FIG.

Further, on the outer periphery of the integrated circuit storage device 200, there is formed an engaged concave portion 201 as a positioning portion capable of engaging with an engaging projection 115 as a positioning portion of the housing portion 112 of the electronic device 100. ing.

The integrated circuit memory device 200 is constructed in this way, and the electronic device body 100 is housed when it is stored.
In the storage part 112 of the
The lid 1 is housed in a state of being engaged with 4 and positioned.
20 is in a closed state.

The display section DP on the front side of the lid 120 is always clocked, and the integrated circuit memory device is displayed on the display section by operating a changeover switch (not shown) of the electronic device main body 100. Information of the stored data read from the device 200 can be displayed.

An example of the case where the integrated circuit storage device 200 is applied to the electronic device 1 configured as a wristwatch for serial transfer has been described above.
By configuring the integrated circuit memory chip 240 of No. 0 by the electronic circuit 500 shown in FIG. 5, it can be applied to other electronic devices of different models (for example, IC cards).

3 and 4 are views showing an example in which the integrated circuit memory device 200 according to the embodiment of the present invention is applied to an IC card type adapter 300. FIG. 3 is an exploded perspective view of the IC card type adapter. 4 is a perspective view of an electronic device 400 in which an IC card is used, and FIG. 6 is another IC card type adapter 6
It is an exploded perspective view of 00.

In FIG. 3, the IC card type adapter 30 is shown.
Reference numeral 0 denotes a storage device holder 310 for positioning and storing the integrated circuit storage device 200, and this storage device holder 31.
Support members 320 and 320 for locking 0 after inserting the main body,
Many parallel input / output pins 331, 331, ...
Circuit board 340 having input / output terminals 330 in which
And a front case 350 and a back case 360, in the case of this embodiment, the memory chip is irremovably sealed and has the same shape and size as an IC card. The integrated circuit storage device 200 is provided with a parallel / serial conversion circuit, which will be described later, and a parallel / serial switching terminal for switching between parallel transfer / serial transfer, and the integrated circuit storage device 200 is housed in the storage device holder 310 to store an IC. When properly mounted on the card type adapter 300, the data input / output from the integrated circuit storage device 200 becomes parallel transfer data. That is, when the integrated circuit storage device 200 is mounted in the IC card type adapter 300, the IC card type adapter 300 performs the same function as a normal IC card, and the integrated circuit storage device 200 is mounted. IC card type adapter 300
When mounted on an electronic device that performs parallel transfer, the stored data of the integrated circuit storage device 200 is transmitted / received to / from the electronic device main body by parallel transfer.

More specifically, the storage device holder 310 has, for example, a circular integrated circuit storage device 2 in the storage device holder 310.
Storage unit 311 and 3 having a semicircular shape for holding the outer circumference of 00
12 is formed. Engagement protrusions 311a and 312a for engaging the storage device holder 310 in the state after inserting the storage device holder 310 into the support members 320 and 320 at the tips of the storage parts 311 and 312.
Are formed. In addition, this storage device holder 310
On the inner peripheral wall of one of the accommodating parts 311 is a locking projection 31 as a positioning part for positioning the integrated circuit memory device 200.
3 is formed.

Further, the support members 320, 320 are configured as support members for supporting the storage device holder 310, and are divided into two members in the IC card type adapter 300, so that the storage device holder 31.
When 0 is inserted into the main body, the end portions 320a, 320a of the support members 320, 320 in the storage device holder 310 have the engaging protrusions 311a, 311a of the storage device holder 310.
And the storage device holder 310 can be locked in the inserted state. That is, when the memory device holder 310 accommodating the integrated circuit memory device 200 is inserted into the IC card type adapter 300, the engaging protrusions 311a and 312a of the memory device holder 310 are supported by the support member 3.
It comes into contact with the inner peripheral wall of 20, 320. In this state, when the storage device holder 310 is inserted in the back direction,
The support members 320 and 320 are engaging protrusions 311a and 312a.
When the storage device holder 310 is pushed in, it spreads outward, and when it is inserted further back, the engagement protrusions 311a and 312 of the storage device holder 310 are inserted.
a is the ends 320a, 320a of the support members 320, 320
, Thereby returning 320 and 320 to their original positions, and the storage device holder 310 is moved to the IC card type adapter 30.
Fully engaged in zero.

On the other hand, the circuit board 340 is based on an insulating plate, and the electrodes 341, 34 are radially disposed on the upper side of the circuit board 340 so as to face the electrodes 220b of the integrated circuit memory device 200.
1, while the IC card type adapter 300 is provided.
The input / output terminal 330 in which the input / output pins 331, 331, ... Are arranged is provided on the side surface of the wiring pattern 3, and the wiring pattern 3 that links the input / output terminal 330 and the electrodes 341, 341 ,.
42, 342, ... Are formed. Input / output pin 3 above
The input / output terminal 330 in which 31, 331, ... Are arranged is an IC
It becomes a connector portion of the card type adapter 300. And
Data is transmitted / received by parallel transfer with an external electronic device connected via the input / output terminal 330.

Further, the outer peripheral portions of the supporting members 320, 320 which are the side surfaces of the IC card type adapter 300, the circuit board 340 and the front case 35 which are in contact with the outer peripheral portions.
0 and a predetermined position of the back case 360, a double-sided adhesive sheet (not shown) is interposed, and these members are bonded by the double-sided adhesive sheet to form the IC card type adapter 300.

FIG. 4 shows a small electronic device to which the IC card type adapter 300 having the above-mentioned structure is applied (for example,
FIG. 4 is a diagram showing an electronic notebook 400, and the IC card type adapter 3 in which the integrated circuit storage device 200 is mounted from the card slot 401 of the electronic device 400 as shown in FIG.
When 00 is inserted, the memory in the IC card type adapter 300 is electrically connected to the microcomputer or the like in the main body of the electronic device 400, and data can be transmitted / received by parallel transfer.

FIG. 5 is a circuit diagram of the memory chip 240 of the integrated circuit memory device 200. In FIG. 5, 5
Reference numeral 00 denotes an electronic circuit in the memory chip 240. The electronic circuit 500 is provided with an external terminal 510 for transmitting / receiving data to / from the electronic device (wristwatch or the like) 100 or the electronic device (electronic notebook or the like) 400. .. The external terminals 510 are data input / output terminals D1 to D4 for inputting / outputting parallel transfer data to / from the electronic device 400 (however, when connected to the electronic device 100, only the input / output terminal D1 is a data input / output terminal). Address input terminals A1 to A to which address signals from the electronic devices 100 and 400 are input.
4, P / S to switch between parallel transfer and serial transfer
Parallel / serial switching terminal 51 to which a switching signal is input
1, 512, a Write signal to which a write signal (Write signal) is input, and a Vcc terminal and a GND terminal to which the power supply voltage Vcc and GND are supplied.

Of these, the parallel / serial switching terminal 5
Reference numerals 11 and 512 denote electrodes 2 of the integrated circuit memory device 200.
Wired to two adjacent electrodes of 20, 220, ..., For example, when the integrated circuit memory device 200 is housed in the integrated circuit device housing portion 112 of the electronic device 100 that performs serial transfer, these parallel serial The electrodes 220 and 220 of the integrated circuit memory device 200 communicating with the switching terminals 511 and 512 are the storage unit 1 of the electronic device 100.
The wide parallel / serial switching terminals 114 (see FIG. 1) arranged on the upper surface 12 are in electrical contact with each other. As a result, the parallel / serial switching terminal 5
It is possible to determine that the electronic devices 11 and 512 are connected to each other to be in a conductive state and an electronic device for serial transfer is accommodated.

The electronic circuit 500 includes the external terminal 51.
0, EEPROM that is electrically writable and rewritable
(Erasable and electrically programmable ROM) 52
0, a data latch 530 that latches the data input to the data input / output terminals D1 to D4, and serial data according to a serial / parallel control signal φSR from the control unit 590 described later when serial data is supplied to the input / output terminal D1. Is converted into parallel data and output to the data latch 530, an address latch 550 that latches the address signal input to the address input terminals A1 to A4, and a +1 is counted during serial transfer. Up / down counter 5 that outputs the VCT voltage supplied at the timing as address data
60, an address selector 570 that selects an address supplied from the input terminals A1 to A4 and an address generated by the up / down counter 560 and outputs the selected address to the EEPROM 520, and when serial data is output (the electronic device 100 is connected. Parallel / serial conversion unit 580 which converts parallel data read from the EEPROM 520 into serial data and outputs the serial data to the input / output terminal D1.
And a control unit 590 that outputs a control signal to each unit based on the Write signal and the parallel / serial switching signal (parallel / serial terminals 511, 512 ON signal) to perform data input / output control for parallel transfer and serial transfer. It is configured.

More specifically, the control unit 590 is described.
From, the clock signal φW1 for performing address access in synchronization with the clock, the clock signal φW2 for the timing signal for writing data, the clock signal φR for the timing signal for reading data, and the serial signal output during serial transfer. The serial / parallel control signal φSP for operating the parallel / serial conversion unit 540, and the parallel / serial conversion unit 58 which is output when the memory is read in the serial transfer.
A serial read control signal φSR for operating 0 and a control signal (reset signal RST, increment signal) for controlling the up / down counter 560 are output. Further, the parallel data input from the data input / output terminals D1 to D4 are input to the AND gates 601, 601 ,.
The AND gates 601, 601, ... Synchronize with the clock signal φW2 and output to the OR gates 602, 602 ,. On the other hand, during serial transfer, the data input / output terminal D1
The serial data input to the AND gate 603 is input to the AND gate 603 and is input to the serial / parallel conversion unit 540 in synchronization with the clock signal φW2 input via the inverter 604. Cereal/
The data converted into parallel data by the parallel conversion unit 540 is output to the data latch 530 via the OR gates 602, 602, ....

Further, the address latched in the address latch 550 is inputted to the AND gates 605, 605, ... And the AND gates 605, 605 ,.
The signal is output to the OR gates 606, 606, ... Synchronized with W1. On the other hand, during serial transfer, the address from the up / down counter 560 is OR gates 606, 60.
6 is input to the EEPROM 520. Above AN
D gates 605, 605, ... and OR gates 606, 6
, 06 form an address selector 570.

The parallel data output of the EEPROM 520 is input to AND gates 607, 607, ...
The AND gates 607, 607, ... Synchronize with the clock signal .phi.R and then output via the AND gates 608, 608 ,. Also, EEP
The parallel data output of the ROM 520 is the AND gate 6
The parallel / serial conversion unit 5 via 09, 609, ...
, And the serial read control signal φSR is supplied to the AND gates 609, 609, ... To turn these AND gates 609, 609 ,.
At the same time, an inverted signal from the inverter 610 is supplied to the AND gates 608, 608, ... And these AND gates 608, 608 ,.

The serial data subjected to parallel / serial conversion in the parallel / serial conversion section 580 during serial transfer is output through the OR gate 611 and the input / output terminal D1 during serial transfer.

Next, the operation of this embodiment will be described. First,
The operation of the electronic circuit 500 of the integrated circuit memory device 200 will be described. During parallel transfer (Integrated circuit memory device 200
When stored in the mold adapter 300 ) Address signals input to the address input terminals A1 to A4 are latched by the address latch 550. In this state,
When parallel data is input from the data input / output terminals D1 to D4, the parallel data is synchronized with the clock signal φW2 by the AND gates 601 and 601 and then the OR gate 60.
2 is input to the data latch 530 and latched there.

The address latch 550 is called at the timing of the latch clock signal φW1 and the OR gate 6 is called.
The data is output to the EEPROM 520 via 06, 606, ... And the EEPROM 520 writes and stores the parallel data latched by the data latch 530 at this address.

At the time of reading, the address input terminal A1
.About.A4 to the EEPROM 520, the addressed data is read from the EEPROM 520 according to the read timing clock signal .phi.R, AND gates 608, 608, and the input / output terminal D1.
Is output via D4. Further, since the serial read signal φSR is OFF at this time, no parallel data is sent to the parallel / serial conversion unit 580.

During serial transfer (integrated circuit memory device 200
(When stored in the electronic device 100 ) The address signals input to the address input terminals A1 to A4 are latched by the address latch 550, the up / down counter 560 is supplied with the voltage VCT, and control from the control unit 590 is performed. The signal sequentially increments the address by +1. At this time, the write timing clock φW1 is not output. When serial data is supplied to the data input / output terminal D1, this serial data is input to the serial / parallel conversion unit 540 through the AND gate 603. Serial / parallel conversion unit 540
The OR gates 602, 6 convert serial data input into parallel data according to the output timing of the serial / parallel control signal φSR output from the control unit 590.
, And output to the data latch 530. Then, the EEPROM 520 writes and stores the data converted into the parallel data at the write address created by the up / down counter 560. At this time, the data write timing clock φW2 is Low.

At the time of reading, the address input terminal A1
When the data is addressed from the A4 to the EEPROM 520, the addressed data is read from the EEPROM 520 in accordance with the read timing clock signal φR. At this time, the serial read signal φSR is AND gates 609, 609, ... And the AND gate 608. , 60
Since it is output to 8 ..., Parallel / when the φSR is output (that is, the timing when φSR is turned on)
Serial conversion is performed, and the serial converted serial data is output via the OR gate 611 and the data input / output terminal D1. At this time, AND gates 608, 608,
Is turned off, no parallel data is output.

Next, the operation of attaching the integrated circuit memory device 200 to the electronic devices 100 and 400 will be described. As shown in FIG. 1, on the lower surface of the integrated circuit memory device 200, input / output terminals required for parallel transfer are electrodes 220, 220,
It is provided as ...

When the integrated circuit memory device 200 is completely attached to the IC card type adapter 300 of the electronic device 400 for parallel transfer via the memory device holder 310, the electrodes 220 and 22 of the integrated circuit memory device 200 are installed.
, And the electrodes 341, 341, ... on the circuit board 340 of the memory device holder 310 contact each other to enable parallel transfer, and the electronic device 400 and the integrated circuit memory device 2
It is possible to realize 4-bit parallel processing with 00.

On the other hand, the housing portion 11 of the electronic device 100 such as a wrist watch for serially transferring the integrated circuit storage device 200.
.. and the serial / parallel switching terminal 114, which are necessary for serial transfer, are disposed in the storage section 112 when they are aligned and stored in the storage section 112. Therefore, these terminals 113, 113 ,. , 114 are connected to the electrodes 220, 220, ... Of the integrated circuit memory device 200, and serial transfer is possible between the electronic device 100 and the integrated circuit memory device 200.

As described above, the integrated circuit memory device 200 according to this embodiment has the EEPROM 520 and the serial / parallel control signal φSR from the controller 590, which will be described later, when serial data is supplied to the input / output terminal D1. A serial / parallel converter 54 that converts data into parallel data and outputs the data to the data latch 530.
0, an up / down counter 560 that counts by 1 during serial transfer and outputs the VCT voltage supplied at this timing as address data, and an input terminal A1
~ The address supplied from A4 and the address generated by the up / down counter 560 are selected and EEPRO is selected.
Address selector 570 for outputting to M520 and EEP
A parallel / parallel circuit that converts parallel data read from the ROM 520 into serial data and outputs the serial data to the input / output terminal D1.
The serial conversion unit 580, the Write signal, and the parallel / serial switching signal (parallel / serial terminals 511, 51
2 ON signal) and the like to output a control signal to each unit to perform data input / output control of parallel transfer and serial transfer, and to provide data of the electronic devices 100 and 400 in which the integrated circuit storage device 200 is installed. Since the parallel transfer and the serial transfer are switched according to the transfer method, it is possible to use any of the electronic devices 100 such as the IC card type adapter 300 inserted in the electronic device 400 for parallel transfer and the electronic device 100 such as a wristwatch for serial transfer. Can be installed. In this case, since the switching signal is input to the parallel / serial switching terminals 511 and 512 only by storing the integrated circuit storage device 200 in the storage portion of the electronic device, the integrated circuit storage device 200 is automatically electronically stored. The data transfer method of the main body of the device 100 or 400 can be matched. As a result, if the integrated circuit memory device 200 is replaced, the EEP in the integrated circuit memory device 200 is changed.
Electronic device 100, 4 of data stored in ROM 520
00 can be used mutually, for example, the data stored in the integrated circuit storage device 200 can be input by an electronic device that can easily input data, and can be later used for the electronic device 100 such as a wristwatch.

In the above embodiment, the integrated circuit memory device 200 is used.
Is held in the storage device holder 310, the integrated circuit storage device 200 held in the storage device holder 310 is
Although the C card type adapter 300 is inserted and engaged with the C card type adapter 300, any type may be used as long as the integrated circuit storage device 200 is properly accommodated in the IC card type adapter 300. For example, instead of the storage device holder 310 and the support members 320, 320 of FIG. 3, the integrated circuit storage device 20 may be provided in the IC card 600 as shown in FIG.
A support member 610 for storing 0 is provided, and the integrated circuit storage device 200 is stored while being positioned by a locking projection 615 formed as a positioning portion on the support member 610.
After that, the lid 630 of the case 620 may be screwed to install the integrated circuit storage device 200 in the IC card 600. This has the advantage that the integrated circuit storage device 200 installed in the IC card 600 can be easily replaced.

Although the electronic device 1 is a wristwatch and the electronic device 400 is an electronic notebook in the above embodiment, the electronic device 1 may be applied to any type of electronic device.

In the above embodiment, the integrated circuit memory device 2 is used.
Although the memory unit of 00 is an EEPROM, it is needless to say that it is not limited to this and may be an EPROM, a mask ROM, a RAM, or the like.

Of course, the types and numbers of the circuits and gates that constitute the integrated circuit memory device 200 are not limited to those in the above embodiment. For example, an up counter or a down counter may be used instead of the up / down counter 500.

In the above embodiment, the 4-bit parallel processing is performed by performing the parallel transfer with 4 bits, but the 8-bit or 16-bit parallel processing is performed according to the JEIDA (Japan Electronic Industry Development Association) standard. May be

Needless to say, the serial data terminal may be provided separately from the parallel data terminal.

Further, in the above embodiment, the parallel / serial switching is performed depending on the presence / absence of the electrodes in contact with the parallel / serial switching terminals 511 and 512, but the parallel / serial switching is performed by the control signal from the electronic device. May be.

[0046]

According to the invention described in claim 1, since the parallel / serial conversion means and the parallel / serial switching terminal are provided, data input / output can be performed by switching between parallel transfer and serial transfer. It can be installed in any electronic device such as an electronic device for performing (for example, an electronic notebook) and an electronic device for performing serial transfer such as a wristwatch.

According to the second aspect of the invention, when the integrated circuit storage device is set, it can be automatically matched with the data transfer system of the electronic equipment main body.

According to the third or fourth aspect of the invention, the integrated circuit storage device can be installed in the wristwatch body for serial transfer, and can be installed in the IC card for parallel transfer.

[Brief description of drawings]

FIG. 1 is a perspective view of an integrated circuit memory device according to an embodiment of the present invention and an electronic device equipped with the integrated circuit memory device.

2 is a vertical side view of the integrated circuit memory device shown in FIG. 1. FIG.

FIG. 3 is an exploded perspective view of an IC card type adapter to which the integrated circuit memory device of FIG. 1 is attachable / detachable.

FIG. 4 is a perspective view of the IC card type adapter of FIG. 3 and an electronic device into which the IC card type adapter is inserted.

FIG. 5 is a circuit diagram incorporated in a memory chip that constitutes the integrated circuit memory device shown in FIG.

FIG. 6 is an exploded perspective view of the IC card.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electronic device 100,400 Electronic device main body 110 Main body case 112 Integrated circuit storage device housing 113 Input / output terminal 114 Parallel / serial switching terminal 115 Locking protrusion 200 Integrated circuit storage device 201 Engaged recess 300,600 IC card type adapter 310 Storage device holder 313 Locking protrusion 320 Support member 500 Electronic circuit 510 External terminal 511, 512 Parallel / serial switching terminal 520 EEPROM 530 Data latch 540 Serial / parallel converter 550 Address latch 560 Up / down counter 570 Address selector 580 Parallel / Serial conversion unit 590 Control unit

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display area H01L 27/115

Claims (4)

[Claims] 1. In an integrated circuit memory device having a plurality of data input / output terminals, parallel / serial conversion means for converting parallel data into serial data, and parallel / serial for inputting a signal for controlling the parallel / serial conversion means. An integrated circuit memory device having a switching terminal to enable both parallel transfer and serial transfer. 2. The signal input to the parallel / serial switching terminal is parallel / serial by the parallel / serial conversion means when the integrated circuit storage device is housed in a predetermined electric device, according to the data transfer method of the electronic device. The integrated circuit memory device according to claim 1, wherein the integrated circuit memory is a switching signal for switching so as to match the conversion. 3. The integrated circuit memory device is housed and installed in an integrated circuit memory device housing portion of an electronic device body, and is configured to perform data transfer with the electronic device via the data input / output terminal. The integrated circuit memory device according to claim 1, wherein the integrated circuit memory device comprises: 4. The integrated circuit memory device is housed and installed in an integrated circuit memory device housing part of an IC card, and the data input / output terminal is connected to an external terminal of the IC card.
3. The integrated circuit storage device according to claim 1, wherein the integrated circuit storage device is configured to perform data transfer with an electronic device to which a card is attached via the external terminal.