JPH05173946A - Computer system - Google Patents

Abstract

PURPOSE:To replace a ROM where system software is written without degrading the efficiency of development of system software. CONSTITUTION:A command signal selector 2a of a bus controller 2 performs switching between the bus protocol of a ROM 3 on a mother board 5 and that of a ROM 4 to be replaced with on a bus slot 6 in accordance with the presence or the absence of a response signal 1a of a bus 1. Thus, the same effect as replacement of the ROM 3 on the mother board 5 is realized without detaching the ROM 3 mounted on the mother board 5 by only mounting another ROM 4 to be replaced with on the bus slot 6.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to computer systems, and more particularly to computer systems that require memory replacement.

[0002]

2. Description of the Related Art Conventionally, in a computer system of this type, when a memory that cannot be placed in a bus slot connected to a bus is replaced, an IC itself such as a ROM (read only memory) or a RAM (random access memory) is replaced. There is a need to.

In the development of system software that requires ROMization in a computer system such as a personal computer, the ROM in which the software is written is mounted on an actual system and evaluated. As a result, if a defect is found, the software is analyzed, and the ROM in which the software corrected based on the analysis result is written is written.
The work of exchanging with and re-evaluating is repeated.

Generally, BIOS (basic input output s)
ROM in which system software such as ystem) is written
Is not intended for replacement as a product and is placed on the motherboard.

In such a conventional computer system, it is often necessary to disassemble and reassemble the system in order to replace the ROM in which the system software is written. Therefore, many man-hours are required for disassembling and assembling the system. This is necessary, and there is a problem that the efficiency of system software development is significantly reduced.

On the other hand, there is a system in which this type of ROM can be mounted without disassembling the system. However, since the mounting position of the ROM is prioritized in this system, the printed circuit board design and the housing design are performed. With restrictions,
There is a problem that makes hardware development difficult.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned problems of the conventional ones, and to replace the ROM in which the system software is written without lowering the efficiency of the development of the system software. The purpose is to provide a computer system capable of performing.

[0008]

The computer system according to the present invention comprises:
A bus slot connected to a bus having a plurality of bus protocols, a memory connected to the bus other than the bus slot, and a bus slot having the same address as the memory and connected to the bus in the bus slot And a switching means for switching between the bus protocol of the memory and the bus protocol of the bus slot memory according to the presence or absence of a response signal on the bus.

[0009]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a bus 1 is a computer system bus controlled by a bus controller 2. This bus 1 is composed of a response signal 1a, a bus cycle start signal 1b, a bus command signal 1c, a memory command signal 1d, an address signal 1e, a data signal 1f, a status signal 1g and a control signal 1h. ing.

The bus controller 2 is mounted on the motherboard 5 and selects one of a plurality of bus protocols according to the presence / absence of the response signal 1a for the activated bus memory cycle. The selection of the bus protocol includes the selection of the command signal, and the selection of the command signal is performed by the command signal selector 2a. The command signal selector 2a selects to use the bus command signal 1c if there is a response signal 1a at the start of the bus memory cycle and use the memory command signal 1d if there is no response signal 1a at the start of the bus memory cycle.

An example of such a bus is NEC.
It is used as a compatible machine of the NESA bus of PC-H98 personal computer (PC-H98 and NESA are trademarks of NEC Corporation) and IBM PC-AT personal computer (PC-AT is a registered trademark of IBM Corporation in the United States). There is an EISA bus.

In the case of this example, the RPLY160 of the NESA bus,
The RPLY320 signal and the EX16 # and EX32 # signals of the EISA bus correspond to the response signal 1a, and the BCSTRT0 signal of the NESA bus and the START # signal of the EISA bus correspond to the bus cycle start signal 1b. The CMD0 signal of the NESA bus and the CMD # signal of the EISA bus are the bus command signal 1c.
Corresponding to, MRC0 and MWC0 signals of NESA bus and EIS
The SMEMR #, SMEMW #, MEMR #, MEMW # signals of the A bus correspond to the memory command signal 1d.

In the bus 1, the bus command signal 1c and the memory command signal 1d are not asserted at the same time. In the memory cycle in which the response signal 1a is asserted, the bus command signal 1c is asserted and the response signal 1
In the memory cycle in which a is not asserted, the memory command signal 1d is asserted.

The ROM 3 is mounted on the motherboard 5,
It stores system software such as BIOS.
Further, the ROM 3 stores the memory command signal 1d of the bus 1,
It is connected to the address signal 1e, the data signal 1f, the status signal 1g, and the control signal 1h, and is accessed by the memory command signal 1d. Furthermore, RO
Since M3 is not connected to the response signal 1a, it does not respond to this.

On the other hand, the exchange ROM 4 is mounted on the bus slot 6, and the response signal 1a, the bus cycle start signal 1b, the command signal 1c, and the address signal 1e.
, The data signal 1f, the status signal 1g, and the control signal 1h. The exchange ROM 4 responds to the response signal 1a when its own circuit is designated by the address signal 1e and the status signal 1g, and as a result is accessed by the bus command signal 1c output from the bus controller 2. Also, the replacement ROM 4 is mapped to the same address as the ROM 3.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. In the figure, non-response cycle a
ROM3 is mounted on the motherboard 5, and the replacement ROM4
Shows the operation in the state where is not inserted in the bus slot 6. The response cycle b shows the operation when the ROM 3 is mounted on the motherboard 5 and the replacement ROM 4 is mounted on the bus slot 6.

In the non-response cycle a, the bus cycle is started by the bus cycle start signal 1b, and even if the ROM 3 is designated by the address signal 1e and the status signal 1g, the ROM 3 does not assert the response signal 1a. The ROM 3 is accessed by asserting the memory command signal 1d.

In the response cycle b, since the exchange ROM 4 is mounted in the bus slot 6, the bus cycle is started by the bus cycle start signal 1b and the address signal 1
When the ROM 3 is designated by e and the status signal 1g, the ROM 3 does not assert the response signal 1a, but the exchange ROM 4 asserts the response signal 1a. For this reason,
The bus controller 2 asserts the bus command signal 1c without asserting the memory command signal 1d. As a result, the ROM 3 is not accessed and the replacement ROM 4
Is accessed.

In this way, the command signal selector 2a switches between the bus protocol of the ROM 3 on the motherboard 5 and the bus protocol of the replacement ROM 4 on the bus slot 6 depending on the presence or absence of the response signal 1a of the bus 1. The RO mounted on the motherboard 5 by
Another replacement RO for bus slot 6 without removing M3
Only by mounting M4, the same effect as replacing the ROM 3 on the motherboard 5 can be realized, and the ROM replacement work at the time of developing the ROM software can be significantly reduced. Therefore, the ROM 3 in which the system software is written can be replaced without reducing the efficiency of developing the system software.

[0021]

As described above, according to the present invention, the bus protocol of the bus slot memory connected to the bus by the bus slot connected to the bus having a plurality of bus protocols and the bus protocol other than the bus slot By switching the bus protocol of the connected memory according to the presence / absence of a response signal on the bus, the ROM in which the system software is written can be replaced without reducing the efficiency of the system software development. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 bus 1a response signal 1c bus command signal 1d memory command signal 2 bus controller 2a command signal selector 3 ROM 4 replacement ROM 5 motherboard 6 bus slot

Claims (1)

[Claims] 1. A bus slot connected to a bus having a plurality of bus protocols, a memory connected to the bus other than the bus slot, and the same address as the memory, wherein the bus slot connects the bus to the bus. And a switching means for switching between the bus protocol of the memory and the bus protocol of the memory for the bus slot depending on the presence or absence of a response signal on the bus. Computer system.