JPH05173882A - Information processor - Google Patents

Abstract

PURPOSE:To enhance address efficiency in the small capacity high--speed address translation mechanism of a full-associative system. CONSTITUTION:A valid V bit, a page attribute flag, an MP bit, a virtual page address part and a physical page address part exsist in the entry of a high-speed translation table 2. When indexing is executed, a selector 4 selects the virtual page address of a one-page or two-page unit from a comparators 3 and 6 in accordance with the MP bit and the hit signal of AND with the V bit is informed by an AND gate 5. The selector 10 selection-outputs the physical address of the one-page or two-page unit from couplers 8 and 9. When a register is executed, the comparators 7, 12 and 13 confirm the exsistance of the adjacent page of the physical address and the both virtual and physical page addresses and the AND gate 11 obtains the AND of the respective comparators with the V bit so that the signal is informed and a flag is changed to be the address conversion result of the two-page unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a high speed address conversion mechanism, and more particularly to a method of using a high speed address conversion table.

[0002]

2. Description of the Related Art Conventionally, many information processing apparatuses of this type have a high-speed address conversion mechanism for performing address conversion at high speed. The high-speed address translation mechanism is described in "Cache Memories" A. J. S
MITH ACM Computing Survey
s Vol14, No. 3 Sep. TLB in 1982
(Translation lookaside buffer, Translation Loo
abbreviation of case buffer).

[0003]

In the conventional information processing apparatus, a set associative (implementation of a cache memory in which a cache is divided into lines of different sets) type large-capacity address translation mechanism and a full associative (entry search) are used. There is often a small-capacity high-speed address conversion mechanism of the implementation of the cache memory that is performed for all lines). These are intended to achieve high address translation efficiency using limited hardware resources. On the other hand, when handling enormous data such as image data, a small capacity high-speed address translation mechanism causes an absolute number of entries in the address translation table to be insufficient with respect to the amount of data to be handled, which causes a decrease in address translation efficiency. Become. To avoid this, there are some that prepare a large size page for exclusive use, but there is a problem that the large size page can be used only for a specific purpose because the operating system cannot manage the page uniformly. there were. The present invention has been made in view of the above problems, and provides an information processing apparatus capable of achieving high address translation efficiency by using limited hardware resources by reducing the number of entries used in the high-speed address translation mechanism. The purpose is to do.

[0004]

According to the information processing apparatus of the present invention, in an information processing apparatus having a high-speed address conversion mechanism, an entry in a conversion table included in the high-speed address conversion mechanism has an address in units of one page or two pages. A flag unit indicating which of the conversion results is present, a conversion table indexing unit for indexing the conversion table corresponding to the output of the flag unit, and a registering process when registering the address conversion result in the conversion table. Adjacent page detection means for detecting the presence of an address translation result entry in the translation table in units of one page where both the virtual page address and the physical page address of the address are adjacent, and a response to the output of the adjacent page detection means The flag means included in the adjacent page entry detected by And a flag change means for changing the position and the address conversion results.

[0005]

According to the above construction, the flag means indicates whether the entry of the translation table included in the high speed address translation mechanism is the result of address translation in units of one page or two pages. The conversion table indexing means indexes the conversion table according to the output,
When registering the address translation result in the translation table, an address translation result entry in units of one page in which the virtual page address of the address to be registered by the adjacent page detection means and the physical page address are both adjacent is stored in the translation table. Since the flag changing means detects the existence and changes the flag means included in the adjacent page entry detected in response to the output of the adjacent page detecting means to the address conversion result in units of two pages, it is fast. The number of entries used by the address translation mechanism can be reduced and the translation efficiency can be improved.

[0006]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention. This embodiment shows an example of a full-associative high-speed address conversion mechanism, and FIG. 1 shows a certain entry.

In FIG. 1, reference numeral 1 is a virtual address register for holding a virtual address to be translated. Reference numeral 2 is a conversion table for high speed address conversion. The entry of the conversion table 2 is composed of 5 fields. That is,
A V bit indicating that the entry is valid, a flag indicating the attribute of the page, and a multi-page (MP) bit indicating whether the entry is an entry in units of one page or an entry based on two pages , A virtual page address part and a corresponding physical page address part. Reference numeral 3 is a page address comparator in units of one page in the virtual page address section, 6 is a page address comparator in units of two pages, and 4 is a selector for selecting the outputs of the comparators 3 and 6. Reference numeral 5 is an AND gate that takes the logical product of the output of the selector 4 and the V bit of the conversion table 2, 8 is a physical address generation coupler in units of 1 page, and 9 is a physical address generation coupling in units of 2 pages. It is a vessel. Reference numeral 10 is a selector for selecting the outputs of the combiners 8 and 9 and outputting the physical address. Reference numeral 7 is a comparator for comparing the page address of the physical address in units of two pages, 12 is a comparator for checking the virtual page address of the conversion table 2 and an odd or even page of the physical page address, and 13 is a virtual page to be registered. Reference numeral 11 is a comparator for confirming an odd or even page of an address and a physical page address, and 11 is an AND gate for notifying this signal (NEIGHBOR), which is constituted by the above.

In the case of FIG. 1, the above-mentioned comparator, selector, AND gate, etc. are shown for one entry of the conversion table 2 as an example for simplification of description, but in reality, they are shown in the figure. Not exist for each entry.

Next, the operation of indexing the address conversion table will be described.

The comparator 3 compares the page address part of the virtual address stored in the virtual address register 1 with the virtual page address part of the translation table entry. In the comparator 6, the part excluding the least significant 1 bit of the page address of the virtual address stored in the virtual address register 1 matches the part excluding the least significant 1 bit of the virtual page address part of the translation table entry. Compare if there is. That is, the comparator 6 determines whether or not the virtual addresses match in units of two pages. The selector 4 selects the output of the comparators 3 and 6 according to the value of the MP bit of the conversion table entry. When the MP bit is 0, the page address registered in the conversion table 2 is in units of one page, so the output of the comparator 3 is selected, and the MP bit 1
At this time, since the page address registered in the conversion table 2 is a unit of two pages, the output of the comparator 6 is selected.

The AND gate 5 calculates the logical product of the output of the selector 4 and the V bit of the conversion table 2 and sends a hit signal for a valid conversion table entry through the signal line L1. On the other hand, the combiner 8 combines the in-page address of the virtual address stored in the virtual address register 1 and the physical page address part included in the conversion table 2 to generate a physical address. Also, the combiner 9 combines the least significant bit of the page address of the virtual address stored in the virtual address register 1, the in-page address, and the part of the physical page address included in the conversion table 2 excluding the least significant 1 bit. A physical address is generated in units of 2 pages. The selector 10 selects the output of the combiner 8 and the combiner 9 according to the value of the MP bit of the conversion table entry, and outputs it as a physical address corresponding to the output of the signal line L1.

Next, the operation of registration in the address conversion table will be described. When no hit is reported from the AND gate 5 through the signal line L1 as a result of indexing the address conversion table 2, it means that the physical address corresponding to the virtual address held in the virtual address register 1 is not stored in the address conversion table 2. Become. At this time, the corresponding physical page address is obtained by indexing the address translation page table based on the virtual address stored in the virtual address register 1, and the result is registered in the translation table 2. At the time of registration in the address conversion table 2, a search is performed to see if an adjacent page address has already been registered in the conversion table 2. The output of the comparator 6 indicates that the page address of the 2-page unit of the virtual address matches the page address of the 2-page unit of the virtual page address part stored in the conversion table 2. Further, the comparator 7 indicates that the page address of the physical address obtained by indexing the page table in 2-page units matches the page address of 2-page units in the physical page address section stored in the conversion table 2. .. The comparator 12 indicates that both the virtual page address and the physical page address registered in the conversion table 2 are in the odd page or the even page. The comparator 13 indicates that both the virtual page address and the physical page address to be registered in the conversion table are on the odd page or the even page. The AND gate 11 includes comparators 6, 7, 12,
The output of 13 and the V bit of the conversion table 2 are ANDed and a coincidence signal for a valid conversion table entry is notified through the signal line L2. This signal (NEIGHBOR)
When this is notified, the registration in the address conversion table 2 is not performed for a new entry but for the entry of the translation table to which the NEIGHBOR signal is output. That is, 1 is set in the MP bit of the corresponding entry that performs degeneration (invalidation processing) of some pages, and registration is performed in units of 2 pages.

In this embodiment, the high-speed address translation mechanism of the full associative structure has been described, but the same can be realized by the set associative structure / direct mapping.

[0015]

As described above, according to the present invention, in an information processing apparatus having a high speed address translation mechanism, the translation table entry included in the high speed address translation mechanism can be used to display the address translation result in units of one page or two pages. A flag means indicating which is the conversion means, a conversion table indexing means for indexing the conversion table corresponding to the output of the flag means, and a virtual page address of an address to be registered when registering the address conversion result in the conversion table. Adjacent page detection means for detecting the existence of an address conversion result entry in the conversion table in units of one page in which both the physical page address and the adjacent physical page address are adjacent, and the adjacency detected in response to the output of the adjacent page detection means. Address conversion result in units of two pages for the flag means included in the page entry By a flag change means for changing, there is an effect that efficiently address conversion table by reducing the number of used entries degenerated two entries fast address translation buffer for the adjacent page in one entry can be used.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 1 Register 2 Address Conversion Table 3, 6, 7, 12, 13 Comparator 4, 10 Selector 5, 11 AND Gate 8, 9 Coupler

Claims (1)

[Claims] 1. An information processing apparatus having a high-speed address conversion mechanism, and flag means for indicating whether an entry of a conversion table included in the high-speed address conversion mechanism is one page or an address conversion result in units of two pages. , A conversion table indexing means for indexing the conversion table corresponding to the output of the flag means, and a virtual page address and a physical page address of an address to be registered are adjacent when registering an address conversion result in the conversion table. Adjacent page detecting means for detecting the existence of an address conversion result entry in units of one page in the conversion table, and the adjacent page entry detected in response to the output of the adjacent page detecting means. Flag for changing the flag means to the address conversion result in units of two pages. An information processing apparatus having a group changing unit.