JPH05173688A - Key input device - Google Patents

Abstract

PURPOSE:To inhibit a reset signal, generated periodically by a watchdog timer, in certain specific operation such as key input operation. CONSTITUTION:A watchdog signal WD and a signal which generates a Low level in the certain specific operation are inputted to an AND gate 5, which outputs the reset signal when the both are at a High level. Consequently, a device for key input operation such ash remote control transmitter can be reset in the key input operation regardless of the watchdog timer 6 and by the watchdog timer 6 at other times. For example, the key switch of the remote control transmitter is pressed and then released to put the watchdog timer 6 in operation immediately, thereby automatically resetting the transmission of a remote control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used to prevent malfunction. In particular, the present invention relates to a technique for preventing malfunction of the CPU of a device that involves key input operation. In particular, it is suitable for use as a remote control transmitter.

[0002]

2. Description of the Related Art A watchdog timer is constructed independently of the rest of the circuit, and the watchdog timer keeps counting while the circuit is operating, and after a certain period of time, the entire circuit must be reset. There is something to call. Since the watchdog timer of this system always resets after a certain period of time, it can always recover even if the circuit goes out of control. However, it is not often used because there is a constraint that it cannot be performed even when it is desired to perform a process longer than the count-up time of the watchdog timer.

A conventional device will be described with reference to FIG. FIG. 4 is a block diagram of a conventional example device.

The ROM 11 stores software for operating the circuit. The instruction decoder 12 decodes the instruction from the ROM 11 and sends a signal to each part of the circuit. Watchdog timer 13
It is composed of a plurality of flip-flops with reset, and generates a watchdog signal WD when counting up. In the watchdog timer having this configuration, an instruction for resetting the count value of the watchdog timer is prepared in advance in the instruction for operating the circuit, and when the instruction decoder 12 decodes this instruction, the count value of the watchdog timer 13 is reset. Signal RW for delaying the generation of the watchdog signal WD. That is, when the software creator creates the software, the software execution time is calculated, and the software is created so as to execute the instruction to reset the watchdog timer 13 just before the watchdog timer 13 counts up. If the circuit is out of control and the software is not executed in the order as scheduled, the timing for executing the instruction to reset the watchdog timer 13 is deviated, and the watchdog signal W
When D is generated, the entire circuit is reset.

[0005]

SUMMARY OF THE INVENTION In such a system,
In the former case, there is a problem that processing longer than the count-up time of the watchdog timer cannot be executed, and in the latter case, it is difficult to create software that is effective for detecting runaway, and the detection rate changes depending on the software. There is a problem that it ends up.

[0006] In various devices that operate by key input, the time during which the CPU accepts key input is not constant because the key operation speed of the person performing the key operation varies. In such a case, a watchdog timer configured to constantly generate a watchdog signal to reset the device is not appropriate. Correct resetting during key input operation will prevent proper key input. Will end up.

The present invention has been made against such a background, and an object thereof is to provide a key input device for inhibiting generation of a watchdog signal during a key input operation.

[0008]

According to the present invention, a key input circuit to which a plurality of key switches are connected, a CPU operated by an input from the key input circuit, an operation of the CPU is monitored, and a reset signal is sent. In the key input device, the monitoring circuit includes means for stopping transmission of a reset signal when an input is present in the key input circuit.

[0009]

The output side of the plurality of key switches is connected to the NOR gate having a plurality of gates corresponding to the output side. This N
The output of the OR gate becomes High level when there is no input in all of the key switches connected to the input side,
Lo if there is input from any one of the key switches
w level. The output of the NOR gate and the watchdog signal output of the watchdog timer are connected to the input side of the AND gate.

It is well known that the output of this AND gate also becomes High level when both of its two inputs become High level. As a result, the watchdog signal input to the AND gate is the reset signal only when both the high level signal of the watchdog signal and the high level signal from the NOR gate when there is no input in any of the key switches exist. As CPU
If any one of the key switches has an input, the watchdog signal is not output from the AND gate.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the device of the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

According to the present invention, a key input circuit 1 to which a plurality of key switches are connected, a CPU 2 which operates by an input from the key input circuit 1, and a monitoring circuit 3 which monitors the operation of the CPU 2 and sends a reset signal. In the key input device provided with, the monitoring circuit 3 is characterized by including a NOR gate 4 and an AND gate 5 as means for stopping the transmission of the reset signal R when an input is present in the key input circuit 1.

The monitoring circuit 3 uses the NOR gates 4 and A.
In addition to the ND gate 5, it is composed of a watchdog timer 6. The watchdog timer 6 is composed of a plurality of flip-flops, and generates a watchdog signal WD when the clock signal CK is input and counted up. The key input circuit 1 comprises an input terminal 8 with a pull-down resistor 7 and generates an input signal KI. The NOR gate 4 receives the input signal KI and generates the key input determination signal KJ. AN
The D gate 5 is a 2-input AND gate and a watchdog signal WD.
The key input determination signal KJ is input and the reset signal R is output.

Next, the operation of the apparatus of the present invention will be described with reference to FIG. FIG. 2 is a time chart showing the operation of the apparatus of the present invention. It should be noted that all the various signals of the apparatus of the present invention are rising edge detection signals.

The watchdog timer 6 has a clock signal C.
Divide K to obtain the number of flip-flop stages and clock signal C
The watchdog signal WD is generated every time determined by the frequency of K. Normally, this watchdog signal WD
Is regarded as the same as the system reset signal, and when this signal is generated, the entire circuit is reset. The key input circuit 1 has an input terminal 8 with a pull-down resistor 7.
Since there is no input from the outside, the input signal KI becomes the Low level, and the input signal KI becomes the High level only when there is the High level input from the outside. The key input circuit 1 of the device of the present invention is composed of four input terminals 8. The NOR gate 4 is composed of a 4-input NOR, and the input signal KI is all L level.
At the ow level, that is, when there is no key input, the key input determination signal KJ is at the high level, and when at least one of the input signals KI is at the high level, that is, when there is at least one key input, the key input determination is performed. The signal KJ becomes Low level. The 2-input AND gate 5 inputs the watchdog signal WD and the key input determination signal KJ, and when both signals are at the high level, that is, there is no key input and the watchdog signal W
The reset signal R is generated only when D is generated.
As a result, generation of the reset signal R during the key input operation is prohibited.

Next, an example in which the apparatus of the present invention is applied to a remote control transmitter will be described with reference to FIG. FIG. 3 is a block diagram when the apparatus of the present invention is applied to a remote control transmitter.

The apparatus of the present invention is particularly suitable for application to a remote control transmitter and the like. By using the device of the embodiment of the present invention for the remote control transmitter, the remote control signal is transmitted only while the key switch is being pressed, so that battery consumption can be prevented and the power supply of the remote control transmitter main body can be opened and closed. The switch can be omitted. Further, the device of the present invention is also applicable to a configuration in which the display of the operation content is output to the display unit only while the key switch of the remote control transmitter is pressed and the display is automatically stopped after the key switch is released. it can.

[0018]

[Effects of the Invention] By prohibiting the output of the watchdog timer while performing a key input operation, the watchdog timer's output can be maintained as long as the key is held down without resetting the count value of the watchdog timer by software. It is possible to continue processing for a time longer than the count-up time. In addition, the circuit configuration is simple and a reliable malfunction monitoring circuit can be easily configured. When applied to a remote control transmitter, it can be easily configured to send a remote control signal and output a display output only when a key switch is pressed.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the apparatus according to the embodiment of the present invention.

FIG. 3 is a block diagram when the device according to the embodiment of the present invention is applied to a remote control transmitter.

FIG. 4 is a block diagram of a conventional device.

[Explanation of symbols]

1 key input circuit 2 CPU 3 monitoring circuit 4 NOR gate 5 AND gate 6 watchdog timer 7 pull-down resistor 8 input terminal 11 ROM 12 instruction decoder 13 watchdog timer CK clock signal KI input signal KJ key input determination signal R reset signal RW watch Signal that resets the count value of the dog timer WD Watchdog signal

Claims (1)

[Claims] 1. A key input circuit to which a plurality of key switches are connected, a CPU that operates by an input from the key input circuit, and a monitoring circuit that monitors the operation of the CPU and sends a reset signal. In the key input device, the monitoring circuit includes means for stopping transmission of a reset signal when an input is present in the key input circuit.