JPH05173523A - Multiscreen display - Google Patents

Abstract

PURPOSE:To realize high picture quality by compensating luminance unevenness generated on a multiscreen display. CONSTITUTION:Screens of each core of a multiscreen display are divided into plural blocks respectively, and converters 4a-4d which compensates a video signal in every cores are provided. Data converters 4a-4d consist of LUTs (Look- Up Table), and adjust data of each data converter 4a-4d via the arithmetic controller 7 so that luminance unevenness in each core 6a-6d and between each core are eliminated. Furthermore, adjusting time is shortened by using arithmetic interpolation processing for adjusting data. Not only luminance unevenness, but also a video of a multiscreen display having little color unevenness and uniformity can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen display in which a plurality of image display devices are combined to form a single screen, and relates to a device for correcting unevenness in brightness and color in an image display device.

[0002]

2. Description of the Related Art As shown in FIG. 2, a multi-screen display in which a television set is stacked to form one screen has a shorter depth and a relatively higher brightness than a front projection type or rear projection type large screen display. , Used in event venues and showrooms. Individual television sets (hereinafter referred to as cores) are in practical use, such as cathode ray tube direct-view type and projection type. Among them, the projection type is more popular than the direct-view type because it is lighter in weight and has a flat screen surface. However, CRT type direct-view type and projection type cores generally have a specific brightness unevenness in which the peripheral part is darker than the center, and in particular, in the case of a multi-screen display, the variation is noticeable. In order to solve such a problem, for example, in Japanese Patent Laid-Open No. 57-111187, overscanning and superimposing are performed to compensate for the decrease in the brightness in the peripheral portion between the cores and to make the screen brightness uniform.

[0003]

However, in the above-mentioned conventional technique, it is necessary to match all the characteristics such as image alignment, convergence, distortion correction, etc. of the overscan portion between cores, and there is a problem to be solved in practice. Many. Therefore, the non-uniformity of brightness should be solved for each core.

[0004]

Therefore, in the present invention, each core is provided with a data converter that electrically corrects a video signal, and each data converter is connected to one arithmetic and control unit. The data conversion method of each data converter is controlled via the arithmetic and control unit so as to eliminate the uneven brightness every time.

[0005]

After the screen has a certain brightness, the arithmetic and control unit is operated to eliminate the brightness unevenness of each core.
Adjust the brightness unevenness for each core. After that, if further adjustment is made so that there is no difference in brightness between cores, the screen brightness can be made uniform. By repeating this operation while changing the brightness, it is possible to obtain a uniform image on the multi-screen display with no brightness unevenness and color unevenness at all brightness levels.

[0006]

FIG. 1 shows a first embodiment of the present invention.

FIG. 1 shows an example of a multi-screen display system using, for example, four cores, and the multi-screen screen can be constructed as shown in FIG. The cores 6a, 6
For b, 6c and 6d, for example, a CRT projection type television set can be used.

In FIG. 1, an A / D converter 1, a control circuit 2, a frame memory 3, data converters 4a and 4b,
4c, 4d, D / A converters 5a, 5b, 5c, 5
d, cores 6a, 6b, 6c, 6d and the first arithmetic and control unit 7. In the present embodiment, in particular, the cores 6a, 6b, 6 are provided by providing the arithmetic control unit 7 connected to the data converters 4a, 4b, 4c, 4d and the bus 9.
unevenness correction of the respective c and 6d and the cores 6a, 6b and 6
The feature is the correction of the uneven brightness between c and 6d. The data converters 4a, 4b, 4c and 4d include cores 6a, 6b, 6c,
In order to correct the uneven brightness of each of the 6d, the cores 6a,
Each screen of 6b, 6c, and 6d is divided into a plurality of blocks, and each block is provided with, for example, an LUT (look-up table). The arithmetic and control unit 7 can be composed of, for example, a microcomputer.

The outline of the operation of FIG. 1 is as follows. The video signal input to the terminal 10 is converted into a digital signal by the A / D converter 1 and written in the frame memory 3. The video signal written in the frame memory 3 is controlled and read by the control circuit 2. The video signals read out from the frame memory 3 are converted into data converters 4a, 4
b, 4c, 4d, and the cores 6a, 6b, 6c, 6
d uneven brightness correction and cores 6a, 6b, 6c, 6
d is converted into data in which the uneven brightness is corrected, and then D
The signals are converted into analog signals by the / A converters 5a, 5b, 5c and 5d and displayed on the cores 6a, 6b, 6c and 6d.

An example of a procedure for correcting unevenness in screen brightness will be described with reference to FIG. The correction procedure is shown in FIG.

As an example of the brightness unevenness of the cores 6a, 6b, 6c, 6d, the brightness unevenness in the central part and the peripheral part of the screen, which is often found in a CRT projection type television set as shown in FIG. 4, is taken up. .. Further, the screen of FIG. 4 is divided into 128 in the horizontal and vertical directions, for example, and the total is 1
It is assumed that it is divided into 6,384 blocks. Of course there is an LUT for each block.

First, the cores 6a, 6 are set to 100% brightness.
The uneven brightness in the core is corrected for each of b, 6c, and 6d. The uneven brightness of each core is corrected by, for example, 16,
The LUT data of 384 blocks is rewritten so that the brightness in the cores 6a, 6b, 6c, 6d becomes uniform. Of course, it may be rewritten one by one, but in consideration of usability, for example, as shown in FIG. 4, data for each LUT is calculated and rewritten by the arithmetic and control unit using a function such as a parabolic wave. May be. In this way, the uneven brightness in each core 6a, 6b, 6c, 6d is corrected, and then the uneven brightness in each core 6a, 6b, 6c, 6d is corrected. For example, on the basis of the brightness of the core 6a, the core 6
so that the brightness of b, 6c, and 6d is the same as that of the core 6a,
For example, the data of the data converters 4b, 4c, and 4d may be rewritten to a value obtained by adding or subtracting a certain level.

As a result of correcting the uneven brightness between the cores,
If brightness unevenness occurs in each core, brightness unevenness correction in each core is performed again, and brightness unevenness correction between cores is performed. This is repeated until the entire surface becomes uniform.

In this way, the data converters 4a, 4
In the LUTs b, 4c, and 4d, the correction data for making 100% luminance uniform is fixed. By performing the brightness correction according to the above procedure for a plurality of brightness levels up to 0% brightness, it is possible to obtain a uniform image display without brightness unevenness.

It is apparent that the color unevenness in the screen can be corrected by correcting the brightness unevenness at each brightness while taking the white balance.

As described above, it is possible to obtain a uniform multi-screen display without uneven brightness and uneven color.

The data converters 4a, 4b, 4c, 4d.
Although the input of is the output of the frame memory 3, the present invention can of course be applied to the case where an A / D converter is provided for each of the data converters 4a, 4b, 4c and 4d to input different video signals. Also, for example, if a core having a digital input / output terminal is used, the output of the data converter can be directly input to the core without D / A conversion, and the D / A converters 5a, 5b, 5c,
5d becomes unnecessary.

Needless to say, the number of cores can be arbitrarily selected, the number of data converters can be increased according to the number of cores, and the data converters can be connected to the arithmetic and control unit 7 via the bus 9.
Even with a multi-screen display including an arbitrary number of cores, it is possible to obtain a uniform image display without uneven brightness or uneven color.

A second embodiment of the present invention is shown in FIG. Figure 5
Are the data converters 4a, 4b, 4c, 4 of the embodiment of FIG.
A specific configuration example for each of d (data converter 4a,
4b, 4c, and 4d may have the same configuration). The feature of the present embodiment is that the memory capacity of the LUT used for the data converter is reduced and the data rewriting time is shortened by using the interpolation.

For example, assuming that the digital image signal is composed of 8 bits per pixel (0 to 255 gradations) and the luminance of the peripheral portion is about 75% with respect to the central portion of the screen, the central portion and the peripheral portion are It is necessary to correct the partial difference in luminance of 25% (64 gradations). In order to prevent the problem that the difference in the correction curve between blocks causes a difference in brightness at the junction (boundary region) of the blocks to be conspicuous, for example, if the correction between blocks is set to about 1 gradation, the difference from the central portion to the peripheral portion is reduced. The number of divisions is 6
The number of blocks is 4, which is 128 × 128 = 16,384 blocks obtained by dividing the entire display screen into 128 both horizontally and vertically.

If 8-bit correction data for 256 gradations is required for each of the three primary colors for each block, the LUT requires a large amount of data of 16,384 × 256 × 8 × 3 = 96 Mbits ( Regarding the memory capacity, by convention, 1024 bits = 1 Kbit, 1024 Kbi
It is shown in units of t = 1 Mbit).

Therefore, the block having the correction data and the block having no correction data are divided, and the data of the block having no correction data is obtained by interpolation from the block having the correction data. As a result, for example, if correction data is stored only in 4 × 4 = 16 blocks,
Compared with the method of providing correction data in 16,384 blocks, the memory capacity for storing the correction data is about 1 /
It can be reduced to 16 and the data rewriting time becomes 1/16.

The configuration of FIG. 5 will be described. In FIG. 5, 2
1a and 21b, 21c and 21d are LUTs, 23a and 23
b, 23c and 23d are coefficient adding circuits, 28 is an adder, terminals 35R, 35G and 35B are digital video signals RGB
Input terminal.

For example, R (red) 8b of the frame memory 3
The digital video signal output of it is the LUT 21a, 21
For example, it is input in parallel to lower addresses of b, 21c, and 21d.

A horizontal drive pulse and a vertical drive pulse indicating a display position in one screen are applied to the terminals 31h and 31v of the address circuit 22. The horizontal drive pulse and the vertical drive pulse may be, for example, a horizontal data read clock and a vertical data read clock of the frame memory 3.

The address circuit 22 creates horizontal block position data and vertical block position data indicating block positions divided into screens from the horizontal drive pulse and the vertical drive pulse applied to the terminals 31h and 31v, and based on the block position data. LUT control signals 25a, 25b, 25c,
25d is input to, for example, an upper address of the LUTs 21a, 21b, 21c, 21d. As a result, LUT21
a, 21b, 21c, and 21d are data-converted 4
Video signals 30a, 30b, 30c, 30d for blocks
Is obtained. At the same time, the address circuit 22 determines the coefficient selection signals 26a, 26b, 2 based on the block position data.
6c and 26d are coefficient adding circuits 23a, 23b, 23c,
23d, and a predetermined coefficient for the coefficient selection signal is supplied to the video signals 30a, 30b, 30c, 30 for the four blocks.
For example, signals 27a, 27b, 27c, which are multiplied by d,
You get 27d. By adding these signals to the adder 28 and adding them, a spatially interpolated digital video signal 29 corresponding to the block position is obtained. This is converted into an analog signal by, for example, a D / A converter and input to the core to obtain an image. Although the block 24R has been described, the same operation may be performed for 24G and 24B.

On the other hand, the bus 9 has LUTs 21a, 21b, 2
1c, 21d, address lines 25a, 25b, 25c,
25d, 33 and buses 30a, 30b, 30c, 30d
In addition, the buses 26a, 26b, 26c, 26d and the buses 27a, 27 of the coefficient circuits 23a, 23b, 23c, 23d.
b, 27c and 27d, and via this bus 9, the LUT 21, the coefficient adding circuit 23 and the arithmetic and control unit 7
For example, data is transmitted and received using the blanking period of the video signal to correct the uneven brightness of the screen.

The operation of the data converter configured as described above will be described below.

FIG. 6 is a diagram for explaining the operation of FIG. 5, for example, by interpolation from four adjacent blocks having correction data,
The corrected digital video signal eij of the block having no correction data is obtained.

In FIG. 6, i and j indicate vertical and horizontal block positions, respectively, and hereinafter, the block position is represented by (i,
The coordinates of j) are shown. Circles are written in each block of horizontal and vertical 4 blocks having correction data.

LUTs 21a, 21b, 21c, 21d
Are (8m, 8n), (8m + 4, 8n),
It is assumed that correction data of blocks (8m, 8n + 4) and (8m + 4, 8n + 4) are stored (where m and n are integers of 0 or more).

At this time, in the range of 0 ≦ i, j ≦ 4,
Four blocks (0,
0), (0, 4), (4, 0), (4, 4) correction data a00, b04, c40, d44 are used to generate a video signal eij for the input video signal of the (i, j) block. For example, it can be obtained by two-dimensional linear interpolation as in the following equation.

[0033]

[Equation 1]

That is, the digital video signals a00 and b0
A corrected digital video signal eij is obtained by multiplying 4, c40 and d44 by a predetermined coefficient and then adding them. The circuits for multiplying and adding the coefficients are the coefficient adding circuits 23a, 23b, 23c, 23d and the adder 28. As described above, a00, b04, c40, d
Since 44 is the data for which the uneven brightness is corrected, the video signal eij interpolated from these is also corrected for the uneven brightness.

Next, the operation of the coefficient adding circuit will be described by taking the coefficient adding circuit 23a as an example.

As shown in FIG. 5, the coefficient addition circuit 23a receives the output video signal 30a of the LUT 21a (corresponding to the video signals a00 and a08 in FIG. 6) and the coefficient selection signal 26a of the address circuit 22. This is a circuit for obtaining output data corresponding to the first term in the equation (1). FIG. 7 summarizes these relationships and is a diagram showing the output data of the coefficient adding circuit 23a in the first embodiment. Like the LUT, the coefficient adding circuit can be realized by, for example, a memory, and the 8-bit video signal 30a that switches to the video signals a00, a08, a80, etc. according to the block position is set to, for example, the lower address, and the address i and j indicating the block position are set. Lower 3 bits
For example, a total of 6 bits may be given to the upper address, for example.
With this 14-bit address and 8-bit data structure, the memory capacity of the coefficient adding circuit 23a is 16K.
bit × 8 = 128 Kbit is required. At this time, LU
2Mbit + 128Kbit including the memory capacity of T
× 4 = 2.5 Mbit, 2.5 Mbi for 3 primary colors
t × 3 = 7.5 Mbit, which can be greatly reduced compared to the above-described 96 Mbit when considering the entire system.

Now, referring to FIG. 7, the coefficients required for the coefficient adding circuit 23 are 0, 1/16, 1/8, 3/16,
1/4, 3/8, 1/2, 9/16, 3/4, 1 of 10
You can see that there are only types. Therefore, by devising the coefficient selection signal, the lower 3b of the addresses i and j indicating the block position when the coefficient adding circuit 23 is configured by a memory.
Since it is not necessary to use 64 types of coefficient selection signals of 6 bits each but 10 types, the memory capacity of the coefficient adding circuit is 25.
6 × 10 × 8 = 20 Kbit, which can be reduced to 1/6 of 128 Kbit described above.

Hereinafter, based on this memory capacity reducing method, the specific circuit configuration and operation of the address circuit 22 in the embodiment of FIG. 5 and the coefficient adding circuits 23a, 23b, 23c,
The operation of 23d will be described.

FIG. 8 is a block diagram showing a configuration example of the address circuit 22. A horizontal drive pulse and a vertical drive pulse are applied to the input terminals 31h and 31v, respectively, and the frequency dividers 41h and 41v obtain a horizontal block pulse 42h and a vertical block pulse 42v. Horizontal block pulse 4
By dividing 2h by the frequency divider 43h and the frequency divider 44h, the lower 3bit signal 45h of the horizontal block position j is obtained.
Is obtained and is given to the lower addresses of the decoders 46a, 46b, 46c and 46d. Similarly, vertical block pulse 4
By dividing the 2v by the 4 divider 43v and the 2 divider 44v, the lower 3bit signal 45v of the vertical block position i
Is obtained and is given to the upper addresses of the decoders 46a, 46b, 46c and 46d. Decoders 46a, 46b, 46
c and 46d are lower 3 of horizontal and vertical block positions i and j
From the bit signals 45h, 45v to the coefficient adding circuits 23a, 2
4 bit coefficient selection signals 26a, 26b, 26c and 26d are provided to 3b, 23c and 23d, respectively.

The output signal of the 2 frequency divider 44h is further divided by 16 by a 16 frequency divider 48h, and the upper 4 bit signal 49h of the horizontal block position j is used as the lower control signal of the LUT control signals 25a and 25c of the LUTs 21a and 21c. .. A signal 51h obtained by delaying the upper 4-bit signal 49h at the horizontal block position j by a delay circuit 50h is used as LUTs 21b and 21d.
LUT control signals 25b and 25d are used as lower control signals. The delay circuit is used because each LUT has correction data for every 8 horizontal blocks, and LUTs 21a and 21c are provided.
On the other hand, the corresponding blocks of the correction data stored in the LUTs 21b and 21d are offset by 4 horizontal blocks. Similarly, the output signal of the divide-by-two frequency divider 44v is further divided by 16 by the divide-by-16 frequency divider 48v, and the upper 4-bit signal 49v at the vertical block position i is converted into LUTs 21a and 21.
It is used as an upper control signal of the LUT control signals 25a and 25b of b. Upper 4-bit signal 49 of horizontal block position i
v is delayed by the delay circuit 50v and the signal 51v is delayed by the LUT2.
It is used as a lower order control signal for LUT control signals 25c and 25d for 1c and 21d.

[0041]

[Table 1]

[0042]

[Table 2]

[0043]

[Table 3]

[0044]

[Table 4]

[0045]

[Table 5]

Table 1 is a table showing the correspondence between the coefficient selection signal input to the coefficient adding circuit and the above 10 kinds of coefficients. A 4-bit coefficient selection signal is used to select 10 types of coefficients, which are the coefficient selection signals 23a, 23b,
It corresponds to 23c and 23d. By defining in this way, as described above, the circuit scale of the coefficient addition circuit is 20 Kbi.
can be t. Table 2 shows the relationship between the vertical and horizontal block positions i and j and the coefficient selection signal using the coefficient selection signal of Table 1 based on the output data of the coefficient adding circuit 23a of FIG. This is an input / output table for the decoder 46a. Similarly, the input / output tables of the decoders 46b, 46c and 46d are obtained as shown in Table 3, Table 4 and Table 5. These decoders can also be realized as a LUT using a memory,
At this time, the memory capacity is 64 × 4 = 256 bits because the address is 6 bits in total of the lower 3 bits of the vertical and horizontal block positions i and j, and the output data is 4 bits.

Summarizing the above results, the above 128 × 1
When 28 blocks are used, the memory capacity required per color is such that the LUT is 0.5 Mbit × 4 = 2 Mbit,
The coefficient adding circuit is 20 Kbit × 4 = 80 Kbit, and the address adding circuit 256 × 4 = 1 Kbit, which is 2.1 Mbi in total.
t, which is 2.1 Mbit × 3 = even if the three primary colors are taken into consideration.
It can be configured with 6.3 Mbit. In this way, the above-mentioned 96M
The memory capacity can be reduced to about 1/16 of the bit,
The time required for rewriting the LUT data by the arithmetic and control unit 7 can be shortened, and the time for adjustment work can be shortened.

The third embodiment of the present invention is shown in FIG. Figure 9
Shows the adjustment procedure of the luminance unevenness correction using interpolation.
The adjustment of the brightness unevenness correction can be accurately performed in a short time.

In the first embodiment, the luminance unevenness correction is performed for each luminance. If, for example, the video signal has 8 bits, the number of gray scales of luminance that can be obtained is 256 and 256.
This is a problem in practice, as it requires repeated adjustment work. Therefore, from the adjusted brightness correction data, the uncorrected brightness correction data is obtained by interpolation to reduce the number of adjustment operations.

Hereinafter, the procedure for correcting unevenness in brightness will be described by taking a multi-screen display including four cores as shown in FIG. 2 (the circuit configuration is, for example, FIG. 1) as an example.

In FIG. 9, first, 100% luminance display is performed, and the cores 6a, 6b, 6c and 6d are formed as in the first embodiment.
Each uneven brightness correction and the cores 6a, 6b, 6c, 6
d Mutual luminance unevenness correction is performed. Next, 0% luminance is displayed and luminance unevenness correction is performed as in the case of 100% luminance.
Then, the correction data between 100% brightness and 0% brightness is set to 1
From the correction data of 00% brightness and 0% brightness, for example, a linear expression or a curve expression such as the following expression

[0052]

[Equation 2]

It is calculated by using and is written in the data converters 4a, 4b, 4c, and 4d as luminance unevenness correction data between 100% luminance and 0% luminance. If the voltage-luminance characteristics from 100% luminance to 0% luminance are uniform in the screens of the cores 6a, 6b, 6c, 6d or between the cores 6a, 6b, 6c, 6d, respectively, Even if the display is performed with an appropriate luminance, the uniformity of the screen luminance should be maintained by the correction data obtained by the above interpolation.

Therefore, for example, halftone display of 50% brightness is performed to confirm the uniformity of screen brightness. At this time, if the screen brightness is not uniform, the uneven brightness correction at 50% brightness is performed in the same manner as at 100% brightness and 0% brightness so as to be uniform. And 100% brightness, 0% brightness and 50
With 100% luminance unevenness correction data, 100% again
Brightness unevenness correction data of brightness to 50% brightness and 50% brightness to 0% brightness is obtained by interpolation, and data converters 4a, 4b,
Rewrite the data of 4c and 4d. This can improve the accuracy of interpolation.

Further, for example, 25% brightness, 75% brightness ...
By increasing the number of points for actually performing the luminance unevenness correction while looking at the screen, the accuracy of interpolation can be further increased, and the luminance unevenness can be made to be inconspicuous at an appropriate halftone luminance. With this, for example, the uneven brightness correction work is performed only for 5 points of 100% brightness, 75% brightness, 50% brightness, 25% brightness, and 0% brightness, and for other brightnesses, the uneven brightness correction data is obtained by interpolation. , The number of user adjustment work can be drastically reduced from 256 to 5.
It is possible to significantly reduce the adjustment time.

FIG. 10 is a diagram showing an image of the procedure for correcting the luminance unevenness described with reference to FIG. Horizontal and vertical screen positions are shown on the X and Y axes, and brightness is shown on the Z axis. Figure 10
2 has the same configuration as that of FIG. 2, which means that the X-axis and the Y-axis are equally divided into two and one screen is configured by four cores. or,
The screens 60 to 67 in the Z-axis direction mean the brightness levels on the screen, for example, a screen with 0% brightness is 60, 1.
A screen having a brightness of 00% is 67.

First, the uneven brightness correction work is performed on the screen 60 having 100% brightness. Next, the uneven brightness correction work is performed on the screen 67 having 0% brightness. As a result, the correction data 70 and 72 of 100% brightness and 0% brightness at the same spatial position are fixed. From the correction data 70 and 72, the correction data at 100% to 0% brightness at this spatial position is obtained by interpolation. Then, for example, a screen 64 of 50% brightness
Is displayed. The correction data 71 is obtained by interpolation, but if there is brightness unevenness at this time, the brightness unevenness correction work is actually performed on the screen 64 of 50% brightness, and the brightness unevenness correction data is rewritten. Then, the correction data of the other brightness is obtained again by interpolation. Of course, the same applies to correction data for other spatial positions.

A fourth embodiment of the present invention is shown in FIG.

This is the data converter 4a, 4b, 4c, 4
In order to obtain the data to be written in d by, for example, interpolation calculation, the second calculation control devices 107a, 107b, 107c, dedicated to the respective data converters 4a, 4b, 4c, 4d,
107d is provided. Therefore, the arithmetic and control unit 7 need only give, for example, a calculation command to the arithmetic and control units 107a, 107b, 107c, 107d, and the data converter 4
Since processing such as data calculation of a, 4b, 4c, and 4d is not performed, the processing speed becomes faster, the adjustment time can be shortened, and the burden on the adjuster can be reduced.

The arithmetic and control unit 7 and the arithmetic and control unit 10
The amount of information transmission between 7a, 107b, 107c and 107d is small, and quick adjustment work can be performed using a serial interface such as RS-232C. Since other operations are the same as those in the first embodiment, the description will be omitted.

FIG. 12 shows the fifth embodiment. This is one in which the part that relied on human eyes for the adjustment work was replaced with a light receiving device such as a television camera 80, and the adjustment work was automated.

In FIG. 12, the multi-screen display is captured by the television camera 80, and the output information is arithmetically processed by the third arithmetic and control unit 207 to adjust the video signal expander 118 so that the unevenness in brightness is reduced. .. The video signal expander 118 can be realized by a circuit as shown in FIG. 1, for example. The procedure of the arithmetic processing of the arithmetic and control unit 207 may be the same as the work procedure shown in FIG. 9, for example, and the arithmetic and control unit 207 may be operated by software according to this procedure. Further, a small light receiver may be arranged at a predetermined position on the screen instead of the television camera shown in FIG.

According to this method, the brightness unevenness can be automatically adjusted without the need for the adjuster to move.

A sixth embodiment of the present invention is shown in FIG. The feature of this embodiment is that the data converter 4 and the second arithmetic and control unit 107 are provided inside each of the cores 6a, 6b, 6c and 6d.

The structure of FIG. 13 is shown. 6a, 6b, 6c,
6d is a core, 301 is a video expansion and distribution device, 7 is a first arithmetic and control unit, and 10 is a video signal input terminal. The image enlarging distribution device 301 is a device that distributes the image signal applied to the terminal 10 to each core 6a, 6b, 6c, 6d, and may have the configuration of FIG. 1, for example. However, since the data converters 4a to 4d are built in the core, the data converters 4a to 4d do not have to be provided inside the image enlarging distribution device 301, and the output of the frame memory 3 may be directly input to the D / A converters 5a to 5d.

The internal configuration of each core 6a, 6b, 6c, 6d is as follows: video signal input terminal 100a, A / D converter 60
a, data converter 4a, D / A converter 61a, video circuit 62a, CRT (cathode ray tube) drive circuit 63a, C
RT64a and the second arithmetic and control unit 107 dedicated to the core
made of a. The video circuit 62a is a circuit that adjusts the contrast, brightness, and the like of the video signal. The CRT drive circuit 63a outputs the output signal from the video circuit 62a,
It is an amplifier that makes the voltage level necessary to drive the CRT 64a. The video circuit 62a, the CRT drive circuit 63a, and the CRT 64a may be circuits used in television sets currently on the market. The first arithmetic and control unit 7 and the second arithmetic and control unit 107a are, for example, RS-23.
It is connected to the terminal 200a by a serial interface such as 2C.

The data converter 4a, the first arithmetic and control unit 7 and the second arithmetic and control unit 107a may be the same as in the first embodiment, and the details of the operation are as described above.

The outline of the operation of FIG. 13 is as follows.
The image enlarging distribution device 301 distributes the image signal input from the terminal 10 and sends the distributed image signal to each core 6a, 6b, 6c, 6d. The video signal sent to the core 6a is converted into a digital signal by the A / D converter 60a and input to the data converter 4a. The data converter 4a converts the data so as to correct the uneven brightness of the core 6a, and the D / A converter 61a converts the data into an analog signal. The video signal whose brightness unevenness is corrected passes through the video circuit 62a and the CRT drive circuit 63a, and then the CRT 64.
Displayed by a. The procedure for correcting unevenness in brightness within and between cores by the first arithmetic and control unit 7 is as described in the first embodiment.

According to this embodiment, since the data converter 4a is built in the core 6a, no data converter is required in the image enlarging / distributing device 301, and the image enlarging / distributing device 301 can have a simple structure. In this embodiment, the first arithmetic and control unit 7 and the image enlarging and distributing unit 301 are separate, but the first arithmetic and control unit 7 may be incorporated into the image enlarging and distributing unit 301 to simplify the device arrangement. ..

A seventh embodiment of the present invention is shown in FIG. The feature of this embodiment is that the contrast of the video circuit or the brightness control terminal is modulated by the data generator 67a.
The purpose is to correct uneven brightness. Note that FIG. 14 shows the configuration of only the core 6a, and the entire configuration such as wiring to the image enlarging / distributing device may be the same as that of FIG. The adjustment procedure using the first arithmetic and control unit 7 may be the same.

FIG. 14 shows an address circuit 66a, a data generator 67a, a D / A converter 68a, and a sync separation circuit 65.
a, the contrast of the video circuit 62a, or the brightness control terminal 300a.

The sync separation circuit 65a extracts horizontal and vertical sync signals from the video signal input from the terminal 100a,
It is sent to the address circuit 66a, and the address circuit 66a
From the input horizontal and vertical sync signals,
Position data divided into 28 × 128 blocks is created. The data generator 67a outputs luminance unevenness correction data for each block of the screen divided into 128 × 128 blocks based on the block position data.
The brightness unevenness correction data output from the data generator 67a is converted into an analog signal by the D / A converter 68a, and the contrast or brightness of the video circuit 62a is modulated. Needless to say, this modulation refers to the terminal 100a.
The multiplication of the video signal applied to the data generator 67a and the data of the data generator 67a, that is, the analog signal of the luminance nonuniformity correction data, is performed by a large circuit as compared with the digital signal multiplication of the first and second embodiments. Simplification is achieved. Of course, since the brightness unevenness correction data is in the data generator 67a, it is possible to arrange any data, and it is possible to perform accurate correction that is not in the conventional parabola signal correction.

The eighth embodiment of the present invention is shown in FIG. The feature of this embodiment is that the D / A converter 68a in the core 6a is
This is because a low-pass filter (LPF) 400a was connected to the output side of the above to reduce the number of horizontal correction block divisions. Other configurations and operations are shown in FIGS.
The same as

As described above, in the luminance correction step between blocks, the luminance difference between the blocks does not occur,
For example, since the gradation is about one, 128 blocks are required for horizontal and vertical division. Therefore, the L.O. P. F400a is connected to smooth the luminance difference between horizontal blocks as shown in FIG. As a result, the number of blocks divided in the horizontal direction can be reduced, and the memory capacity of the data generator 67a can be reduced.

Although the CRT-type projection type TV set has been described as an example of the core as described above, the same effect can be obtained in a CRT-type direct view type TV set or a projection TV using a liquid crystal display element. it is obvious. In the case of a projection television set using a liquid crystal display element, it goes without saying that the data written in the LUT matches the voltage / luminance characteristic of the liquid crystal display element.

[0076]

As described above, according to the present invention, it is possible to obtain a uniform image on a multi-screen display in which not only the brightness unevenness but also the color unevenness is small.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a multi-screen display.

FIG. 3 is a PAD showing a procedure for correcting luminance unevenness.

FIG. 4 is a diagram showing an example of uneven brightness.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram for explaining the operation of the second embodiment.

FIG. 7 is an explanatory diagram of output data of the coefficient adding circuit 23a.

FIG. 8 is a diagram showing a configuration example of an address circuit 22.

FIG. 9 is a diagram illustrating a third embodiment of the present invention.

FIG. 10 is a diagram showing an image of a correction procedure.

FIG. 11 is a block diagram showing a fourth embodiment of the present invention.

FIG. 12 is a block diagram showing a fifth embodiment of the present invention.

FIG. 13 is a block diagram showing a sixth embodiment of the present invention.

FIG. 14 is a block diagram showing a seventh embodiment of the present invention.

FIG. 15 is a block diagram showing an eighth embodiment of the present invention.

FIG. 16 is a diagram illustrating an eighth embodiment of the present invention.

[Explanation of symbols]

1, 60a ... A / D converter, 2 ... Control circuit 3 ... Frame memory 4a, 4b, 4c, 4d ... Data converter 67a ... Data generator 5a, 5b, 5c, 5d, 68a ... D / A converter 6a, 6b , 6c, 6d ... Core 7, 107a, 107b, 107c, 107d ... Operation control device 21a, 21b, 21c, 21d ... LUT (look-up table) 22, 66a ... Address circuit 23a, 23b, 23c, 23d ... Coefficient addition circuit 28 ... Adder 41h, 41v, 43h, 43v, 44h, 44v, 4
8h, 48v ... Division cycle 50h, 50v ... Delay circuit 46a, 46b, 46c, 46d ... Decoder 80 ... Television camera 118 ... Video signal expander 301 ... Video expansion / distribution device 62a ... Video circuit 63a ... CRT drive 64a ... CRT 65a ... Sync separation circuit 400a ... Low-pass filter

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Takeshi Maruyama 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Hitachi Ltd. AV Equipment Division

Claims (8)

[Claims] 1. A multi-screen display in which a plurality of image display devices are combined to form a single screen, and data for converting video signal data digitally converted for each image display device in accordance with display characteristics of the image display device. A converter and a first for controlling the plurality of data converters
A multi-screen display characterized by being provided with the arithmetic and control unit of. 2. A multi-screen display in which a plurality of image display devices are combined to form one screen, and data for converting video signal data digitally converted for each image display device according to display characteristics of the image display device. The converter includes a plurality of look-up tables (LUTs) for storing display unevenness correction data for each of a plurality of blocks.
And a first arithmetic control for controlling the plurality of data converters, the interpolation processing circuit including a coefficient adding circuit and an adder that inputs a plurality of video signal data output from the plurality of look-up tables. A multi-screen display characterized by having a device. 3. A multi-screen display in which a plurality of image display devices are combined to form one screen, and data for converting digitally converted video signal data for each image display device according to the display characteristics of the image display device. A converter and a first for controlling the plurality of data converters
The multi-screen display, wherein the arithmetic control device is provided, and the correction data for the brightness other than the specific brightness is obtained by interpolation from the data of the data converter that corrects a plurality of specific brightness. 4. A multi-screen display in which a plurality of image display devices are combined to form one screen, and data for converting video signal data digitally converted for each image display device according to display characteristics of the image display device. A converter, a second arithmetic and control unit for performing data arithmetic processing for each data converter, and a first arithmetic and control unit for exchanging information with the plurality of second arithmetic and control units are provided. And a multi-screen display. 5. In a multi-screen display in which a plurality of image display devices are combined to form one screen, data for converting video signal data digitally converted for each image display device in accordance with display characteristics of the image display device. A converter and a third controlling the plurality of data converters
And a brightness detector for performing brightness detection on the screens of the plurality of image display devices and for inputting the brightness detected information to the third calculation control device. .. 6. A multi-screen display in which a plurality of image display devices are combined to form one screen, and data conversion for converting digitally converted video signal data of the image display device according to display characteristics of the image display device. And a second arithmetic and control unit that performs a data arithmetic process for each of the data converters inside the image display device, and transmits and receives information to and from the plurality of second arithmetic and control units. A multi-screen display characterized by having an arithmetic and control unit. 7. In a multi-screen display in which a plurality of image display devices are combined to form one screen, a data generator that generates data according to the display characteristics of the image display device, and the data generator is controlled. An address circuit, a D / A converter for converting a digital signal output of the data generator into an analog signal, a video circuit for modulating a video signal of the image display device with an output of the D / A converter, and the data Second data processing for each generator
And an arithmetic and control unit of the inside of the image display device,
A multi-screen display comprising a first arithmetic and control unit for exchanging information with the plurality of second arithmetic and control units. 8. In a multi-screen display in which a plurality of image display devices are combined to form one screen, a data generator that generates data according to the display characteristics of the image display device, and the data generator are controlled. An address circuit, a D / A converter that converts the digital signal output of the data generator into an analog signal, and an L.L. that smoothes the output of the D / A converter. P. F circuit and the L.F. P. F
A video circuit that modulates a video signal of the image display device by a circuit, and a second arithmetic control device that performs a data arithmetic process for each of the data generators are provided inside the image display device. A multi-screen display comprising a first arithmetic and control unit for exchanging information with the arithmetic and control unit.