JPH05167631A - Delay detection circuit for psk modulation wave - Google Patents

Abstract

PURPOSE:To improve demodulation characteristics without increasing a quantization bit number. CONSTITUTION:A phase data synthesizer 50 is provided in a post-stage of a phase data converter 14. The phase data synthesizer 50 adds M-bit phase data outputted from the phase data converter 14 while deviating its timing to expand the bit number into (M+N) bits so that a narrow angle intermediate value is obtained when the phase data are changed. The quantization bit number of the phase data is expanded simulatingly into the (M+N) bits and the demodulation characteristic to improve the resolution is enhanced. When the quantization bit number is not actually increased, it is not required to increase the oscillation frequency of a local master oscillator 10 to convert a PSK modulation wave into the phase data and the power consumption is not increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection circuit for differentially detecting a PSK modulated wave signal, and more particularly to improvement of means for converting a modulated wave signal into phase data.

[0002]

2. Description of the Related Art FIG. 6 shows a configuration example of a conventional differential detection circuit. The circuit shown in this figure is P
This is a circuit that performs differential detection of the SK modulated wave signal.

This conventional example comprises a local master oscillator 10 which oscillates at a predetermined frequency, and a phase data converter 14 which converts a PSK modulated wave signal fetched from an input terminal 12 into phase data. The phase data converter 14 is
The PSK modulated wave signal is converted into phase data by comparing the phase of the PSK modulated wave signal related to the carrier frequency of the frequency f ₀ with the phase of the local oscillation signal output from the local master oscillator 10.

On the other hand, the phase data converter 14 has a subtracter 1
6 is directly connected to one input (+), and is connected to the other input (−) of the subtracter 16 via the 1-symbol delay unit 18 on the other side.

The 1-symbol delay unit 18 converts the phase data to 1
Delay by the symbol time. The subtractor 16 takes in the phase data from the phase data converter 14, takes in the phase data delayed by the 1-symbol delay device 18, subtracts the latter from the former, and outputs the result as a phase difference signal.

The subtractor 16 is connected to the frequency error corrector 20. The frequency error corrector 20 is a circuit that corrects the frequency error of the phase difference signal caused by the difference between the transmission carrier frequency and the frequency of the local oscillation signal. The frequency error corrector 20 is further connected to the determiner 22.

The discriminator 22 determines 1, 0 based on the phase difference signal whose frequency error is corrected by the frequency error corrector 20.
This is a circuit for judging data. Therefore, the signal output from the determiner 22 to the output terminal 24 is the demodulated transmitted data.

The output of the judging device 22 is used for the correction of the frequency error in the frequency error correcting device 20. That is, the frequency error corrector 20 is connected to the subsequent stage of the subtractor 16 to correct the frequency error of the phase difference signal, and the frequency error corrector 26 outputs the frequency error based on the output of the frequency error corrector 26 and the determiner 22. And a averaging circuit 30 for averaging the output of the frequency error detecting circuit 28 and supplying a correction amount to the frequency error correcting circuit 26.

The frequency error correction circuit 26 includes an averaging circuit 3
It is an adder that adds the correction amount output from 0 to the phase difference signal output from the subtracter 16. If the frequency error correction circuit 26 has insufficient or excessive correction,
This deficiency or excess is detected by the frequency error detection circuit 28. The frequency error detection circuit 28 outputs phase data for proper correction, and the averaging circuit 3
When 0, the output of the frequency error detection circuit 28 is averaged to smooth the phase data variation due to noise or the like, and the correction amount is supplied to the frequency error correction circuit 26.

Here, in order to clarify the problems of this conventional technique, the circuit configuration and operation of the phase data converter 14 will be described.

FIG. 7 shows an example configuration of the phase data converter 14. The phase data converter 14 shown in this figure includes a frequency divider 32 and a shift register 34 in order to take in the output from the local master oscillator 10 and convert it into reference signals θ _{1 to} θ ₈ having different phases. There is. The local oscillation signal (m × f ₀ ) from the local master oscillator 10 is frequency-divided by the frequency divider 32 and supplied to the shift register 34 as a signal of frequency f ₀ . A local oscillation signal is input to the shift register 34 as a clock (CLK), and the shift register 34 shifts a signal having a frequency f ₀ according to the clock and outputs the reference signals θ _{1 to} θ ₈ having different phases. To do.

Further, the phase data converter 14 takes in the PSK modulated wave signal from the input terminal 12 and limits the voltage level, and the modulated wave signal output from the limiter 36 to the reference signals θ _{1 to} θ ₈ . .., 38-8 and eight phase comparators 38-1, 38-2, ..., 38-8 for comparison, and the phase of the modulated wave signal based on the outputs of the phase comparators 38-1, 38-2 ,. And a phase data determination circuit 40 that outputs the phase data as phase data.

Next, the operation of this conventional example will be described. FIG. 8 shows the phase data converter 1 according to this embodiment.
The operation of No. 4 is shown as a timing chart.

As shown in this figure, the reference signals θ _1-
θ ₈ has different phases by 45 °.
For example, the reference signal θ ₁ is 22.5 ° and the reference signal θ ₂ is 6
7.5 °, ... The reference signal θ ₈ has a phase of 337.5 °.

Here, consider the case where the modulated wave signal θ _n-1 is input in the (n-1) th symbol. At this time, the phase comparators 38-1, 38-2, ..., 38-8
, Respectively, are compared with the reference signals θ ₁ , θ ₂ , ..., And θ ₈ and the modulated wave signal θ _n-1 . If they match as a result of comparison, the phase comparators 38-1, 38-2, ..., 38-8 output H-level signals, and if they do not match, L-level signals are output.

When the modulated wave signal θ _n-1 has a phase of 170 °, for example, the phases of the reference signals θ _{1 to} θ ₄ are 170.
Since it is smaller than °, the outputs of the phase comparators 38-1 to 38-4 have an H value. However, since the phase of the reference signal θ ₅ supplied to the phase comparator 38-5 is 202.5,
The output of the phase comparator 38-5 has an L value. Similarly, the outputs of the phase comparators 38-6 to 38-8 also have L values. Therefore,
The signal supplied to the phase data determination circuit 40 is HHHHLLLL in the ascending order of the phase comparator 38. In the phase data determination circuit 40, the phase comparators 38-1 and 38
-2, ..., 38-8 is used to determine the range of the phase to which the modulated wave signal θ _n-1 belongs. in this case,
Since the signal supplied from the comparator 38-4 has an H value and the signal supplied from the phase comparator 38-5 has an L value, the phase of the modulated wave signal θ _n-1 is from 157.5 °. 20
It is determined to belong to the range of 2.5 °. In this case, the phase data determination circuit 40 outputs a value representative of the range of 157.5 ° to 202.5 °, for example 180 °, as the phase data.

Similarly, when the modulated wave signal θ _n is supplied in the n-th symbol, this modulated wave signal θ _n is 26
If it has a phase of 5 °, the phase comparator 38-1
The outputs of ~ 38-8 are HHLLLLLHH in order. The phase data determination circuit 40 makes a determination in the same manner as at timing n−1 and outputs 270 °, which is a value representative of 247.5 ° to 292.5 °, as phase data.

FIG. 9 shows another structural example of the phase data converter 14. FIG. 10 is an operation explanatory diagram of FIG. This configuration example is to count the phase difference by dividing the output of the local master oscillator 10 to obtain the local oscillation signal A ₁ and, PSK modulated wave and the local oscillation signal A _1.

In the configuration shown in this figure, the limiter 36 for limiting the voltage level of the PSK modulated wave taken in from the input terminal 12 and the local oscillation signal of frequency m × f ₀ outputted from the local master oscillator 10 are divided by m. The frequency divider 42 that outputs the local oscillator signal A ₁ having a frequency of f ₀ and the output of the limiter 36 to the set input (S) and the local oscillator signal A ₁ to the reset input (R) are input as digital signals, respectively. And a flip-flop (hereinafter referred to as FF) 44 that operates.

In this configuration example, the PSK modulated wave is supplied to the set input of the FF44, the local oscillator signal A ₁ whose phase is compared with this is generated by the local master oscillator 10 and the frequency divider 42, and the reset input of the FF44. Is supplied to. Therefore, as shown by B in FIG. 10, the positive pulse width of the Q output of the FF 44 in this configuration example is from the rise of the PSK modulated wave to the rise of the local oscillator signal A ₁ .

Further, this configuration example includes a counter 46 which receives the Q output of the FF 44 from the counter enable (CE) input and counts the output of the local master oscillator 10 having the frequency m × f ₀ as the count clock. For the reset input (RESET) of the counter 46,
The pulse A ₂ is supplied from the frequency divider 42.

Therefore, the counter 46 counts from the rising edge of the counter enable input (rising edge of the PSK modulated wave) to the falling edge of the reset input (falling edge of the pulse A ₂ ) with the clock of frequency m × f ₀ . The pulse output A ₂ of the frequency divider 42 that resets the counter 46 is synchronized with the rising edge of the local oscillator signal A ₁ .
As a result, the count value of the counter 46 becomes a value indicating the pulse width of the signal B, that is, the phase difference between the PSK modulated wave and the local oscillation signal A ₁ .

In this configuration example, a latch circuit 48 for latching the count value of the counter 46, an inverter 50 for inverting and supplying the pulse output A ₂ to the latch circuit 48,
Is equipped with. The latch circuit 48 latches the count value of the counter 46, and then the counter 46 is reset by the pulse output A ₂ to start the next phase comparison operation.

As described above, in this configuration example, the output of the latch circuit 48 becomes the output of the phase data converter 14 indicating the phase difference between the PSK modulated wave and the local oscillation signal A ₁ .

[0025]

In the conventional configuration, since the phase data converter has the above-described configuration, the modulation frequency f _{0 is set} as the oscillation frequency of the local master oscillator.
Was required m times. This m is m = 2 ^M, where M is the number of quantization bits of the phase data. The higher the quantization bit number M, the better the demodulation characteristics. On the other hand, in general, a digital circuit requires a process that consumes more power as the frequency increases, and in the same process, the power consumption increases as the frequency increases. Therefore, in the conventional configuration, in order to increase the number M of quantization bits, there is a problem that the increase in power consumption must be accepted.

The present invention has been made to solve the above problems, and by pseudo-increasing the number of quantization bits M, power consumption is suppressed and excellent demodulation characteristics are achieved. An object is to provide a delay detection circuit that can be obtained.

[0027]

In order to achieve such an object, the present invention provides a plurality of phase data relating to different timings obtained by a phase data converter, which indicates an intermediate value of the phase data and has M + N bits. (M, N; natural numbers)
It is characterized by comprising a phase data synthesizer for synthesizing into phase data composed of and supplying to a 1-symbol delay unit and a subtractor.

[0028]

In the differential detection circuit of the present invention, a plurality of phase data obtained by the phase data converter and relating to different timings are combined with the phase data composed of M + N bits, which represents an intermediate value of the phase data. Therefore, the resolution of the phase data is improved without increasing the number of quantization bits M, and M is increased in a pseudo manner (at the same frequency).

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. The same components as those in the conventional example shown in FIGS. 6 to 10 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 shows the configuration of a differential detection circuit according to an embodiment of the present invention. The circuit shown in this figure is an example of a 4-phase PSK differential detection circuit.

In this embodiment, a phase data synthesizer 50 is added between the phase data converter 14 and the subtractor 16 and the 1-symbol delay device 18 in the conventional example. The phase data synthesizer 50 synthesizes the output of the phase data converter 14 by a narrow-angle synthesizer described later to improve the resolution, and is a feature of the present invention.

FIG. 2 shows a structural example of the phase data synthesizer 50. Here, the output of the phase data converter 14 is 3 bits, that is, the input of the phase data synthesizer 50 is 3 bits. Further, the configuration of FIG. 9 is assumed as the phase data converter 14 (when the configuration of FIG. 7 is adopted, “the local oscillator signal A ₂ ” is replaced with “the output of the frequency divider 32” in the following description). Good).

The phase data synthesizer 50 in this figure is composed of shift registers 52-1 and 52-2 and a narrow-angle synthesizer 54. The shift register 52-1 takes in the output of the phase data converter 14, that is, the phase data, and supplies the output to the shift register 52-2 and the narrow-angle synthesizer 54. The shift register 52-2 outputs the output to the narrow-angle synthesizer 54.
Supply to. The shift clocks of the shift registers 52-1 and 52-2 are local oscillator signals of frequency f ₀ , and in this embodiment, the local oscillator signal A ₂ is used. Therefore, the shift timings of the shift registers 52-1 and 52-2 are synchronized. The two inputs to the narrow-angle synthesizer 54 result in
The phase data obtained by the phase data converter 14 becomes data of consecutive cycles (each 3 bits) obtained by synchronously shifting the phase data, and the narrow-angle combiner 54 combines these inputs and expands to 4 bits to output. To do. That is, the number of quantization bits is artificially expanded from 3 to 4 by outputting the narrow-angle intermediate value of both inputs with 4 bits.

Next, this operation, that is, the pseudo expansion of the number of quantization bits according to the feature of the present invention will be described. FIG. 3 shows an example of the configuration of the narrow-angle synthesizer 54, and FIG. 4 shows its operating principle.

The narrow-angle synthesizer 54 shown in FIG. 3 comprises an adder 56, a difference detector 58 and a selection circuit 60. The adder 56 includes shift registers 52-1 and 52.
The phase data is input from -2, added and output. The adder 56 has a bit configuration in which the carry bit is MSB,
That is, the phase data as the addition result is output in a 4-bit configuration in which 1 bit is added to 3 bits.

The 3-bit phase data can be grasped as indicated by the numbers inside the circle in FIG.
That is, the phase data “000” indicates that the phase difference between the PSK modulated wave and the local oscillation signal A ₂ is in the range of 0 ° to 45 °, “001” indicates the phase difference of 45 ° to 90 °, and so on. As described above, the 3-bit phase data corresponds to the phase difference between the PSK modulated wave and the local oscillation signal A ₂ .

On the other hand, the value obtained by adding the two inputs by the adder 56 and expanding it to 4 bits is equal to both values (except when the addition result has a phase difference exceeding 90 ° with the input as will be described later). It corresponds to a value obtained by shifting the input average value by 1 bit to the left. For example, the input from the shift register 52-1 is "0.
00 ”, the input from the shift register 52-2 is“ 00 ”
If it is "1", the output of the adder 56 becomes "0001", and the average value of "000" and "001" is "000.1".
Is shifted to the left by 1 bit. Also, the local signal A ₂
Phase data does not change at two consecutive falling edges of
The outputs of the shift registers 52-1 and 52-2 are both "0".
In the case of "00", the output of the adder 56 is "0000".

Therefore, except when the phase difference between the input to the adder 56 and the addition result exceeds 90 °, the output of the adder 56 is used as the phase data as it is in the circuit of the subsequent stage (the subtractor 16 and one symbol). By supplying it to the delay unit 18), the number of quantization bits can be expanded from 3 to 4 in a pseudo manner, so that the demodulation characteristic is improved. Further, since the number of quantization bits is not actually increased, the local master oscillator 10 which is determined according to the number of quantization bits is used.
The oscillating frequency m × f ₀ is low, and an increase in power consumption is prevented.

FIG. 4 shows the relationship between the outputs of the shift registers 52-1 and 52-2 and the output of the narrow-angle combiner 54 in this embodiment. As described above, the numbers in the inner circle are the shift registers 52-1 and 52-2.
3 shows the 3-bit phase data, and the outer circle shows 4-bit phase data after the pseudo expansion of the quantization bit number.

The case described above, that is, the adder 56
In the case where the phase difference between the input and the output is less than 90 °, the 4-bit data written at the intermediate position of the narrow angle formed by both phase data is the output of the adder 56. For example, "00
“0001” described in the middle (45 °) of the narrow angle formed by “0” and “001” is a value obtained by adding “000” and “001” and expanding to 4 bits.

However, in the case where the phase difference between the input and output of the adder 56 exceeds 90 °, the 4-bit data written at the intermediate position of the narrow angle formed by both phase data is added by the adder 5.
6 does not match the output. That is, if the output of the adder 56 is directly output from the phase data synthesizer 50, the output does not become the phase data corresponding to the intermediate value of the two phase data input to the adder 56, and the resolution of Does not contribute to improvement. In such a case, the adder 56
The output rotated by 180 ° corresponds to the 4-bit data described at the intermediate position of the narrow angle formed by both phase data.

An example will be described as follows.
When the phase data input from the shift register 52-1 to the adder 56 is “000” and the phase data input from the shift register 52-2 to the adder 56 is “111”,
When both are added and expanded to 4 bits, it becomes "0111". “0111” is written in the 180 ° direction in the figure, that is, in the wide-angle center direction formed by the phase data “000” and “111”. In this case, the center direction of the narrow angle is 0 °,
Phase data "111" obtained by rotating "0111" 180 degrees
1 "is the center direction of the phase data of the narrow angle. Therefore, the phase in the data converter 14 at the rise of the local oscillator signal A _2" "and phase data is obtained, the rising subsequent" 111 000 When the phase data of "" is obtained, the output of the adder 56 is rotated by 180 ° to obtain the phase data in the direction of the center of the narrow angle.

In such a situation that the phase data in the direction of the center of the narrow angle cannot be obtained without 180 ° inversion, there is generally a 90 ° phase difference between the input and the output of the adder 56. It happens when. Based on this, the narrow-angle synthesizer 54 in the present embodiment selects the output circuit of the adder 56 so as to switch between the output of the narrow-angle synthesizer 54 as it is or 180 ° rotation. Equipped with 60. Further, a difference detector 58 is provided as a configuration for outputting a signal for this switching.

The difference detector 58 inputs one of the inputs to the adder 56 and the output of the adder 56. The difference detector 58 detects the difference between the two inputs and supplies a signal indicating whether or not the absolute value exceeds 90 ° to the selection circuit 60. The selection circuit 60 outputs the output of the adder 56 as 4-bit phase data as it is in response to the signal indicating that the signal has exceeded the limit, and outputs 18 bits in response to the signal indicating that the signal has not exceeded.
The output is rotated by 0 ° (that is, the most significant bit is inverted).

Therefore, even when the phase difference between the input to the adder 56 and the addition result exceeds 90 °, the same effect as when it does not exceed can be obtained.

The present invention can also be applied to N-phase PSK and π / 4 shift QPSK demodulation circuits. In addition, although the configuration example from 3 bits to 4 bits has been shown, in general, the extension from M bits to M + N (M, N; natural numbers) is possible due to the relationship between the modulation wave frequency and the data transmission rate, and the process relationship. It goes without saying that you can do it. In FIG. 5, M = 4 and N = 2
As shown by the experimental result of, the present invention has a better demodulation characteristic closer to the theoretical value than the conventional one.

[0047]

As described above, according to the present invention, the number of quantization bits is artificially increased by adding the phase data at different timings and expanding the number of bits. That is, it is possible to realize a differential detection circuit having good demodulation characteristics with equivalent power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a differential detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a phase data synthesizer in this embodiment.

FIG. 3 is a block diagram showing a configuration of a narrow-angle synthesizer in the phase data synthesizer of this embodiment.

FIG. 4 is an operation explanatory diagram of a phase data synthesizer.

FIG. 5 is a diagram showing demodulation characteristics of the present invention.

FIG. 6 is a block diagram showing an example configuration of a conventional differential detection circuit.

FIG. 7 is a block diagram showing an example configuration of a phase data converter.

8 is a timing chart showing the operation of the phase data converter of FIG.

FIG. 9 is a block diagram showing another example configuration of the phase data converter.

10 is a timing chart showing the operation of the phase data converter of FIG.

[Explanation of symbols]

 10 Local Master Oscillator 12 Input Terminal 14 Phase Data Converter 16 Subtractor 18 1 Symbol Delayer 20 Frequency Error Corrector 22 Judgmentor 24 Output Terminal 26 Frequency Error Correction Circuit 28 Frequency Error Detection Circuit 30 Averaging Circuit 50 Phase Data Synthesizer 52-1 and 52-2 shift register 54 narrow-angle synthesizer 56 adder 58 difference detector 60 selection circuit

Claims (1)

[Claims] 1. A local master oscillator for outputting a local oscillation signal of a predetermined frequency, a phase data converter for converting a PSK modulated wave signal into M-bit (M; natural number) phase data by the local oscillation signal, and phase data A 1-symbol delay device that delays by 1 symbol time, a subtractor that compares phase data delayed by 1 symbol and phase data to obtain a change in the phase data in 1 symbol time, and outputs as a phase difference signal, In the differential detection circuit for differentially detecting the PSK modulated wave signal, the multiple phase data relating to different timings obtained by the phase data converter indicates the intermediate value of the phase data and M + N bits. Phase data composed of (N; natural number) and supplied to the 1-symbol delay unit and subtractor Delay detection circuit, characterized in that it comprises a combiner.